}
};
+/* Implements below instructions for frm
+ - vfsqrt
+*/
+template<rtx_code CODE>
+class unop_frm : public function_base
+{
+public:
+ bool has_rounding_mode_operand_p () const override { return true; }
+
+ rtx expand (function_expander &e) const override
+ {
+ return e.use_exact_insn (code_for_pred (CODE, e.vector_mode ()));
+ }
+};
+
/* Implements vrsub. */
class vrsub : public function_base
{
static CONSTEXPR const vfwnmsac vfwnmsac_obj;
static CONSTEXPR const vfwnmsac_frm vfwnmsac_frm_obj;
static CONSTEXPR const unop<SQRT> vfsqrt_obj;
+static CONSTEXPR const unop_frm<SQRT> vfsqrt_frm_obj;
static CONSTEXPR const float_misc<UNSPEC_VFRSQRT7> vfrsqrt7_obj;
static CONSTEXPR const float_misc<UNSPEC_VFREC7> vfrec7_obj;
static CONSTEXPR const binop<SMIN> vfmin_obj;
BASE (vfwnmsac)
BASE (vfwnmsac_frm)
BASE (vfsqrt)
+BASE (vfsqrt_frm)
BASE (vfrsqrt7)
BASE (vfrec7)
BASE (vfmin)
extern const function_base *const vfwnmsac;
extern const function_base *const vfwnmsac_frm;
extern const function_base *const vfsqrt;
+extern const function_base *const vfsqrt_frm;
extern const function_base *const vfrsqrt7;
extern const function_base *const vfrec7;
extern const function_base *const vfmin;
// 13.8. Vector Floating-Point Square-Root Instruction
DEF_RVV_FUNCTION (vfsqrt, alu, full_preds, f_v_ops)
+DEF_RVV_FUNCTION (vfsqrt_frm, alu_frm, full_preds, f_v_ops)
+
// 13.9. Vector Floating-Point Reciprocal Square-Root Estimate Instruction
DEF_RVV_FUNCTION (vfrsqrt7, alu, full_preds, f_v_ops)
--- /dev/null
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64 -O3 -Wno-psabi" } */
+
+#include "riscv_vector.h"
+
+typedef float float32_t;
+
+vfloat32m1_t
+test_riscv_vfsqrt_vv_f32m1_rm (vfloat32m1_t op1, size_t vl) {
+ return __riscv_vfsqrt_v_f32m1_rm (op1, 0, vl);
+}
+
+vfloat32m1_t
+test_vfsqrt_vv_f32m1_rm_m (vbool32_t mask, vfloat32m1_t op1, size_t vl) {
+ return __riscv_vfsqrt_v_f32m1_rm_m (mask, op1, 1, vl);
+}
+
+vfloat32m1_t
+test_riscv_vfsqrt_vv_f32m1 (vfloat32m1_t op1, size_t vl) {
+ return __riscv_vfsqrt_v_f32m1 (op1, vl);
+}
+
+vfloat32m1_t
+test_vfsqrt_vv_f32m1_m (vbool32_t mask, vfloat32m1_t op1, size_t vl) {
+ return __riscv_vfsqrt_v_f32m1_m (mask, op1, vl);
+}
+
+/* { dg-final { scan-assembler-times {vfsqrt\.v\s+v[0-9]+,\s*v[0-9]+} 4 } } */
+/* { dg-final { scan-assembler-times {frrm\s+[axs][0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {fsrm\s+[axs][0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {fsrmi\s+[01234]} 2 } } */