arm: improve tests and fix vsubq*

gcc/ChangeLog:

	* config/arm/mve.md (mve_vsubq_n_f<mode>): Fix spacing.

gcc/testsuite/ChangeLog:

	* gcc.target/arm/mve/intrinsics/vsubq_f16.c: Improve test.
	* gcc.target/arm/mve/intrinsics/vsubq_f32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vsubq_m_f16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vsubq_m_f32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vsubq_m_n_f16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vsubq_m_n_f32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vsubq_m_n_s16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vsubq_m_n_s32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vsubq_m_n_s8.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vsubq_m_n_u16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vsubq_m_n_u32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vsubq_m_n_u8.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vsubq_m_s16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vsubq_m_s32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vsubq_m_s8.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vsubq_m_u16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vsubq_m_u32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vsubq_m_u8.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vsubq_n_f16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vsubq_n_f32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vsubq_n_s16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vsubq_n_s32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vsubq_n_s8.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vsubq_n_u16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vsubq_n_u32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vsubq_n_u8.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vsubq_s16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vsubq_s32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vsubq_s8.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vsubq_u16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vsubq_u32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vsubq_u8.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vsubq_x_f16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vsubq_x_f32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vsubq_x_n_f16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vsubq_x_n_f32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vsubq_x_n_s16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vsubq_x_n_s32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vsubq_x_n_s8.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vsubq_x_n_u16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vsubq_x_n_u32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vsubq_x_n_u8.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vsubq_x_s16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vsubq_x_s32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vsubq_x_s8.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vsubq_x_u16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vsubq_x_u32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vsubq_x_u8.c: Likewise.

diff --git a/gcc/config/arm/mve.md b/gcc/config/arm/mve.md
index 5ce2a28922509c5fa27f5d44c241dececacbd27b..714dc6fc7ce3576f4ec8520b45891c9586a8e15b 100644 (file)
--- a/gcc/config/arm/mve.md
+++ b/gcc/config/arm/mve.md
@@ -679,7 +679,7 @@
         VSUBQ_N_F))
   ]
   "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
-  "vsub.f<V_sz_elem>  %q0, %q1, %2"
+  "vsub.f<V_sz_elem>\t%q0, %q1, %2"
   [(set_attr "type" "mve_move")
 ])
 

diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_f16.c
index 8e3ce24fa4942241e40b8d392ecb40714e980dad..3d82b081ca2edfb6a027ce2e3303d93fd5846065 100644 (file)
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_f16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_f16.c
@@ -1,21 +1,33 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**     ...
+**     vsub.f16        q[0-9]+, q[0-9]+, q[0-9]+(?:    @.*|)
+**     ...
+*/
 float16x8_t
 foo (float16x8_t a, float16x8_t b)
 {
   return vsubq_f16 (a, b);
 }
 
-/* { dg-final { scan-assembler "vsub.f16"  }  } */
 
+/*
+**foo1:
+**     ...
+**     vsub.f16        q[0-9]+, q[0-9]+, q[0-9]+(?:    @.*|)
+**     ...
+*/
 float16x8_t
 foo1 (float16x8_t a, float16x8_t b)
 {
   return vsubq (a, b);
 }
 
-/* { dg-final { scan-assembler "vsub.f16"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file

diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_f32.c
index 5cb239d70fa89c135d0c8eefb2f86592076d377c..d0f64bb98729eee8931db6af076570be26db90cc 100644 (file)
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_f32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_f32.c
@@ -1,21 +1,33 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**     ...
+**     vsub.f32        q[0-9]+, q[0-9]+, q[0-9]+(?:    @.*|)
+**     ...
+*/
 float32x4_t
 foo (float32x4_t a, float32x4_t b)
 {
   return vsubq_f32 (a, b);
 }
 
-/* { dg-final { scan-assembler "vsub.f32"  }  } */
 
+/*
+**foo1:
+**     ...
+**     vsub.f32        q[0-9]+, q[0-9]+, q[0-9]+(?:    @.*|)
+**     ...
+*/
 float32x4_t
 foo1 (float32x4_t a, float32x4_t b)
 {
   return vsubq (a, b);
 }
 
-/* { dg-final { scan-assembler "vsub.f32"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file

diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_m_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_m_f16.c
index f4b3f80682201f6470d7622dfcf32d1bd742411a..434b0a7ced8e4cbb48b21f6043a2e88c28c1f4c8 100644 (file)
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_m_f16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_m_f16.c
@@ -1,23 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**     ...
+**     vmsr    p0, (?:ip|fp|r[0-9]+)(?:        @.*|)
+**     ...
+**     vpst(?: @.*|)
+**     ...
+**     vsubt.f16       q[0-9]+, q[0-9]+, q[0-9]+(?:    @.*|)
+**     ...
+*/
 float16x8_t
 foo (float16x8_t inactive, float16x8_t a, float16x8_t b, mve_pred16_t p)
 {
   return vsubq_m_f16 (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vsubt.f16"  }  } */
 
+/*
+**foo1:
+**     ...
+**     vmsr    p0, (?:ip|fp|r[0-9]+)(?:        @.*|)
+**     ...
+**     vpst(?: @.*|)
+**     ...
+**     vsubt.f16       q[0-9]+, q[0-9]+, q[0-9]+(?:    @.*|)
+**     ...
+*/
 float16x8_t
 foo1 (float16x8_t inactive, float16x8_t a, float16x8_t b, mve_pred16_t p)
 {
   return vsubq_m (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vsubt.f16"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file

diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_m_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_m_f32.c
index 75dbf9335c97d2c87a9d8953866a2cd7d0b672ad..0b8e056647edeace92cfdca75c9e98ef96030bfe 100644 (file)
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_m_f32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_m_f32.c
@@ -1,23 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**     ...
+**     vmsr    p0, (?:ip|fp|r[0-9]+)(?:        @.*|)
+**     ...
+**     vpst(?: @.*|)
+**     ...
+**     vsubt.f32       q[0-9]+, q[0-9]+, q[0-9]+(?:    @.*|)
+**     ...
+*/
 float32x4_t
 foo (float32x4_t inactive, float32x4_t a, float32x4_t b, mve_pred16_t p)
 {
   return vsubq_m_f32 (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vsubt.f32"  }  } */
 
+/*
+**foo1:
+**     ...
+**     vmsr    p0, (?:ip|fp|r[0-9]+)(?:        @.*|)
+**     ...
+**     vpst(?: @.*|)
+**     ...
+**     vsubt.f32       q[0-9]+, q[0-9]+, q[0-9]+(?:    @.*|)
+**     ...
+*/
 float32x4_t
 foo1 (float32x4_t inactive, float32x4_t a, float32x4_t b, mve_pred16_t p)
 {
   return vsubq_m (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vsubt.f32"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file

diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_m_n_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_m_n_f16.c
index 556a0845087ee6bd5627bd5dfb49b6c8bfe3ea6b..abbd60060a76a49b6098a78d68b175ac05d92a9e 100644 (file)
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_m_n_f16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_m_n_f16.c
@@ -1,23 +1,57 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**     ...
+**     vmsr    p0, (?:ip|fp|r[0-9]+)(?:        @.*|)
+**     ...
+**     vpst(?: @.*|)
+**     ...
+**     vsubt.f16       q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:  @.*|)
+**     ...
+*/
 float16x8_t
 foo (float16x8_t inactive, float16x8_t a, float16_t b, mve_pred16_t p)
 {
   return vsubq_m_n_f16 (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vsubt.f16"  }  } */
 
+/*
+**foo1:
+**     ...
+**     vmsr    p0, (?:ip|fp|r[0-9]+)(?:        @.*|)
+**     ...
+**     vpst(?: @.*|)
+**     ...
+**     vsubt.f16       q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:  @.*|)
+**     ...
+*/
 float16x8_t
 foo1 (float16x8_t inactive, float16x8_t a, float16_t b, mve_pred16_t p)
 {
   return vsubq_m (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vsubt.f16"  }  } */
+/*
+**foo2:
+**     ...
+**     vmsr    p0, (?:ip|fp|r[0-9]+)(?:        @.*|)
+**     ...
+**     vpst(?: @.*|)
+**     ...
+**     vsubt.f16       q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:  @.*|)
+**     ...
+*/
+float16x8_t
+foo2 (float16x8_t inactive, float16x8_t a, mve_pred16_t p)
+{
+  return vsubq_m (inactive, a, 1.1, p);
+}
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file

diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_m_n_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_m_n_f32.c
index e53f5f1966a2fc9cce29337fa7f2f096a5285b88..40ca4284a1f66e4a7cdf7b659bb1199e6b2b4fe6 100644 (file)
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_m_n_f32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_m_n_f32.c
@@ -1,23 +1,57 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**     ...
+**     vmsr    p0, (?:ip|fp|r[0-9]+)(?:        @.*|)
+**     ...
+**     vpst(?: @.*|)
+**     ...
+**     vsubt.f32       q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:  @.*|)
+**     ...
+*/
 float32x4_t
 foo (float32x4_t inactive, float32x4_t a, float32_t b, mve_pred16_t p)
 {
   return vsubq_m_n_f32 (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vsubt.f32"  }  } */
 
+/*
+**foo1:
+**     ...
+**     vmsr    p0, (?:ip|fp|r[0-9]+)(?:        @.*|)
+**     ...
+**     vpst(?: @.*|)
+**     ...
+**     vsubt.f32       q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:  @.*|)
+**     ...
+*/
 float32x4_t
 foo1 (float32x4_t inactive, float32x4_t a, float32_t b, mve_pred16_t p)
 {
   return vsubq_m (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vsubt.f32"  }  } */
+/*
+**foo2:
+**     ...
+**     vmsr    p0, (?:ip|fp|r[0-9]+)(?:        @.*|)
+**     ...
+**     vpst(?: @.*|)
+**     ...
+**     vsubt.f32       q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:  @.*|)
+**     ...
+*/
+float32x4_t
+foo2 (float32x4_t inactive, float32x4_t a, mve_pred16_t p)
+{
+  return vsubq_m (inactive, a, 1.1, p);
+}
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file

diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_m_n_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_m_n_s16.c
index 73443d500ba062b5b55c7ee30207e763b2e18e6f..f13eff8ad2d9e42ba57e199166714e5b97e0adb6 100644 (file)
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_m_n_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_m_n_s16.c
@@ -1,23 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**     ...
+**     vmsr    p0, (?:ip|fp|r[0-9]+)(?:        @.*|)
+**     ...
+**     vpst(?: @.*|)
+**     ...
+**     vsubt.i16       q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:  @.*|)
+**     ...
+*/
 int16x8_t
 foo (int16x8_t inactive, int16x8_t a, int16_t b, mve_pred16_t p)
 {
   return vsubq_m_n_s16 (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vsubt.i16"  }  } */
 
+/*
+**foo1:
+**     ...
+**     vmsr    p0, (?:ip|fp|r[0-9]+)(?:        @.*|)
+**     ...
+**     vpst(?: @.*|)
+**     ...
+**     vsubt.i16       q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:  @.*|)
+**     ...
+*/
 int16x8_t
 foo1 (int16x8_t inactive, int16x8_t a, int16_t b, mve_pred16_t p)
 {
   return vsubq_m (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vsubt.i16"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file

diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_m_n_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_m_n_s32.c
index b4031111678a369eb0edc45c4eac7b2a1afeebb0..21ba17ba86960647bc736aa1501731f277d64735 100644 (file)
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_m_n_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_m_n_s32.c
@@ -1,23 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**     ...
+**     vmsr    p0, (?:ip|fp|r[0-9]+)(?:        @.*|)
+**     ...
+**     vpst(?: @.*|)
+**     ...
+**     vsubt.i32       q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:  @.*|)
+**     ...
+*/
 int32x4_t
 foo (int32x4_t inactive, int32x4_t a, int32_t b, mve_pred16_t p)
 {
   return vsubq_m_n_s32 (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vsubt.i32"  }  } */
 
+/*
+**foo1:
+**     ...
+**     vmsr    p0, (?:ip|fp|r[0-9]+)(?:        @.*|)
+**     ...
+**     vpst(?: @.*|)
+**     ...
+**     vsubt.i32       q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:  @.*|)
+**     ...
+*/
 int32x4_t
 foo1 (int32x4_t inactive, int32x4_t a, int32_t b, mve_pred16_t p)
 {
   return vsubq_m (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vsubt.i32"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file

diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_m_n_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_m_n_s8.c
index 5c4e1019225dbb36d3f322d9c14d0b15d3bc459b..c75b8b5420da750e951eb8f1455c282696a0f9a5 100644 (file)
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_m_n_s8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_m_n_s8.c
@@ -1,23 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**     ...
+**     vmsr    p0, (?:ip|fp|r[0-9]+)(?:        @.*|)
+**     ...
+**     vpst(?: @.*|)
+**     ...
+**     vsubt.i8        q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:  @.*|)
+**     ...
+*/
 int8x16_t
 foo (int8x16_t inactive, int8x16_t a, int8_t b, mve_pred16_t p)
 {
   return vsubq_m_n_s8 (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vsubt.i8"  }  } */
 
+/*
+**foo1:
+**     ...
+**     vmsr    p0, (?:ip|fp|r[0-9]+)(?:        @.*|)
+**     ...
+**     vpst(?: @.*|)
+**     ...
+**     vsubt.i8        q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:  @.*|)
+**     ...
+*/
 int8x16_t
 foo1 (int8x16_t inactive, int8x16_t a, int8_t b, mve_pred16_t p)
 {
   return vsubq_m (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vsubt.i8"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file

diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_m_n_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_m_n_u16.c
index 04a3036ede8458f23d994f621659520d0fb53500..700bc01833c4c25992349550162504fb421bf310 100644 (file)
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_m_n_u16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_m_n_u16.c
@@ -1,23 +1,57 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**     ...
+**     vmsr    p0, (?:ip|fp|r[0-9]+)(?:        @.*|)
+**     ...
+**     vpst(?: @.*|)
+**     ...
+**     vsubt.i16       q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:  @.*|)
+**     ...
+*/
 uint16x8_t
 foo (uint16x8_t inactive, uint16x8_t a, uint16_t b, mve_pred16_t p)
 {
   return vsubq_m_n_u16 (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vsubt.i16"  }  } */
 
+/*
+**foo1:
+**     ...
+**     vmsr    p0, (?:ip|fp|r[0-9]+)(?:        @.*|)
+**     ...
+**     vpst(?: @.*|)
+**     ...
+**     vsubt.i16       q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:  @.*|)
+**     ...
+*/
 uint16x8_t
 foo1 (uint16x8_t inactive, uint16x8_t a, uint16_t b, mve_pred16_t p)
 {
   return vsubq_m (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vsubt.i16"  }  } */
+/*
+**foo2:
+**     ...
+**     vmsr    p0, (?:ip|fp|r[0-9]+)(?:        @.*|)
+**     ...
+**     vpst(?: @.*|)
+**     ...
+**     vsubt.i16       q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:  @.*|)
+**     ...
+*/
+uint16x8_t
+foo2 (uint16x8_t inactive, uint16x8_t a, mve_pred16_t p)
+{
+  return vsubq_m (inactive, a, 1, p);
+}
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file

diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_m_n_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_m_n_u32.c
index a21f9366373621413493e1c218d54ded0f4912f2..25dd37ae5b2a9ad4ec22afb1dbad62c6173f7710 100644 (file)
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_m_n_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_m_n_u32.c
@@ -1,23 +1,57 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**     ...
+**     vmsr    p0, (?:ip|fp|r[0-9]+)(?:        @.*|)
+**     ...
+**     vpst(?: @.*|)
+**     ...
+**     vsubt.i32       q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:  @.*|)
+**     ...
+*/
 uint32x4_t
 foo (uint32x4_t inactive, uint32x4_t a, uint32_t b, mve_pred16_t p)
 {
   return vsubq_m_n_u32 (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vsubt.i32"  }  } */
 
+/*
+**foo1:
+**     ...
+**     vmsr    p0, (?:ip|fp|r[0-9]+)(?:        @.*|)
+**     ...
+**     vpst(?: @.*|)
+**     ...
+**     vsubt.i32       q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:  @.*|)
+**     ...
+*/
 uint32x4_t
 foo1 (uint32x4_t inactive, uint32x4_t a, uint32_t b, mve_pred16_t p)
 {
   return vsubq_m (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vsubt.i32"  }  } */
+/*
+**foo2:
+**     ...
+**     vmsr    p0, (?:ip|fp|r[0-9]+)(?:        @.*|)
+**     ...
+**     vpst(?: @.*|)
+**     ...
+**     vsubt.i32       q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:  @.*|)
+**     ...
+*/
+uint32x4_t
+foo2 (uint32x4_t inactive, uint32x4_t a, mve_pred16_t p)
+{
+  return vsubq_m (inactive, a, 1, p);
+}
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file

diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_m_n_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_m_n_u8.c
index 18f635f1e1a30e95e97eeff470fea03fa00c742f..4fed154d258199e7dbe051a0137388538c4d0926 100644 (file)
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_m_n_u8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_m_n_u8.c
@@ -1,23 +1,57 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**     ...
+**     vmsr    p0, (?:ip|fp|r[0-9]+)(?:        @.*|)
+**     ...
+**     vpst(?: @.*|)
+**     ...
+**     vsubt.i8        q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:  @.*|)
+**     ...
+*/
 uint8x16_t
 foo (uint8x16_t inactive, uint8x16_t a, uint8_t b, mve_pred16_t p)
 {
   return vsubq_m_n_u8 (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vsubt.i8"  }  } */
 
+/*
+**foo1:
+**     ...
+**     vmsr    p0, (?:ip|fp|r[0-9]+)(?:        @.*|)
+**     ...
+**     vpst(?: @.*|)
+**     ...
+**     vsubt.i8        q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:  @.*|)
+**     ...
+*/
 uint8x16_t
 foo1 (uint8x16_t inactive, uint8x16_t a, uint8_t b, mve_pred16_t p)
 {
   return vsubq_m (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vsubt.i8"  }  } */
+/*
+**foo2:
+**     ...
+**     vmsr    p0, (?:ip|fp|r[0-9]+)(?:        @.*|)
+**     ...
+**     vpst(?: @.*|)
+**     ...
+**     vsubt.i8        q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:  @.*|)
+**     ...
+*/
+uint8x16_t
+foo2 (uint8x16_t inactive, uint8x16_t a, mve_pred16_t p)
+{
+  return vsubq_m (inactive, a, 1, p);
+}
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file

diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_m_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_m_s16.c
index 598d648887be04b5913d2089fc5cf6ee9e4c5016..dde77dc51b792f5c4a6b796e58667240295431e9 100644 (file)
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_m_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_m_s16.c
@@ -1,22 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**     ...
+**     vmsr    p0, (?:ip|fp|r[0-9]+)(?:        @.*|)
+**     ...
+**     vpst(?: @.*|)
+**     ...
+**     vsubt.i16       q[0-9]+, q[0-9]+, q[0-9]+(?:    @.*|)
+**     ...
+*/
 int16x8_t
 foo (int16x8_t inactive, int16x8_t a, int16x8_t b, mve_pred16_t p)
 {
   return vsubq_m_s16 (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vsubt.i16"  }  } */
 
+/*
+**foo1:
+**     ...
+**     vmsr    p0, (?:ip|fp|r[0-9]+)(?:        @.*|)
+**     ...
+**     vpst(?: @.*|)
+**     ...
+**     vsubt.i16       q[0-9]+, q[0-9]+, q[0-9]+(?:    @.*|)
+**     ...
+*/
 int16x8_t
 foo1 (int16x8_t inactive, int16x8_t a, int16x8_t b, mve_pred16_t p)
 {
   return vsubq_m (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file

diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_m_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_m_s32.c
index af6750278f1707f5f338cd37e0509b6882343cd0..8770e31ad95d467b5181ccbbd5c49e3626911075 100644 (file)
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_m_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_m_s32.c
@@ -1,22 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**     ...
+**     vmsr    p0, (?:ip|fp|r[0-9]+)(?:        @.*|)
+**     ...
+**     vpst(?: @.*|)
+**     ...
+**     vsubt.i32       q[0-9]+, q[0-9]+, q[0-9]+(?:    @.*|)
+**     ...
+*/
 int32x4_t
 foo (int32x4_t inactive, int32x4_t a, int32x4_t b, mve_pred16_t p)
 {
   return vsubq_m_s32 (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vsubt.i32"  }  } */
 
+/*
+**foo1:
+**     ...
+**     vmsr    p0, (?:ip|fp|r[0-9]+)(?:        @.*|)
+**     ...
+**     vpst(?: @.*|)
+**     ...
+**     vsubt.i32       q[0-9]+, q[0-9]+, q[0-9]+(?:    @.*|)
+**     ...
+*/
 int32x4_t
 foo1 (int32x4_t inactive, int32x4_t a, int32x4_t b, mve_pred16_t p)
 {
   return vsubq_m (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file

diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_m_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_m_s8.c
index 5effbe2e01741d81fd72ad827dacf0cb4cadf712..c98133135944d7d5c16d4e02e44f2d735e49617f 100644 (file)
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_m_s8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_m_s8.c
@@ -1,22 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**     ...
+**     vmsr    p0, (?:ip|fp|r[0-9]+)(?:        @.*|)
+**     ...
+**     vpst(?: @.*|)
+**     ...
+**     vsubt.i8        q[0-9]+, q[0-9]+, q[0-9]+(?:    @.*|)
+**     ...
+*/
 int8x16_t
 foo (int8x16_t inactive, int8x16_t a, int8x16_t b, mve_pred16_t p)
 {
   return vsubq_m_s8 (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vsubt.i8"  }  } */
 
+/*
+**foo1:
+**     ...
+**     vmsr    p0, (?:ip|fp|r[0-9]+)(?:        @.*|)
+**     ...
+**     vpst(?: @.*|)
+**     ...
+**     vsubt.i8        q[0-9]+, q[0-9]+, q[0-9]+(?:    @.*|)
+**     ...
+*/
 int8x16_t
 foo1 (int8x16_t inactive, int8x16_t a, int8x16_t b, mve_pred16_t p)
 {
   return vsubq_m (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file

diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_m_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_m_u16.c
index 12218ae679115cfdbcbf0e5368e5f4945799b343..eebc3ad6929933a2e7e6d299602e3ded7e30aa44 100644 (file)
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_m_u16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_m_u16.c
@@ -1,22 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**     ...
+**     vmsr    p0, (?:ip|fp|r[0-9]+)(?:        @.*|)
+**     ...
+**     vpst(?: @.*|)
+**     ...
+**     vsubt.i16       q[0-9]+, q[0-9]+, q[0-9]+(?:    @.*|)
+**     ...
+*/
 uint16x8_t
 foo (uint16x8_t inactive, uint16x8_t a, uint16x8_t b, mve_pred16_t p)
 {
   return vsubq_m_u16 (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vsubt.i16"  }  } */
 
+/*
+**foo1:
+**     ...
+**     vmsr    p0, (?:ip|fp|r[0-9]+)(?:        @.*|)
+**     ...
+**     vpst(?: @.*|)
+**     ...
+**     vsubt.i16       q[0-9]+, q[0-9]+, q[0-9]+(?:    @.*|)
+**     ...
+*/
 uint16x8_t
 foo1 (uint16x8_t inactive, uint16x8_t a, uint16x8_t b, mve_pred16_t p)
 {
   return vsubq_m (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file

diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_m_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_m_u32.c
index 3a63eeb2b3da840c092a23587ba944c148979bfc..d85bbec7ebf2be3c695decfc111622b3e24f2710 100644 (file)
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_m_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_m_u32.c
@@ -1,22 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**     ...
+**     vmsr    p0, (?:ip|fp|r[0-9]+)(?:        @.*|)
+**     ...
+**     vpst(?: @.*|)
+**     ...
+**     vsubt.i32       q[0-9]+, q[0-9]+, q[0-9]+(?:    @.*|)
+**     ...
+*/
 uint32x4_t
 foo (uint32x4_t inactive, uint32x4_t a, uint32x4_t b, mve_pred16_t p)
 {
   return vsubq_m_u32 (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vsubt.i32"  }  } */
 
+/*
+**foo1:
+**     ...
+**     vmsr    p0, (?:ip|fp|r[0-9]+)(?:        @.*|)
+**     ...
+**     vpst(?: @.*|)
+**     ...
+**     vsubt.i32       q[0-9]+, q[0-9]+, q[0-9]+(?:    @.*|)
+**     ...
+*/
 uint32x4_t
 foo1 (uint32x4_t inactive, uint32x4_t a, uint32x4_t b, mve_pred16_t p)
 {
   return vsubq_m (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file

diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_m_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_m_u8.c
index a17a2741a47f015b3699e9c1f606edf3b46bd380..a104a74e2590d5de169affc7ffa4fdff9cbf7f23 100644 (file)
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_m_u8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_m_u8.c
@@ -1,22 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**     ...
+**     vmsr    p0, (?:ip|fp|r[0-9]+)(?:        @.*|)
+**     ...
+**     vpst(?: @.*|)
+**     ...
+**     vsubt.i8        q[0-9]+, q[0-9]+, q[0-9]+(?:    @.*|)
+**     ...
+*/
 uint8x16_t
 foo (uint8x16_t inactive, uint8x16_t a, uint8x16_t b, mve_pred16_t p)
 {
   return vsubq_m_u8 (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vsubt.i8"  }  } */
 
+/*
+**foo1:
+**     ...
+**     vmsr    p0, (?:ip|fp|r[0-9]+)(?:        @.*|)
+**     ...
+**     vpst(?: @.*|)
+**     ...
+**     vsubt.i8        q[0-9]+, q[0-9]+, q[0-9]+(?:    @.*|)
+**     ...
+*/
 uint8x16_t
 foo1 (uint8x16_t inactive, uint8x16_t a, uint8x16_t b, mve_pred16_t p)
 {
   return vsubq_m (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file

diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_n_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_n_f16.c
index 10e27dae907c0eee7264c234a6c7850aaf948f80..4db52649ab498140b188de171d4f0f3db33b6563 100644 (file)
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_n_f16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_n_f16.c
@@ -1,21 +1,45 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**     ...
+**     vsub.f16        q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:  @.*|)
+**     ...
+*/
 float16x8_t
 foo (float16x8_t a, float16_t b)
 {
   return vsubq_n_f16 (a, b);
 }
 
-/* { dg-final { scan-assembler "vsub.f16"  }  } */
 
+/*
+**foo1:
+**     ...
+**     vsub.f16        q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:  @.*|)
+**     ...
+*/
 float16x8_t
 foo1 (float16x8_t a, float16_t b)
 {
   return vsubq (a, b);
 }
 
-/* { dg-final { scan-assembler "vsub.f16"  }  } */
+/*
+**foo2:
+**     ...
+**     vsub.f16        q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:  @.*|)
+**     ...
+*/
+float16x8_t
+foo2 (float16x8_t a)
+{
+  return vsubq (a, 1.1);
+}
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file

diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_n_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_n_f32.c
index 9e16d6c075c7089ff4c1f1b3d02b3cc6fe1c6380..fe97eed7d3717d04740d1c39046400b0bf1ba218 100644 (file)
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_n_f32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_n_f32.c
@@ -1,21 +1,45 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**     ...
+**     vsub.f32        q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:  @.*|)
+**     ...
+*/
 float32x4_t
 foo (float32x4_t a, float32_t b)
 {
   return vsubq_n_f32 (a, b);
 }
 
-/* { dg-final { scan-assembler "vsub.f32"  }  } */
 
+/*
+**foo1:
+**     ...
+**     vsub.f32        q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:  @.*|)
+**     ...
+*/
 float32x4_t
 foo1 (float32x4_t a, float32_t b)
 {
   return vsubq (a, b);
 }
 
-/* { dg-final { scan-assembler "vsub.f32"  }  } */
+/*
+**foo2:
+**     ...
+**     vsub.f32        q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:  @.*|)
+**     ...
+*/
+float32x4_t
+foo2 (float32x4_t a)
+{
+  return vsubq (a, 1.1);
+}
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file

diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_n_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_n_s16.c
index 7f2af8691c005c53732267314ad982c964bbe07e..d695fc83e06bfeb878c28b27fb4e90e3dc22d27f 100644 (file)
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_n_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_n_s16.c
@@ -1,22 +1,33 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
-/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**     ...
+**     vsub.i16        q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:  @.*|)
+**     ...
+*/
 int16x8_t
 foo (int16x8_t a, int16_t b)
 {
   return vsubq_n_s16 (a, b);
 }
 
-/* { dg-final { scan-assembler "vsub.i16"  }  } */
 
+/*
+**foo1:
+**     ...
+**     vsub.i16        q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:  @.*|)
+**     ...
+*/
 int16x8_t
 foo1 (int16x8_t a, int16_t b)
 {
   return vsubq (a, b);
 }
 
-/* { dg-final { scan-assembler "vsub.i16"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file

diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_n_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_n_s32.c
index a5e6bf486fd6803628a4e995af0a6ca5a9043fe6..c281e21ab0cfdee75521acceef9abe48349a985f 100644 (file)
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_n_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_n_s32.c
@@ -1,22 +1,33 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
-/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**     ...
+**     vsub.i32        q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:  @.*|)
+**     ...
+*/
 int32x4_t
 foo (int32x4_t a, int32_t b)
 {
   return vsubq_n_s32 (a, b);
 }
 
-/* { dg-final { scan-assembler "vsub.i32"  }  } */
 
+/*
+**foo1:
+**     ...
+**     vsub.i32        q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:  @.*|)
+**     ...
+*/
 int32x4_t
 foo1 (int32x4_t a, int32_t b)
 {
   return vsubq (a, b);
 }
 
-/* { dg-final { scan-assembler "vsub.i32"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file

diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_n_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_n_s8.c
index 5754379358db5f4040bebbe3c13b19030897d8d8..ef36b4d6330d0f89d771d3f52f2e1cde104340cf 100644 (file)
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_n_s8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_n_s8.c
@@ -1,22 +1,33 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
-/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**     ...
+**     vsub.i8 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:  @.*|)
+**     ...
+*/
 int8x16_t
 foo (int8x16_t a, int8_t b)
 {
   return vsubq_n_s8 (a, b);
 }
 
-/* { dg-final { scan-assembler "vsub.i8"  }  } */
 
+/*
+**foo1:
+**     ...
+**     vsub.i8 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:  @.*|)
+**     ...
+*/
 int8x16_t
 foo1 (int8x16_t a, int8_t b)
 {
   return vsubq (a, b);
 }
 
-/* { dg-final { scan-assembler "vsub.i8"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file

diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_n_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_n_u16.c
index ea0a3f9260c51729816022be0c903bfa786989ce..be754d894a8d3b8fa16c2572ecd7528c35026713 100644 (file)
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_n_u16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_n_u16.c
@@ -1,22 +1,45 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
-/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**     ...
+**     vsub.i16        q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:  @.*|)
+**     ...
+*/
 uint16x8_t
 foo (uint16x8_t a, uint16_t b)
 {
   return vsubq_n_u16 (a, b);
 }
 
-/* { dg-final { scan-assembler "vsub.i16"  }  } */
 
+/*
+**foo1:
+**     ...
+**     vsub.i16        q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:  @.*|)
+**     ...
+*/
 uint16x8_t
 foo1 (uint16x8_t a, uint16_t b)
 {
   return vsubq (a, b);
 }
 
-/* { dg-final { scan-assembler "vsub.i16"  }  } */
+/*
+**foo2:
+**     ...
+**     vsub.i16        q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:  @.*|)
+**     ...
+*/
+uint16x8_t
+foo2 (uint16x8_t a)
+{
+  return vsubq (a, 1);
+}
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file

diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_n_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_n_u32.c
index cc409b59438dfe8792830731515540ae80ccd40e..ef0aaa4cf08b90fc48c4fa8801c3c56863b6d309 100644 (file)
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_n_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_n_u32.c
@@ -1,22 +1,45 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
-/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**     ...
+**     vsub.i32        q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:  @.*|)
+**     ...
+*/
 uint32x4_t
 foo (uint32x4_t a, uint32_t b)
 {
   return vsubq_n_u32 (a, b);
 }
 
-/* { dg-final { scan-assembler "vsub.i32"  }  } */
 
+/*
+**foo1:
+**     ...
+**     vsub.i32        q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:  @.*|)
+**     ...
+*/
 uint32x4_t
 foo1 (uint32x4_t a, uint32_t b)
 {
   return vsubq (a, b);
 }
 
-/* { dg-final { scan-assembler "vsub.i32"  }  } */
+/*
+**foo2:
+**     ...
+**     vsub.i32        q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:  @.*|)
+**     ...
+*/
+uint32x4_t
+foo2 (uint32x4_t a)
+{
+  return vsubq (a, 1);
+}
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file

diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_n_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_n_u8.c
index 8a18a89b35341a6735129bd174a6cc9610eb8b12..c55aefc3307670f2557c13dc7a775f62516269e3 100644 (file)
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_n_u8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_n_u8.c
@@ -1,22 +1,45 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
-/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**     ...
+**     vsub.i8 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:  @.*|)
+**     ...
+*/
 uint8x16_t
 foo (uint8x16_t a, uint8_t b)
 {
   return vsubq_n_u8 (a, b);
 }
 
-/* { dg-final { scan-assembler "vsub.i8"  }  } */
 
+/*
+**foo1:
+**     ...
+**     vsub.i8 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:  @.*|)
+**     ...
+*/
 uint8x16_t
 foo1 (uint8x16_t a, uint8_t b)
 {
   return vsubq (a, b);
 }
 
-/* { dg-final { scan-assembler "vsub.i8"  }  } */
+/*
+**foo2:
+**     ...
+**     vsub.i8 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:  @.*|)
+**     ...
+*/
+uint8x16_t
+foo2 (uint8x16_t a)
+{
+  return vsubq (a, 1);
+}
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file

diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_s16.c
index 15e732f1f66cfabbfa775bdd5af4899fe90855c1..469395452bdc1025ca5689f4d3b0ec9b2b33cc45 100644 (file)
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_s16.c
@@ -1,21 +1,33 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**     ...
+**     vsub.i16        q[0-9]+, q[0-9]+, q[0-9]+(?:    @.*|)
+**     ...
+*/
 int16x8_t
 foo (int16x8_t a, int16x8_t b)
 {
   return vsubq_s16 (a, b);
 }
 
-/* { dg-final { scan-assembler "vsub.i16"  }  } */
 
+/*
+**foo1:
+**     ...
+**     vsub.i16        q[0-9]+, q[0-9]+, q[0-9]+(?:    @.*|)
+**     ...
+*/
 int16x8_t
 foo1 (int16x8_t a, int16x8_t b)
 {
   return vsubq (a, b);
 }
 
-/* { dg-final { scan-assembler "vsub.i16"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file

diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_s32.c
index 5b4ee855711e779f5a7b25da2c4b4126917bed29..0e60e1c6f60a620f48423c3e088576d7ae461971 100644 (file)
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_s32.c
@@ -1,21 +1,33 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**     ...
+**     vsub.i32        q[0-9]+, q[0-9]+, q[0-9]+(?:    @.*|)
+**     ...
+*/
 int32x4_t
 foo (int32x4_t a, int32x4_t b)
 {
   return vsubq_s32 (a, b);
 }
 
-/* { dg-final { scan-assembler "vsub.i32"  }  } */
 
+/*
+**foo1:
+**     ...
+**     vsub.i32        q[0-9]+, q[0-9]+, q[0-9]+(?:    @.*|)
+**     ...
+*/
 int32x4_t
 foo1 (int32x4_t a, int32x4_t b)
 {
   return vsubq (a, b);
 }
 
-/* { dg-final { scan-assembler "vsub.i32"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file

diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_s8.c
index b23893af605d28f8f9debfc57017695612ee4908..882d63dfcf7301c9048691d125855a4849c44459 100644 (file)
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_s8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_s8.c
@@ -1,21 +1,33 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**     ...
+**     vsub.i8 q[0-9]+, q[0-9]+, q[0-9]+(?:    @.*|)
+**     ...
+*/
 int8x16_t
 foo (int8x16_t a, int8x16_t b)
 {
   return vsubq_s8 (a, b);
 }
 
-/* { dg-final { scan-assembler "vsub.i8"  }  } */
 
+/*
+**foo1:
+**     ...
+**     vsub.i8 q[0-9]+, q[0-9]+, q[0-9]+(?:    @.*|)
+**     ...
+*/
 int8x16_t
 foo1 (int8x16_t a, int8x16_t b)
 {
   return vsubq (a, b);
 }
 
-/* { dg-final { scan-assembler "vsub.i8"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file

diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_u16.c
index edb5e354411f55ce0973f97d98b0a83319e7826e..fe9baf3d52cb44cecec01340efcf7e7b9aa8c8e8 100644 (file)
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_u16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_u16.c
@@ -1,21 +1,33 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**     ...
+**     vsub.i16        q[0-9]+, q[0-9]+, q[0-9]+(?:    @.*|)
+**     ...
+*/
 uint16x8_t
 foo (uint16x8_t a, uint16x8_t b)
 {
   return vsubq_u16 (a, b);
 }
 
-/* { dg-final { scan-assembler "vsub.i16"  }  } */
 
+/*
+**foo1:
+**     ...
+**     vsub.i16        q[0-9]+, q[0-9]+, q[0-9]+(?:    @.*|)
+**     ...
+*/
 uint16x8_t
 foo1 (uint16x8_t a, uint16x8_t b)
 {
   return vsubq (a, b);
 }
 
-/* { dg-final { scan-assembler "vsub.i16"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file

diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_u32.c
index 68040afd52b8b2ee15b354ca8d490fe10c5a7ed5..b82051d69d51f2ff84c8652f70bd9fad05c74433 100644 (file)
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_u32.c
@@ -1,21 +1,33 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**     ...
+**     vsub.i32        q[0-9]+, q[0-9]+, q[0-9]+(?:    @.*|)
+**     ...
+*/
 uint32x4_t
 foo (uint32x4_t a, uint32x4_t b)
 {
   return vsubq_u32 (a, b);
 }
 
-/* { dg-final { scan-assembler "vsub.i32"  }  } */
 
+/*
+**foo1:
+**     ...
+**     vsub.i32        q[0-9]+, q[0-9]+, q[0-9]+(?:    @.*|)
+**     ...
+*/
 uint32x4_t
 foo1 (uint32x4_t a, uint32x4_t b)
 {
   return vsubq (a, b);
 }
 
-/* { dg-final { scan-assembler "vsub.i32"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file

diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_u8.c
index 92c4f059b0e24e5212aee0d492d4b58e2475ed1c..630b2f79f1fd7dc6a533defd474e0e38774df0b2 100644 (file)
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_u8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_u8.c
@@ -1,21 +1,33 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**     ...
+**     vsub.i8 q[0-9]+, q[0-9]+, q[0-9]+(?:    @.*|)
+**     ...
+*/
 uint8x16_t
 foo (uint8x16_t a, uint8x16_t b)
 {
   return vsubq_u8 (a, b);
 }
 
-/* { dg-final { scan-assembler "vsub.i8"  }  } */
 
+/*
+**foo1:
+**     ...
+**     vsub.i8 q[0-9]+, q[0-9]+, q[0-9]+(?:    @.*|)
+**     ...
+*/
 uint8x16_t
 foo1 (uint8x16_t a, uint8x16_t b)
 {
   return vsubq (a, b);
 }
 
-/* { dg-final { scan-assembler "vsub.i8"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file

diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_x_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_x_f16.c
index 4cb8be0ea7fd1e306d2da6f55888efc5e2f33ab3..c48bea7e9f04ffedc0f51e03bbde27181adf0ca5 100644 (file)
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_x_f16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_x_f16.c
@@ -1,15 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**     ...
+**     vmsr    p0, (?:ip|fp|r[0-9]+)(?:        @.*|)
+**     ...
+**     vpst(?: @.*|)
+**     ...
+**     vsubt.f16       q[0-9]+, q[0-9]+, q[0-9]+(?:    @.*|)
+**     ...
+*/
 float16x8_t
 foo (float16x8_t a, float16x8_t b, mve_pred16_t p)
 {
-    return vsubq_x_f16 (a, b, p);
+  return vsubq_x_f16 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vsubt.f16"  }  } */
 
+/*
+**foo1:
+**     ...
+**     vmsr    p0, (?:ip|fp|r[0-9]+)(?:        @.*|)
+**     ...
+**     vpst(?: @.*|)
+**     ...
+**     vsubt.f16       q[0-9]+, q[0-9]+, q[0-9]+(?:    @.*|)
+**     ...
+*/
+float16x8_t
+foo1 (float16x8_t a, float16x8_t b, mve_pred16_t p)
+{
+  return vsubq_x (a, b, p);
+}
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file

diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_x_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_x_f32.c
index f6711d7f20735bc4e071e2177265e545d57bf9d3..d3e129bb6ee1f0e61b1f12ba4f3693c6c65f5746 100644 (file)
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_x_f32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_x_f32.c
@@ -1,15 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**     ...
+**     vmsr    p0, (?:ip|fp|r[0-9]+)(?:        @.*|)
+**     ...
+**     vpst(?: @.*|)
+**     ...
+**     vsubt.f32       q[0-9]+, q[0-9]+, q[0-9]+(?:    @.*|)
+**     ...
+*/
 float32x4_t
 foo (float32x4_t a, float32x4_t b, mve_pred16_t p)
 {
-    return vsubq_x_f32 (a, b, p);
+  return vsubq_x_f32 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vsubt.f32"  }  } */
 
+/*
+**foo1:
+**     ...
+**     vmsr    p0, (?:ip|fp|r[0-9]+)(?:        @.*|)
+**     ...
+**     vpst(?: @.*|)
+**     ...
+**     vsubt.f32       q[0-9]+, q[0-9]+, q[0-9]+(?:    @.*|)
+**     ...
+*/
+float32x4_t
+foo1 (float32x4_t a, float32x4_t b, mve_pred16_t p)
+{
+  return vsubq_x (a, b, p);
+}
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file

diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_x_n_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_x_n_f16.c
index c4adacbf5bee9ac10016a5984c2f462aa31073c7..2dcaff58c096601243b0db78c1a9717359463ff1 100644 (file)
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_x_n_f16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_x_n_f16.c
@@ -1,15 +1,57 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**     ...
+**     vmsr    p0, (?:ip|fp|r[0-9]+)(?:        @.*|)
+**     ...
+**     vpst(?: @.*|)
+**     ...
+**     vsubt.f16       q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:  @.*|)
+**     ...
+*/
 float16x8_t
 foo (float16x8_t a, float16_t b, mve_pred16_t p)
 {
-    return vsubq_x_n_f16 (a, b, p);
+  return vsubq_x_n_f16 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vsubt.f16"  }  } */
 
+/*
+**foo1:
+**     ...
+**     vmsr    p0, (?:ip|fp|r[0-9]+)(?:        @.*|)
+**     ...
+**     vpst(?: @.*|)
+**     ...
+**     vsubt.f16       q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:  @.*|)
+**     ...
+*/
+float16x8_t
+foo1 (float16x8_t a, float16_t b, mve_pred16_t p)
+{
+  return vsubq_x (a, b, p);
+}
+
+/*
+**foo2:
+**     ...
+**     vmsr    p0, (?:ip|fp|r[0-9]+)(?:        @.*|)
+**     ...
+**     vpst(?: @.*|)
+**     ...
+**     vsubt.f16       q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:  @.*|)
+**     ...
+*/
+float16x8_t
+foo2 (float16x8_t a, mve_pred16_t p)
+{
+  return vsubq_x (a, 1.1, p);
+}
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file

diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_x_n_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_x_n_f32.c
index a4affa0a3a9f47cd6b7228bfc24a84a2fbf79de7..92bafa3c4ccda6638e25ee4887a494cf2fd5fff6 100644 (file)
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_x_n_f32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_x_n_f32.c
@@ -1,15 +1,57 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**     ...
+**     vmsr    p0, (?:ip|fp|r[0-9]+)(?:        @.*|)
+**     ...
+**     vpst(?: @.*|)
+**     ...
+**     vsubt.f32       q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:  @.*|)
+**     ...
+*/
 float32x4_t
 foo (float32x4_t a, float32_t b, mve_pred16_t p)
 {
-    return vsubq_x_n_f32 (a, b, p);
+  return vsubq_x_n_f32 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vsubt.f32"  }  } */
 
+/*
+**foo1:
+**     ...
+**     vmsr    p0, (?:ip|fp|r[0-9]+)(?:        @.*|)
+**     ...
+**     vpst(?: @.*|)
+**     ...
+**     vsubt.f32       q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:  @.*|)
+**     ...
+*/
+float32x4_t
+foo1 (float32x4_t a, float32_t b, mve_pred16_t p)
+{
+  return vsubq_x (a, b, p);
+}
+
+/*
+**foo2:
+**     ...
+**     vmsr    p0, (?:ip|fp|r[0-9]+)(?:        @.*|)
+**     ...
+**     vpst(?: @.*|)
+**     ...
+**     vsubt.f32       q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:  @.*|)
+**     ...
+*/
+float32x4_t
+foo2 (float32x4_t a, mve_pred16_t p)
+{
+  return vsubq_x (a, 1.1, p);
+}
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file

diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_x_n_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_x_n_s16.c
index 99c59b1a6c13ed2082b7976c3fd810e4f609e4be..f01e8d7d4908dd67e0cb60e0ed04eecb54c76121 100644 (file)
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_x_n_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_x_n_s16.c
@@ -1,15 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**     ...
+**     vmsr    p0, (?:ip|fp|r[0-9]+)(?:        @.*|)
+**     ...
+**     vpst(?: @.*|)
+**     ...
+**     vsubt.i16       q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:  @.*|)
+**     ...
+*/
 int16x8_t
 foo (int16x8_t a, int16_t b, mve_pred16_t p)
 {
-    return vsubq_x_n_s16 (a, b, p);
+  return vsubq_x_n_s16 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vsubt.i16"  }  } */
 
+/*
+**foo1:
+**     ...
+**     vmsr    p0, (?:ip|fp|r[0-9]+)(?:        @.*|)
+**     ...
+**     vpst(?: @.*|)
+**     ...
+**     vsubt.i16       q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:  @.*|)
+**     ...
+*/
+int16x8_t
+foo1 (int16x8_t a, int16_t b, mve_pred16_t p)
+{
+  return vsubq_x (a, b, p);
+}
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file

diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_x_n_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_x_n_s32.c
index 6c29ebec05c74bf4ce406fc5e9aaa8acb1dab48a..506966424cc5a21f907cefa0a31bf549c0a0bdd0 100644 (file)
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_x_n_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_x_n_s32.c
@@ -1,15 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**     ...
+**     vmsr    p0, (?:ip|fp|r[0-9]+)(?:        @.*|)
+**     ...
+**     vpst(?: @.*|)
+**     ...
+**     vsubt.i32       q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:  @.*|)
+**     ...
+*/
 int32x4_t
 foo (int32x4_t a, int32_t b, mve_pred16_t p)
 {
-    return vsubq_x_n_s32 (a, b, p);
+  return vsubq_x_n_s32 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vsubt.i32"  }  } */
 
+/*
+**foo1:
+**     ...
+**     vmsr    p0, (?:ip|fp|r[0-9]+)(?:        @.*|)
+**     ...
+**     vpst(?: @.*|)
+**     ...
+**     vsubt.i32       q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:  @.*|)
+**     ...
+*/
+int32x4_t
+foo1 (int32x4_t a, int32_t b, mve_pred16_t p)
+{
+  return vsubq_x (a, b, p);
+}
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file

diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_x_n_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_x_n_s8.c
index 0f83c3054731293300896a7fefc016e6fe934603..3c4a5d8129c073cb2b7ffa024463e76fa3329642 100644 (file)
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_x_n_s8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_x_n_s8.c
@@ -1,15 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**     ...
+**     vmsr    p0, (?:ip|fp|r[0-9]+)(?:        @.*|)
+**     ...
+**     vpst(?: @.*|)
+**     ...
+**     vsubt.i8        q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:  @.*|)
+**     ...
+*/
 int8x16_t
 foo (int8x16_t a, int8_t b, mve_pred16_t p)
 {
-    return vsubq_x_n_s8 (a, b, p);
+  return vsubq_x_n_s8 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vsubt.i8"  }  } */
 
+/*
+**foo1:
+**     ...
+**     vmsr    p0, (?:ip|fp|r[0-9]+)(?:        @.*|)
+**     ...
+**     vpst(?: @.*|)
+**     ...
+**     vsubt.i8        q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:  @.*|)
+**     ...
+*/
+int8x16_t
+foo1 (int8x16_t a, int8_t b, mve_pred16_t p)
+{
+  return vsubq_x (a, b, p);
+}
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file

diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_x_n_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_x_n_u16.c
index 9a372d762d1a906800e8944d883ad56624c4be05..958e5aa2ce84d5548486d6ed5c6e20adc8f1dc27 100644 (file)
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_x_n_u16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_x_n_u16.c
@@ -1,15 +1,57 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**     ...
+**     vmsr    p0, (?:ip|fp|r[0-9]+)(?:        @.*|)
+**     ...
+**     vpst(?: @.*|)
+**     ...
+**     vsubt.i16       q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:  @.*|)
+**     ...
+*/
 uint16x8_t
 foo (uint16x8_t a, uint16_t b, mve_pred16_t p)
 {
-    return vsubq_x_n_u16 (a, b, p);
+  return vsubq_x_n_u16 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vsubt.i16"  }  } */
 
+/*
+**foo1:
+**     ...
+**     vmsr    p0, (?:ip|fp|r[0-9]+)(?:        @.*|)
+**     ...
+**     vpst(?: @.*|)
+**     ...
+**     vsubt.i16       q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:  @.*|)
+**     ...
+*/
+uint16x8_t
+foo1 (uint16x8_t a, uint16_t b, mve_pred16_t p)
+{
+  return vsubq_x (a, b, p);
+}
+
+/*
+**foo2:
+**     ...
+**     vmsr    p0, (?:ip|fp|r[0-9]+)(?:        @.*|)
+**     ...
+**     vpst(?: @.*|)
+**     ...
+**     vsubt.i16       q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:  @.*|)
+**     ...
+*/
+uint16x8_t
+foo2 (uint16x8_t a, mve_pred16_t p)
+{
+  return vsubq_x (a, 1, p);
+}
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file

diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_x_n_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_x_n_u32.c
index 5219f154fa9872f3b3d9bf35119792f122d2d2f1..ba39c75bb2b9efb8f1eca80e719eb0e0a6e8e86a 100644 (file)
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_x_n_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_x_n_u32.c
@@ -1,15 +1,57 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**     ...
+**     vmsr    p0, (?:ip|fp|r[0-9]+)(?:        @.*|)
+**     ...
+**     vpst(?: @.*|)
+**     ...
+**     vsubt.i32       q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:  @.*|)
+**     ...
+*/
 uint32x4_t
 foo (uint32x4_t a, uint32_t b, mve_pred16_t p)
 {
-    return vsubq_x_n_u32 (a, b, p);
+  return vsubq_x_n_u32 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vsubt.i32"  }  } */
 
+/*
+**foo1:
+**     ...
+**     vmsr    p0, (?:ip|fp|r[0-9]+)(?:        @.*|)
+**     ...
+**     vpst(?: @.*|)
+**     ...
+**     vsubt.i32       q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:  @.*|)
+**     ...
+*/
+uint32x4_t
+foo1 (uint32x4_t a, uint32_t b, mve_pred16_t p)
+{
+  return vsubq_x (a, b, p);
+}
+
+/*
+**foo2:
+**     ...
+**     vmsr    p0, (?:ip|fp|r[0-9]+)(?:        @.*|)
+**     ...
+**     vpst(?: @.*|)
+**     ...
+**     vsubt.i32       q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:  @.*|)
+**     ...
+*/
+uint32x4_t
+foo2 (uint32x4_t a, mve_pred16_t p)
+{
+  return vsubq_x (a, 1, p);
+}
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file

diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_x_n_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_x_n_u8.c
index 0a0bcf8623ad493d6b9ea5c61dcd56ed3bd3a80a..19204d1d80fd9615cbbb727cd0255babf773ecf5 100644 (file)
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_x_n_u8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_x_n_u8.c
@@ -1,15 +1,57 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**     ...
+**     vmsr    p0, (?:ip|fp|r[0-9]+)(?:        @.*|)
+**     ...
+**     vpst(?: @.*|)
+**     ...
+**     vsubt.i8        q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:  @.*|)
+**     ...
+*/
 uint8x16_t
 foo (uint8x16_t a, uint8_t b, mve_pred16_t p)
 {
-    return vsubq_x_n_u8 (a, b, p);
+  return vsubq_x_n_u8 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vsubt.i8"  }  } */
 
+/*
+**foo1:
+**     ...
+**     vmsr    p0, (?:ip|fp|r[0-9]+)(?:        @.*|)
+**     ...
+**     vpst(?: @.*|)
+**     ...
+**     vsubt.i8        q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:  @.*|)
+**     ...
+*/
+uint8x16_t
+foo1 (uint8x16_t a, uint8_t b, mve_pred16_t p)
+{
+  return vsubq_x (a, b, p);
+}
+
+/*
+**foo2:
+**     ...
+**     vmsr    p0, (?:ip|fp|r[0-9]+)(?:        @.*|)
+**     ...
+**     vpst(?: @.*|)
+**     ...
+**     vsubt.i8        q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:  @.*|)
+**     ...
+*/
+uint8x16_t
+foo2 (uint8x16_t a, mve_pred16_t p)
+{
+  return vsubq_x (a, 1, p);
+}
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file

diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_x_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_x_s16.c
index 37936a6d6473e3c77cee039695c14cb96f83d59d..8dcc5477c6f99212ddaa745a389224d9a60cd716 100644 (file)
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_x_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_x_s16.c
@@ -1,15 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**     ...
+**     vmsr    p0, (?:ip|fp|r[0-9]+)(?:        @.*|)
+**     ...
+**     vpst(?: @.*|)
+**     ...
+**     vsubt.i16       q[0-9]+, q[0-9]+, q[0-9]+(?:    @.*|)
+**     ...
+*/
 int16x8_t
 foo (int16x8_t a, int16x8_t b, mve_pred16_t p)
 {
-    return vsubq_x_s16 (a, b, p);
+  return vsubq_x_s16 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vsubt.i16"  }  } */
 
+/*
+**foo1:
+**     ...
+**     vmsr    p0, (?:ip|fp|r[0-9]+)(?:        @.*|)
+**     ...
+**     vpst(?: @.*|)
+**     ...
+**     vsubt.i16       q[0-9]+, q[0-9]+, q[0-9]+(?:    @.*|)
+**     ...
+*/
+int16x8_t
+foo1 (int16x8_t a, int16x8_t b, mve_pred16_t p)
+{
+  return vsubq_x (a, b, p);
+}
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file

diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_x_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_x_s32.c
index c085f59c6a2ff7f76901905c2d288b7d9efe6de5..a2d4332322759657a2b33053f53390807a05e710 100644 (file)
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_x_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_x_s32.c
@@ -1,15 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**     ...
+**     vmsr    p0, (?:ip|fp|r[0-9]+)(?:        @.*|)
+**     ...
+**     vpst(?: @.*|)
+**     ...
+**     vsubt.i32       q[0-9]+, q[0-9]+, q[0-9]+(?:    @.*|)
+**     ...
+*/
 int32x4_t
 foo (int32x4_t a, int32x4_t b, mve_pred16_t p)
 {
-    return vsubq_x_s32 (a, b, p);
+  return vsubq_x_s32 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vsubt.i32"  }  } */
 
+/*
+**foo1:
+**     ...
+**     vmsr    p0, (?:ip|fp|r[0-9]+)(?:        @.*|)
+**     ...
+**     vpst(?: @.*|)
+**     ...
+**     vsubt.i32       q[0-9]+, q[0-9]+, q[0-9]+(?:    @.*|)
+**     ...
+*/
+int32x4_t
+foo1 (int32x4_t a, int32x4_t b, mve_pred16_t p)
+{
+  return vsubq_x (a, b, p);
+}
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file

diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_x_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_x_s8.c
index 361507821ea71eb324588f3d680cc324cdc958ce..8ead3d22439fcdbc6be2fcfbe9d884125f092fd6 100644 (file)
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_x_s8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_x_s8.c
@@ -1,15 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**     ...
+**     vmsr    p0, (?:ip|fp|r[0-9]+)(?:        @.*|)
+**     ...
+**     vpst(?: @.*|)
+**     ...
+**     vsubt.i8        q[0-9]+, q[0-9]+, q[0-9]+(?:    @.*|)
+**     ...
+*/
 int8x16_t
 foo (int8x16_t a, int8x16_t b, mve_pred16_t p)
 {
-    return vsubq_x_s8 (a, b, p);
+  return vsubq_x_s8 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vsubt.i8"  }  } */
 
+/*
+**foo1:
+**     ...
+**     vmsr    p0, (?:ip|fp|r[0-9]+)(?:        @.*|)
+**     ...
+**     vpst(?: @.*|)
+**     ...
+**     vsubt.i8        q[0-9]+, q[0-9]+, q[0-9]+(?:    @.*|)
+**     ...
+*/
+int8x16_t
+foo1 (int8x16_t a, int8x16_t b, mve_pred16_t p)
+{
+  return vsubq_x (a, b, p);
+}
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file

diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_x_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_x_u16.c
index 21423dc4f80f4ccb65d4e4031d8d3d826cf5e4a2..f0faf8165d2cc8b335965d9a6840b1b5c7210529 100644 (file)
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_x_u16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_x_u16.c
@@ -1,15 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**     ...
+**     vmsr    p0, (?:ip|fp|r[0-9]+)(?:        @.*|)
+**     ...
+**     vpst(?: @.*|)
+**     ...
+**     vsubt.i16       q[0-9]+, q[0-9]+, q[0-9]+(?:    @.*|)
+**     ...
+*/
 uint16x8_t
 foo (uint16x8_t a, uint16x8_t b, mve_pred16_t p)
 {
-    return vsubq_x_u16 (a, b, p);
+  return vsubq_x_u16 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vsubt.i16"  }  } */
 
+/*
+**foo1:
+**     ...
+**     vmsr    p0, (?:ip|fp|r[0-9]+)(?:        @.*|)
+**     ...
+**     vpst(?: @.*|)
+**     ...
+**     vsubt.i16       q[0-9]+, q[0-9]+, q[0-9]+(?:    @.*|)
+**     ...
+*/
+uint16x8_t
+foo1 (uint16x8_t a, uint16x8_t b, mve_pred16_t p)
+{
+  return vsubq_x (a, b, p);
+}
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file

diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_x_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_x_u32.c
index 38dd09ad8f79cef411e3db1d8d8373e2d8a5a5e3..67a709318597b3e4d440c6b50e4d87862699da2c 100644 (file)
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_x_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_x_u32.c
@@ -1,15 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**     ...
+**     vmsr    p0, (?:ip|fp|r[0-9]+)(?:        @.*|)
+**     ...
+**     vpst(?: @.*|)
+**     ...
+**     vsubt.i32       q[0-9]+, q[0-9]+, q[0-9]+(?:    @.*|)
+**     ...
+*/
 uint32x4_t
 foo (uint32x4_t a, uint32x4_t b, mve_pred16_t p)
 {
-    return vsubq_x_u32 (a, b, p);
+  return vsubq_x_u32 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vsubt.i32"  }  } */
 
+/*
+**foo1:
+**     ...
+**     vmsr    p0, (?:ip|fp|r[0-9]+)(?:        @.*|)
+**     ...
+**     vpst(?: @.*|)
+**     ...
+**     vsubt.i32       q[0-9]+, q[0-9]+, q[0-9]+(?:    @.*|)
+**     ...
+*/
+uint32x4_t
+foo1 (uint32x4_t a, uint32x4_t b, mve_pred16_t p)
+{
+  return vsubq_x (a, b, p);
+}
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file

diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_x_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_x_u8.c
index 406cbf760fda3038ac58c1acde4eeb23223e4837..19002336cbdf655c73ce11d4dd63542c7c11a046 100644 (file)
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_x_u8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_x_u8.c
@@ -1,15 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**     ...
+**     vmsr    p0, (?:ip|fp|r[0-9]+)(?:        @.*|)
+**     ...
+**     vpst(?: @.*|)
+**     ...
+**     vsubt.i8        q[0-9]+, q[0-9]+, q[0-9]+(?:    @.*|)
+**     ...
+*/
 uint8x16_t
 foo (uint8x16_t a, uint8x16_t b, mve_pred16_t p)
 {
-    return vsubq_x_u8 (a, b, p);
+  return vsubq_x_u8 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vsubt.i8"  }  } */
 
+/*
+**foo1:
+**     ...
+**     vmsr    p0, (?:ip|fp|r[0-9]+)(?:        @.*|)
+**     ...
+**     vpst(?: @.*|)
+**     ...
+**     vsubt.i8        q[0-9]+, q[0-9]+, q[0-9]+(?:    @.*|)
+**     ...
+*/
+uint8x16_t
+foo1 (uint8x16_t a, uint8x16_t b, mve_pred16_t p)
+{
+  return vsubq_x (a, b, p);
+}
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file