vfmadd213<ssemodesuffix>\t{<round_sd_mask_op4>%3, %2, %0<sd_mask_op4>|%0<sd_mask_op4>, %2, %3<round_sd_mask_op4>}
vfmadd231<ssemodesuffix>\t{<round_sd_mask_op4>%2, %1, %0<sd_mask_op4>|%0<sd_mask_op4>, %1, %2<round_sd_mask_op4>}"
[(set_attr "type" "ssemuladd")
+ (set_attr "prefix" "evex")
(set_attr "mode" "<MODE>")])
(define_expand "cond_fma<mode>"
vfmadd132<ssemodesuffix>\t{<round_op5>%2, %3, %0%{%4%}|%0%{%4%}, %3, %2<round_op5>}
vfmadd213<ssemodesuffix>\t{<round_op5>%3, %2, %0%{%4%}|%0%{%4%}, %2, %3<round_op5>}"
[(set_attr "type" "ssemuladd")
+ (set_attr "prefix" "evex")
(set_attr "mode" "<MODE>")])
(define_insn "<avx512>_fmadd_<mode>_mask3<round_name>"
"TARGET_AVX512F"
"vfmadd231<ssemodesuffix>\t{<round_op5>%2, %1, %0%{%4%}|%0%{%4%}, %1, %2<round_op5>}"
[(set_attr "type" "ssemuladd")
+ (set_attr "prefix" "evex")
(set_attr "mode" "<MODE>")])
(define_insn "*fma_fmsub_<mode>"
vfmsub213<ssemodesuffix>\t{<round_sd_mask_op4>%3, %2, %0<sd_mask_op4>|%0<sd_mask_op4>, %2, %3<round_sd_mask_op4>}
vfmsub231<ssemodesuffix>\t{<round_sd_mask_op4>%2, %1, %0<sd_mask_op4>|%0<sd_mask_op4>, %1, %2<round_sd_mask_op4>}"
[(set_attr "type" "ssemuladd")
+ (set_attr "prefix" "evex")
(set_attr "mode" "<MODE>")])
(define_expand "cond_fms<mode>"
vfmsub132<ssemodesuffix>\t{<round_op5>%2, %3, %0%{%4%}|%0%{%4%}, %3, %2<round_op5>}
vfmsub213<ssemodesuffix>\t{<round_op5>%3, %2, %0%{%4%}|%0%{%4%}, %2, %3<round_op5>}"
[(set_attr "type" "ssemuladd")
+ (set_attr "prefix" "evex")
(set_attr "mode" "<MODE>")])
(define_insn "<avx512>_fmsub_<mode>_mask3<round_name>"
"TARGET_AVX512F && <round_mode512bit_condition>"
"vfmsub231<ssemodesuffix>\t{<round_op5>%2, %1, %0%{%4%}|%0%{%4%}, %1, %2<round_op5>}"
[(set_attr "type" "ssemuladd")
+ (set_attr "prefix" "evex")
(set_attr "mode" "<MODE>")])
(define_insn "*fma_fnmadd_<mode>"
vfnmadd213<ssemodesuffix>\t{<round_sd_mask_op4>%3, %2, %0<sd_mask_op4>|%0<sd_mask_op4>, %2, %3<round_sd_mask_op4>}
vfnmadd231<ssemodesuffix>\t{<round_sd_mask_op4>%2, %1, %0<sd_mask_op4>|%0<sd_mask_op4>, %1, %2<round_sd_mask_op4>}"
[(set_attr "type" "ssemuladd")
+ (set_attr "prefix" "evex")
(set_attr "mode" "<MODE>")])
(define_expand "cond_fnma<mode>"
vfnmadd132<ssemodesuffix>\t{<round_op5>%2, %3, %0%{%4%}|%0%{%4%}, %3, %2<round_op5>}
vfnmadd213<ssemodesuffix>\t{<round_op5>%3, %2, %0%{%4%}|%0%{%4%}, %2, %3<round_op5>}"
[(set_attr "type" "ssemuladd")
+ (set_attr "prefix" "evex")
(set_attr "mode" "<MODE>")])
(define_insn "<avx512>_fnmadd_<mode>_mask3<round_name>"
"TARGET_AVX512F && <round_mode512bit_condition>"
"vfnmadd231<ssemodesuffix>\t{<round_op5>%2, %1, %0%{%4%}|%0%{%4%}, %1, %2<round_op5>}"
[(set_attr "type" "ssemuladd")
+ (set_attr "prefix" "evex")
(set_attr "mode" "<MODE>")])
(define_insn "*fma_fnmsub_<mode>"
vfnmsub213<ssemodesuffix>\t{<round_sd_mask_op4>%3, %2, %0<sd_mask_op4>|%0<sd_mask_op4>, %2, %3<round_sd_mask_op4>}
vfnmsub231<ssemodesuffix>\t{<round_sd_mask_op4>%2, %1, %0<sd_mask_op4>|%0<sd_mask_op4>, %1, %2<round_sd_mask_op4>}"
[(set_attr "type" "ssemuladd")
+ (set_attr "prefix" "evex")
(set_attr "mode" "<MODE>")])
(define_expand "cond_fnms<mode>"
vfnmsub132<ssemodesuffix>\t{<round_op5>%2, %3, %0%{%4%}|%0%{%4%}, %3, %2<round_op5>}
vfnmsub213<ssemodesuffix>\t{<round_op5>%3, %2, %0%{%4%}|%0%{%4%}, %2, %3<round_op5>}"
[(set_attr "type" "ssemuladd")
+ (set_attr "prefix" "evex")
(set_attr "mode" "<MODE>")])
(define_insn "<avx512>_fnmsub_<mode>_mask3<round_name>"
"TARGET_AVX512F"
"vfnmsub231<ssemodesuffix>\t{<round_op5>%2, %1, %0%{%4%}|%0%{%4%}, %1, %2<round_op5>}"
[(set_attr "type" "ssemuladd")
+ (set_attr "prefix" "evex")
(set_attr "mode" "<MODE>")])
;; FMA parallel floating point multiply addsub and subadd operations.
vfmaddsub213<ssemodesuffix>\t{<round_sd_mask_op4>%3, %2, %0<sd_mask_op4>|%0<sd_mask_op4>, %2, %3<round_sd_mask_op4>}
vfmaddsub231<ssemodesuffix>\t{<round_sd_mask_op4>%2, %1, %0<sd_mask_op4>|%0<sd_mask_op4>, %1, %2<round_sd_mask_op4>}"
[(set_attr "type" "ssemuladd")
+ (set_attr "prefix" "evex")
(set_attr "mode" "<MODE>")])
(define_insn "<avx512>_fmaddsub_<mode>_mask<round_name>"
vfmaddsub132<ssemodesuffix>\t{<round_op5>%2, %3, %0%{%4%}|%0%{%4%}, %3, %2<round_op5>}
vfmaddsub213<ssemodesuffix>\t{<round_op5>%3, %2, %0%{%4%}|%0%{%4%}, %2, %3<round_op5>}"
[(set_attr "type" "ssemuladd")
+ (set_attr "prefix" "evex")
(set_attr "mode" "<MODE>")])
(define_insn "<avx512>_fmaddsub_<mode>_mask3<round_name>"
"TARGET_AVX512F"
"vfmaddsub231<ssemodesuffix>\t{<round_op5>%2, %1, %0%{%4%}|%0%{%4%}, %1, %2<round_op5>}"
[(set_attr "type" "ssemuladd")
+ (set_attr "prefix" "evex")
(set_attr "mode" "<MODE>")])
(define_insn "*fma_fmsubadd_<mode>"
vfmsubadd213<ssemodesuffix>\t{<round_sd_mask_op4>%3, %2, %0<sd_mask_op4>|%0<sd_mask_op4>, %2, %3<round_sd_mask_op4>}
vfmsubadd231<ssemodesuffix>\t{<round_sd_mask_op4>%2, %1, %0<sd_mask_op4>|%0<sd_mask_op4>, %1, %2<round_sd_mask_op4>}"
[(set_attr "type" "ssemuladd")
+ (set_attr "prefix" "evex")
(set_attr "mode" "<MODE>")])
(define_insn "<avx512>_fmsubadd_<mode>_mask<round_name>"
vfmsubadd132<ssemodesuffix>\t{<round_op5>%2, %3, %0%{%4%}|%0%{%4%}, %3, %2<round_op5>}
vfmsubadd213<ssemodesuffix>\t{<round_op5>%3, %2, %0%{%4%}|%0%{%4%}, %2, %3<round_op5>}"
[(set_attr "type" "ssemuladd")
+ (set_attr "prefix" "evex")
(set_attr "mode" "<MODE>")])
(define_insn "<avx512>_fmsubadd_<mode>_mask3<round_name>"
"TARGET_AVX512F"
"vfmsubadd231<ssemodesuffix>\t{<round_op5>%2, %1, %0%{%4%}|%0%{%4%}, %1, %2<round_op5>}"
[(set_attr "type" "ssemuladd")
+ (set_attr "prefix" "evex")
(set_attr "mode" "<MODE>")])
;; FMA3 floating point scalar intrinsics. These merge result with
vfmadd132<ssescalarmodesuffix>\t{<round_op4>%2, %3, %0|%0, %<iptr>3, %<iptr>2<round_op4>}
vfmadd213<ssescalarmodesuffix>\t{<round_op4>%3, %2, %0|%0, %<iptr>2, %<iptr>3<round_op4>}"
[(set_attr "type" "ssemuladd")
+ (set_attr "prefix" "maybe_evex")
(set_attr "mode" "<MODE>")])
(define_insn "*fmai_fmsub_<mode>"
vfmsub132<ssescalarmodesuffix>\t{<round_op4>%2, %3, %0|%0, %<iptr>3, %<iptr>2<round_op4>}
vfmsub213<ssescalarmodesuffix>\t{<round_op4>%3, %2, %0|%0, %<iptr>2, %<iptr>3<round_op4>}"
[(set_attr "type" "ssemuladd")
+ (set_attr "prefix" "maybe_evex")
(set_attr "mode" "<MODE>")])
(define_insn "*fmai_fnmadd_<mode><round_name>"
vfnmadd132<ssescalarmodesuffix>\t{<round_op4>%2, %3, %0|%0, %<iptr>3, %<iptr>2<round_op4>}
vfnmadd213<ssescalarmodesuffix>\t{<round_op4>%3, %2, %0|%0, %<iptr>2, %<iptr>3<round_op4>}"
[(set_attr "type" "ssemuladd")
+ (set_attr "prefix" "maybe_evex")
(set_attr "mode" "<MODE>")])
(define_insn "*fmai_fnmsub_<mode><round_name>"
vfnmsub132<ssescalarmodesuffix>\t{<round_op4>%2, %3, %0|%0, %<iptr>3, %<iptr>2<round_op4>}
vfnmsub213<ssescalarmodesuffix>\t{<round_op4>%3, %2, %0|%0, %<iptr>2, %<iptr>3<round_op4>}"
[(set_attr "type" "ssemuladd")
+ (set_attr "prefix" "maybe_evex")
(set_attr "mode" "<MODE>")])
(define_insn "avx512f_vmfmadd_<mode>_mask<round_name>"
vfmadd132<ssescalarmodesuffix>\t{<round_op5>%2, %3, %0%{%4%}|%0%{%4%}, %<iptr>3, %<iptr>2<round_op5>}
vfmadd213<ssescalarmodesuffix>\t{<round_op5>%3, %2, %0%{%4%}|%0%{%4%}, %<iptr>2, %<iptr>3<round_op5>}"
[(set_attr "type" "ssemuladd")
+ (set_attr "prefix" "evex")
(set_attr "mode" "<MODE>")])
(define_insn "avx512f_vmfmadd_<mode>_mask3<round_name>"
"TARGET_AVX512F"
"vfmadd231<ssescalarmodesuffix>\t{<round_op5>%2, %1, %0%{%4%}|%0%{%4%}, %<iptr>3, %<iptr>2<round_op5>}"
[(set_attr "type" "ssemuladd")
+ (set_attr "prefix" "evex")
(set_attr "mode" "<MODE>")])
(define_expand "avx512f_vmfmadd_<mode>_maskz<round_expand_name>"
vfmadd132<ssescalarmodesuffix>\t{<round_op6>%2, %3, %0%{%5%}%{z%}|%0%{%5%}%{z%}, %<iptr>3, %<iptr>2<round_op6>}
vfmadd213<ssescalarmodesuffix>\t{<round_op6>%3, %2, %0%{%5%}%{z%}|%0%{%5%}%{z%}, %<iptr>2, %<iptr>3<round_op6>}"
[(set_attr "type" "ssemuladd")
+ (set_attr "prefix" "evex")
(set_attr "mode" "<MODE>")])
(define_insn "*avx512f_vmfmsub_<mode>_mask<round_name>"
vfmsub132<ssescalarmodesuffix>\t{<round_op5>%2, %3, %0%{%4%}|%0%{%4%}, %<iptr>3, %<iptr>2<round_op5>}
vfmsub213<ssescalarmodesuffix>\t{<round_op5>%3, %2, %0%{%4%}|%0%{%4%}, %<iptr>2, %<iptr>3<round_op5>}"
[(set_attr "type" "ssemuladd")
+ (set_attr "prefix" "evex")
(set_attr "mode" "<MODE>")])
(define_insn "avx512f_vmfmsub_<mode>_mask3<round_name>"
"TARGET_AVX512F"
"vfmsub231<ssescalarmodesuffix>\t{<round_op5>%2, %1, %0%{%4%}|%0%{%4%}, %<iptr>3, %<iptr>2<round_op5>}"
[(set_attr "type" "ssemuladd")
+ (set_attr "prefix" "evex")
(set_attr "mode" "<MODE>")])
(define_insn "*avx512f_vmfmsub_<mode>_maskz_1<round_name>"
vfmsub132<ssescalarmodesuffix>\t{<round_op6>%2, %3, %0%{%5%}%{z%}|%0%{%5%}%{z%}, %<iptr>3, %<iptr>2<round_op6>}
vfmsub213<ssescalarmodesuffix>\t{<round_op6>%3, %2, %0%{%5%}%{z%}|%0%{%5%}%{z%}, %<iptr>2, %<iptr>3<round_op6>}"
[(set_attr "type" "ssemuladd")
+ (set_attr "prefix" "evex")
(set_attr "mode" "<MODE>")])
(define_insn "avx512f_vmfnmadd_<mode>_mask<round_name>"
vfnmadd132<ssescalarmodesuffix>\t{<round_op5>%2, %3, %0%{%4%}|%0%{%4%}, %<iptr>3, %<iptr>2<round_op5>}
vfnmadd213<ssescalarmodesuffix>\t{<round_op5>%3, %2, %0%{%4%}|%0%{%4%}, %<iptr>2, %<iptr>3<round_op5>}"
[(set_attr "type" "ssemuladd")
+ (set_attr "prefix" "evex")
(set_attr "mode" "<MODE>")])
(define_insn "avx512f_vmfnmadd_<mode>_mask3<round_name>"
"TARGET_AVX512F"
"vfnmadd231<ssescalarmodesuffix>\t{<round_op5>%2, %1, %0%{%4%}|%0%{%4%}, %<iptr>3, %<iptr>2<round_op5>}"
[(set_attr "type" "ssemuladd")
+ (set_attr "prefix" "evex")
(set_attr "mode" "<MODE>")])
(define_expand "avx512f_vmfnmadd_<mode>_maskz<round_expand_name>"
vfnmadd132<ssescalarmodesuffix>\t{<round_op6>%2, %3, %0%{%5%}%{z%}|%0%{%5%}%{z%}, %<iptr>3, %<iptr>2<round_op6>}
vfnmadd213<ssescalarmodesuffix>\t{<round_op6>%3, %2, %0%{%5%}%{z%}|%0%{%5%}%{z%}, %<iptr>2, %<iptr>3<round_op6>}"
[(set_attr "type" "ssemuladd")
+ (set_attr "prefix" "evex")
(set_attr "mode" "<MODE>")])
(define_insn "*avx512f_vmfnmsub_<mode>_mask<round_name>"
vfnmsub132<ssescalarmodesuffix>\t{<round_op5>%2, %3, %0%{%4%}|%0%{%4%}, %<iptr>3, %<iptr>2<round_op5>}
vfnmsub213<ssescalarmodesuffix>\t{<round_op5>%3, %2, %0%{%4%}|%0%{%4%}, %<iptr>2, %<iptr>3<round_op5>}"
[(set_attr "type" "ssemuladd")
+ (set_attr "prefix" "evex")
(set_attr "mode" "<MODE>")])
(define_insn "*avx512f_vmfnmsub_<mode>_mask3<round_name>"
"TARGET_AVX512F"
"vfnmsub231<ssescalarmodesuffix>\t{<round_op5>%2, %1, %0%{%4%}|%0%{%4%}, %<iptr>3, %<iptr>2<round_op5>}"
[(set_attr "type" "ssemuladd")
+ (set_attr "prefix" "evex")
(set_attr "mode" "<MODE>")])
(define_insn "*avx512f_vmfnmsub_<mode>_maskz_1<round_name>"
vfnmsub132<ssescalarmodesuffix>\t{<round_op6>%2, %3, %0%{%5%}%{z%}|%0%{%5%}%{z%}, %<iptr>3, %<iptr>2<round_op6>}
vfnmsub213<ssescalarmodesuffix>\t{<round_op6>%3, %2, %0%{%5%}%{z%}|%0%{%5%}%{z%}, %<iptr>2, %<iptr>3<round_op6>}"
[(set_attr "type" "ssemuladd")
+ (set_attr "prefix" "evex")
(set_attr "mode" "<MODE>")])
;; FMA4 floating point scalar intrinsics. These write the
"TARGET_FMA4"
"vfmadd<ssescalarmodesuffix>\t{%3, %2, %1, %0|%0, %1, %<iptr>2, %<iptr>3}"
[(set_attr "type" "ssemuladd")
+ (set_attr "prefix" "vex")
(set_attr "mode" "<MODE>")])
(define_insn "*fma4i_vmfmsub_<mode>"
"TARGET_FMA4"
"vfmsub<ssescalarmodesuffix>\t{%3, %2, %1, %0|%0, %1, %<iptr>2, %<iptr>3}"
[(set_attr "type" "ssemuladd")
+ (set_attr "prefix" "vex")
(set_attr "mode" "<MODE>")])
(define_insn "*fma4i_vmfnmadd_<mode>"
"TARGET_FMA4"
"vfnmadd<ssescalarmodesuffix>\t{%3, %2, %1, %0|%0, %1, %<iptr>2, %<iptr>3}"
[(set_attr "type" "ssemuladd")
+ (set_attr "prefix" "vex")
(set_attr "mode" "<MODE>")])
(define_insn "*fma4i_vmfnmsub_<mode>"
"TARGET_FMA4"
"vfnmsub<ssescalarmodesuffix>\t{%3, %2, %1, %0|%0, %1, %<iptr>2, %<iptr>3}"
[(set_attr "type" "ssemuladd")
+ (set_attr "prefix" "vex")
(set_attr "mode" "<MODE>")])
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
"TARGET_AVX512FP16 && <sdc_mask_mode512bit_condition> && <round_mode512bit_condition>"
"v<complexopname><ssemodesuffix>\t{<round_sdc_mask_op4>%2, %1, %0<sdc_mask_op4>|%0<sdc_mask_op4>, %1, %2<round_sdc_mask_op4>}"
[(set_attr "type" "ssemuladd")
+ (set_attr "prefix" "evex")
(set_attr "mode" "<MODE>")])
(define_insn_and_split "fma_<mode>_fadd_fmul"
UNSPEC_COMPLEX_F_C_MA_PAIR))]
"TARGET_AVX512FP16"
"v<complexpairopname>ph\t{%2, %1, %0|%0, %1, %2}"
- [(set_attr "type" "ssemuladd")])
+ [(set_attr "type" "ssemuladd")
+ (set_attr "prefix" "evex")
+ (set_attr "mode" "<MODE>")])
(define_insn_and_split "fma_<mode>_fmaddc_bcst"
[(set (match_operand:VF_AVX512FP16VL 0 "register_operand")
"TARGET_AVX512FP16 && <round_mode512bit_condition>"
"v<complexopname><ssemodesuffix>\t{<round_op5>%2, %1, %0%{%4%}|%0%{%4%}, %1, %2<round_op5>}"
[(set_attr "type" "ssemuladd")
+ (set_attr "prefix" "evex")
(set_attr "mode" "<MODE>")])
(define_expand "cmul<conj_op><mode>3"
"TARGET_AVX512FP16"
"v<complexopname>sh\t{<round_scalarcz_mask_op4>%2, %1, %0<mask_scalarcz_operand4>|%0<mask_scalarcz_operand4>, %1, %2<round_scalarcz_mask_op4>}"
[(set_attr "type" "ssemuladd")
+ (set_attr "prefix" "evex")
(set_attr "mode" "V8HF")])
(define_insn "avx512fp16_<complexopname>sh_v8hf_mask<round_name>"
"TARGET_AVX512FP16"
"v<complexopname>sh\t{<round_op5>%2, %1, %0%{%4%}|%0%{%4%}, %1, %2<round_op5>}"
[(set_attr "type" "ssemuladd")
+ (set_attr "prefix" "evex")
(set_attr "mode" "V8HF")])
(define_insn "avx512fp16_<complexopname>sh_v8hf<mask_scalarc_name><round_scalarcz_name>"
"TARGET_XOP"
"vp<macs><ssemodesuffix><ssemodesuffix>\t{%3, %2, %1, %0|%0, %1, %2, %3}"
[(set_attr "type" "ssemuladd")
+ (set_attr "prefix" "vex")
(set_attr "mode" "TI")])
(define_insn "xop_p<macs>dql"
"TARGET_XOP"
"vp<macs>dql\t{%3, %2, %1, %0|%0, %1, %2, %3}"
[(set_attr "type" "ssemuladd")
+ (set_attr "prefix" "vex")
(set_attr "mode" "TI")])
(define_insn "xop_p<macs>dqh"
"TARGET_XOP"
"vp<macs>dqh\t{%3, %2, %1, %0|%0, %1, %2, %3}"
[(set_attr "type" "ssemuladd")
+ (set_attr "prefix" "vex")
(set_attr "mode" "TI")])
;; XOP parallel integer multiply/add instructions for the intrinisics
"TARGET_XOP"
"vp<macs>wd\t{%3, %2, %1, %0|%0, %1, %2, %3}"
[(set_attr "type" "ssemuladd")
+ (set_attr "prefix" "vex")
(set_attr "mode" "TI")])
(define_insn "xop_p<madcs>wd"
"TARGET_XOP"
"vp<madcs>wd\t{%3, %2, %1, %0|%0, %1, %2, %3}"
[(set_attr "type" "ssemuladd")
+ (set_attr "prefix" "vex")
(set_attr "mode" "TI")])
;; XOP parallel XMM conditional moves