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arm: [MVE intrinsics] factorize vqrshrunb vqrshrunt vqshrunb vqshrunt
authorChristophe Lyon <christophe.lyon@arm.com>
Thu, 9 Feb 2023 14:58:24 +0000 (14:58 +0000)
committerChristophe Lyon <christophe.lyon@arm.com>
Fri, 5 May 2023 14:12:01 +0000 (16:12 +0200)
Factorize vqrshrunb, vqrshrunt, vqshrunb, vqshrunt so that they use
existing patterns.

2022-09-08  Christophe Lyon  <christophe.lyon@arm.com>

gcc/
* config/arm/iterators.md (MVE_SHRN_N): Add VQRSHRUNBQ,
VQRSHRUNTQ, VQSHRUNBQ, VQSHRUNTQ.
(MVE_SHRN_M_N): Likewise.
(mve_insn): Add vqrshrunb, vqrshrunt, vqshrunb, vqshrunt.
(isu): Add VQRSHRUNBQ, VQRSHRUNTQ, VQSHRUNBQ, VQSHRUNTQ.
(supf): Likewise.
* config/arm/mve.md (mve_vqrshrunbq_n_s<mode>): Remove.
(mve_vqrshruntq_n_s<mode>): Remove.
(mve_vqshrunbq_n_s<mode>): Remove.
(mve_vqshruntq_n_s<mode>): Remove.
(mve_vqrshrunbq_m_n_s<mode>): Remove.
(mve_vqrshruntq_m_n_s<mode>): Remove.
(mve_vqshrunbq_m_n_s<mode>): Remove.
(mve_vqshruntq_m_n_s<mode>): Remove.

gcc/config/arm/iterators.md patch | blob | blame | history
gcc/config/arm/mve.md patch | blob | blame | history

diff --git a/gcc/config/arm/iterators.md b/gcc/config/arm/iterators.md
index d64c924a51308b4e32816f26cffc26deeda3eaf1..583206dac9e0d2d434cd5b856d10f37f20f38f52 100644 (file)
--- a/gcc/config/arm/iterators.md
+++ b/gcc/config/arm/iterators.md
@@ -471,8 +471,12 @@
 (define_int_iterator MVE_SHRN_N [
                     VQRSHRNBQ_N_S VQRSHRNBQ_N_U
                     VQRSHRNTQ_N_S VQRSHRNTQ_N_U
+                    VQRSHRUNBQ_N_S
+                    VQRSHRUNTQ_N_S
                     VQSHRNBQ_N_S VQSHRNBQ_N_U
                     VQSHRNTQ_N_S VQSHRNTQ_N_U
+                    VQSHRUNBQ_N_S
+                    VQSHRUNTQ_N_S
                     VRSHRNBQ_N_S VRSHRNBQ_N_U
                     VRSHRNTQ_N_S VRSHRNTQ_N_U
                     VSHRNBQ_N_S VSHRNBQ_N_U
@@ -482,8 +486,12 @@
 (define_int_iterator MVE_SHRN_M_N [
                     VQRSHRNBQ_M_N_S VQRSHRNBQ_M_N_U
                     VQRSHRNTQ_M_N_S VQRSHRNTQ_M_N_U
+                    VQRSHRUNBQ_M_N_S
+                    VQRSHRUNTQ_M_N_S
                     VQSHRNBQ_M_N_S VQSHRNBQ_M_N_U
                     VQSHRNTQ_M_N_S VQSHRNTQ_M_N_U
+                    VQSHRUNBQ_M_N_S
+                    VQSHRUNTQ_M_N_S
                     VRSHRNBQ_M_N_S VRSHRNBQ_M_N_U
                     VRSHRNTQ_M_N_S VRSHRNTQ_M_N_U
                     VSHRNBQ_M_N_S VSHRNBQ_M_N_U
@@ -594,6 +602,10 @@
                 (VQRSHRNBQ_N_S "vqrshrnb") (VQRSHRNBQ_N_U "vqrshrnb")
                 (VQRSHRNTQ_M_N_S "vqrshrnt") (VQRSHRNTQ_M_N_U "vqrshrnt")
                 (VQRSHRNTQ_N_S "vqrshrnt") (VQRSHRNTQ_N_U "vqrshrnt")
+                (VQRSHRUNBQ_M_N_S "vqrshrunb")
+                (VQRSHRUNBQ_N_S "vqrshrunb")
+                (VQRSHRUNTQ_M_N_S "vqrshrunt")
+                (VQRSHRUNTQ_N_S "vqrshrunt")
                 (VQSHLQ_M_N_S "vqshl") (VQSHLQ_M_N_U "vqshl")
                 (VQSHLQ_M_R_S "vqshl") (VQSHLQ_M_R_U "vqshl")
                 (VQSHLQ_M_S "vqshl") (VQSHLQ_M_U "vqshl")
@@ -604,6 +616,10 @@
                 (VQSHRNBQ_N_S "vqshrnb") (VQSHRNBQ_N_U "vqshrnb")
                 (VQSHRNTQ_M_N_S "vqshrnt") (VQSHRNTQ_M_N_U "vqshrnt")
                 (VQSHRNTQ_N_S "vqshrnt") (VQSHRNTQ_N_U "vqshrnt")
+                (VQSHRUNBQ_M_N_S "vqshrunb")
+                (VQSHRUNBQ_N_S "vqshrunb")
+                (VQSHRUNTQ_M_N_S "vqshrunt")
+                (VQSHRUNTQ_N_S "vqshrunt")
                 (VQSUBQ_M_N_S "vqsub") (VQSUBQ_M_N_U "vqsub")
                 (VQSUBQ_M_S "vqsub") (VQSUBQ_M_U "vqsub")
                 (VQSUBQ_N_S "vqsub") (VQSUBQ_N_U "vqsub")
@@ -640,10 +656,18 @@
                 (VQRSHRNBQ_N_S "s") (VQRSHRNBQ_N_U "u")
                 (VQRSHRNTQ_M_N_S "s") (VQRSHRNTQ_M_N_U "u")
                 (VQRSHRNTQ_N_S "s") (VQRSHRNTQ_N_U "u")
+                (VQRSHRUNBQ_M_N_S "s")
+                (VQRSHRUNBQ_N_S "s")
+                (VQRSHRUNTQ_M_N_S "s")
+                (VQRSHRUNTQ_N_S "s")
                 (VQSHRNBQ_M_N_S "s") (VQSHRNBQ_M_N_U "u")
                 (VQSHRNBQ_N_S "s") (VQSHRNBQ_N_U "u")
                 (VQSHRNTQ_M_N_S "s") (VQSHRNTQ_M_N_U "u")
                 (VQSHRNTQ_N_S "s") (VQSHRNTQ_N_U "u")
+                (VQSHRUNBQ_M_N_S "s")
+                (VQSHRUNBQ_N_S "s")
+                (VQSHRUNTQ_M_N_S "s")
+                (VQSHRUNTQ_N_S "s")
                 (VRSHRNBQ_M_N_S "i") (VRSHRNBQ_M_N_U "i")
                 (VRSHRNBQ_N_S "i") (VRSHRNBQ_N_U "i")
                 (VRSHRNTQ_M_N_S "i") (VRSHRNTQ_M_N_U "i")
@@ -1816,6 +1840,14 @@
                       (VQRDMULHQ_M_N_S "s")
                       (VQDMULHQ_S "s")
                       (VQRDMULHQ_S "s")
+                      (VQRSHRUNBQ_M_N_S "s")
+                      (VQRSHRUNBQ_N_S "s")
+                      (VQRSHRUNTQ_M_N_S "s")
+                      (VQRSHRUNTQ_N_S "s")
+                      (VQSHRUNBQ_M_N_S "s")
+                      (VQSHRUNBQ_N_S "s")
+                      (VQSHRUNTQ_M_N_S "s")
+                      (VQSHRUNTQ_N_S "s")
                       ])
 
 ;; Both kinds of return insn.
diff --git a/gcc/config/arm/mve.md b/gcc/config/arm/mve.md
index d64a075c7bbf7fed5b16b8d4f107e047d30a9242..20ce7ecb3d6b23af10d45eaa5dd5d47a78a68e35 100644 (file)
--- a/gcc/config/arm/mve.md
+++ b/gcc/config/arm/mve.md
@@ -2166,8 +2166,12 @@
 ;;
 ;; [vqrshrnbq_n_u, vqrshrnbq_n_s]
 ;; [vqrshrntq_n_u, vqrshrntq_n_s]
+;; [vqrshrunbq_n_s]
+;; [vqrshruntq_n_s]
 ;; [vqshrnbq_n_u, vqshrnbq_n_s]
 ;; [vqshrntq_n_u, vqshrntq_n_s]
+;; [vqshrunbq_n_s]
+;; [vqshruntq_n_s]
 ;; [vrshrnbq_n_s, vrshrnbq_n_u]
 ;; [vrshrntq_n_u, vrshrntq_n_s]
 ;; [vshrnbq_n_u, vshrnbq_n_s]
@@ -2186,22 +2190,6 @@
   [(set_attr "type" "mve_move")
 ])
 
-;;
-;; [vqrshrunbq_n_s])
-;;
-(define_insn "mve_vqrshrunbq_n_s<mode>"
-  [
-   (set (match_operand:<V_narrow_pack> 0 "s_register_operand" "=w")
-       (unspec:<V_narrow_pack> [(match_operand:<V_narrow_pack> 1 "s_register_operand" "0")
-                                (match_operand:MVE_5 2 "s_register_operand" "w")
-                                (match_operand:SI 3 "<MVE_pred3>" "<MVE_constraint3>")]
-        VQRSHRUNBQ_N_S))
-  ]
-  "TARGET_HAVE_MVE"
-  "vqrshrunb.s%#<V_sz_elem>\t%q0, %q2, %3"
-  [(set_attr "type" "mve_move")
-])
-
 ;;
 ;; [vrmlaldavhaq_s vrmlaldavhaq_u])
 ;;
@@ -4002,54 +3990,6 @@
   [(set_attr "type" "mve_move")
    (set_attr "length""8")])
 
-;;
-;; [vqrshruntq_n_s])
-;;
-(define_insn "mve_vqrshruntq_n_s<mode>"
-  [
-   (set (match_operand:<V_narrow_pack> 0 "s_register_operand" "=w")
-       (unspec:<V_narrow_pack> [(match_operand:<V_narrow_pack> 1 "s_register_operand" "0")
-                      (match_operand:MVE_5 2 "s_register_operand" "w")
-                      (match_operand:SI 3 "<MVE_pred3>" "<MVE_constraint3>")]
-        VQRSHRUNTQ_N_S))
-  ]
-  "TARGET_HAVE_MVE"
-  "vqrshrunt.s%#<V_sz_elem>    %q0, %q2, %3"
-  [(set_attr "type" "mve_move")
-])
-
-;;
-;; [vqshrunbq_n_s])
-;;
-(define_insn "mve_vqshrunbq_n_s<mode>"
-  [
-   (set (match_operand:<V_narrow_pack> 0 "s_register_operand" "=w")
-       (unspec:<V_narrow_pack> [(match_operand:<V_narrow_pack> 1 "s_register_operand" "0")
-                      (match_operand:MVE_5 2 "s_register_operand" "w")
-                      (match_operand:SI 3 "<MVE_pred3>" "<MVE_constraint3>")]
-        VQSHRUNBQ_N_S))
-  ]
-  "TARGET_HAVE_MVE"
-  "vqshrunb.s%#<V_sz_elem>     %q0, %q2, %3"
-  [(set_attr "type" "mve_move")
-])
-
-;;
-;; [vqshruntq_n_s])
-;;
-(define_insn "mve_vqshruntq_n_s<mode>"
-  [
-   (set (match_operand:<V_narrow_pack> 0 "s_register_operand" "=w")
-       (unspec:<V_narrow_pack> [(match_operand:<V_narrow_pack> 1 "s_register_operand" "0")
-                      (match_operand:MVE_5 2 "s_register_operand" "w")
-                      (match_operand:SI 3 "<MVE_pred3>" "<MVE_constraint3>")]
-        VQSHRUNTQ_N_S))
-  ]
-  "TARGET_HAVE_MVE"
-  "vqshrunt.s%#<V_sz_elem>     %q0, %q2, %3"
-  [(set_attr "type" "mve_move")
-])
-
 ;;
 ;; [vrev32q_m_f])
 ;;
@@ -4892,8 +4832,12 @@
 ;;
 ;; [vqrshrnbq_m_n_u, vqrshrnbq_m_n_s]
 ;; [vqrshrntq_m_n_s, vqrshrntq_m_n_u]
+;; [vqrshrunbq_m_n_s]
+;; [vqrshruntq_m_n_s]
 ;; [vqshrnbq_m_n_u, vqshrnbq_m_n_s]
 ;; [vqshrntq_m_n_s, vqshrntq_m_n_u]
+;; [vqshrunbq_m_n_s]
+;; [vqshruntq_m_n_s]
 ;; [vrshrnbq_m_n_u, vrshrnbq_m_n_s]
 ;; [vrshrntq_m_n_u, vrshrntq_m_n_s]
 ;; [vshrnbq_m_n_s, vshrnbq_m_n_u]
@@ -5100,74 +5044,6 @@
   [(set_attr "type" "mve_move")
    (set_attr "length""8")])
 
-;;
-;; [vqrshrunbq_m_n_s])
-;;
-(define_insn "mve_vqrshrunbq_m_n_s<mode>"
-  [
-   (set (match_operand:<V_narrow_pack> 0 "s_register_operand" "=w")
-       (unspec:<V_narrow_pack> [(match_operand:<V_narrow_pack> 1 "s_register_operand" "0")
-                      (match_operand:MVE_5 2 "s_register_operand" "w")
-                      (match_operand:SI 3 "<MVE_pred3>" "<MVE_constraint3>")
-                      (match_operand:<MVE_VPRED> 4 "vpr_register_operand" "Up")]
-        VQRSHRUNBQ_M_N_S))
-  ]
-  "TARGET_HAVE_MVE"
-  "vpst\;vqrshrunbt.s%#<V_sz_elem>\t%q0, %q2, %3"
-  [(set_attr "type" "mve_move")
-   (set_attr "length""8")])
-
-;;
-;; [vqrshruntq_m_n_s])
-;;
-(define_insn "mve_vqrshruntq_m_n_s<mode>"
-  [
-   (set (match_operand:<V_narrow_pack> 0 "s_register_operand" "=w")
-       (unspec:<V_narrow_pack> [(match_operand:<V_narrow_pack> 1 "s_register_operand" "0")
-                      (match_operand:MVE_5 2 "s_register_operand" "w")
-                      (match_operand:SI 3 "<MVE_pred3>" "<MVE_constraint3>")
-                      (match_operand:<MVE_VPRED> 4 "vpr_register_operand" "Up")]
-        VQRSHRUNTQ_M_N_S))
-  ]
-  "TARGET_HAVE_MVE"
-  "vpst\;vqrshruntt.s%#<V_sz_elem>\t%q0, %q2, %3"
-  [(set_attr "type" "mve_move")
-   (set_attr "length""8")])
-
-;;
-;; [vqshrunbq_m_n_s])
-;;
-(define_insn "mve_vqshrunbq_m_n_s<mode>"
-  [
-   (set (match_operand:<V_narrow_pack> 0 "s_register_operand" "=w")
-       (unspec:<V_narrow_pack> [(match_operand:<V_narrow_pack> 1 "s_register_operand" "0")
-                      (match_operand:MVE_5 2 "s_register_operand" "w")
-                      (match_operand:SI 3 "<MVE_pred3>" "<MVE_constraint3>")
-                      (match_operand:<MVE_VPRED> 4 "vpr_register_operand" "Up")]
-        VQSHRUNBQ_M_N_S))
-  ]
-  "TARGET_HAVE_MVE"
-  "vpst\;vqshrunbt.s%#<V_sz_elem>\t%q0, %q2, %3"
-  [(set_attr "type" "mve_move")
-   (set_attr "length""8")])
-
-;;
-;; [vqshruntq_m_n_s])
-;;
-(define_insn "mve_vqshruntq_m_n_s<mode>"
-  [
-   (set (match_operand:<V_narrow_pack> 0 "s_register_operand" "=w")
-       (unspec:<V_narrow_pack> [(match_operand:<V_narrow_pack> 1 "s_register_operand" "0")
-                      (match_operand:MVE_5 2 "s_register_operand" "w")
-                      (match_operand:SI 3 "<MVE_pred3>" "<MVE_constraint3>")
-                      (match_operand:<MVE_VPRED> 4 "vpr_register_operand" "Up")]
-        VQSHRUNTQ_M_N_S))
-  ]
-  "TARGET_HAVE_MVE"
-  "vpst\;vqshruntt.s%#<V_sz_elem>\t%q0, %q2, %3"
-  [(set_attr "type" "mve_move")
-   (set_attr "length""8")])
-
 ;;
 ;; [vrmlaldavhaq_p_u])
 ;;
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