if (GET_CODE (op) == SYMBOL_REF
|| GET_CODE (op) == LABEL_REF
|| (GET_CODE (op) == UNSPEC
- && (XINT (op, 1) == 6
- || XINT (op, 1) == 7
- || XINT (op, 1) == 15)))
+ && (XINT (op, 1) == UNSPEC_GOT
+ || XINT (op, 1) == UNSPEC_GOTOFF
+ || XINT (op, 1) == UNSPEC_GOTPCREL)))
return 1;
if (GET_CODE (op) != PLUS
|| GET_CODE (XEXP (op, 1)) != CONST_INT)
return 1;
/* Only @GOTOFF gets offsets. */
if (GET_CODE (op) != UNSPEC
- || XINT (op, 1) != 7)
+ || XINT (op, 1) != UNSPEC_GOTOFF)
return 0;
op = XVECEXP (op, 0, 0);
cases. */
case CONST:
if (GET_CODE (XEXP (value, 0)) == UNSPEC
- && XVECLEN (XEXP (value, 0), 0) == 1
- && XINT (XEXP (value, 0), 1) == 15)
+ && XINT (XEXP (value, 0), 1) == UNSPEC_GOTPCREL)
return 1;
else if (GET_CODE (XEXP (value, 0)) == PLUS)
{
|| GET_CODE (XEXP (term, 1)) == CONST_DOUBLE))
term = XEXP (term, 0);
if (GET_CODE (term) != UNSPEC
- || XVECLEN (term, 0) != 1
- || XINT (term, 1) != 15)
+ || XINT (term, 1) != UNSPEC_GOTPCREL)
return x;
term = XVECEXP (term, 0, 0);
term = XEXP (term, 0);
if (GET_CODE (term) != UNSPEC
- || XVECLEN (term, 0) != 1
- || XINT (term, 1) != 7)
+ || XINT (term, 1) != UNSPEC_GOTOFF)
return x;
term = XVECEXP (term, 0, 0);
/* We are unsafe to allow PLUS expressions. This limit allowed distance
of GOT tables. We should not need these anyway. */
if (GET_CODE (disp) != UNSPEC
- || XVECLEN (disp, 0) != 1
- || XINT (disp, 1) != 15)
+ || XINT (disp, 1) != UNSPEC_GOTPCREL)
return 0;
if (GET_CODE (XVECEXP (disp, 0, 0)) != SYMBOL_REF
disp = XEXP (disp, 0);
}
- if (GET_CODE (disp) != UNSPEC
- || XVECLEN (disp, 0) != 1)
+ if (GET_CODE (disp) != UNSPEC)
return 0;
/* Must be @GOT or @GOTOFF. */
switch (XINT (disp, 1))
{
- case 6: /* @GOT */
+ case UNSPEC_GOT:
return GET_CODE (XVECEXP (disp, 0, 0)) == SYMBOL_REF;
-
- case 7: /* @GOTOFF */
+ case UNSPEC_GOTOFF:
return local_symbolic_operand (XVECEXP (disp, 0, 0), Pmode);
}
base address (@GOTOFF). */
current_function_uses_pic_offset_table = 1;
- new = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), 7);
+ new = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_GOTOFF);
new = gen_rtx_CONST (Pmode, new);
new = gen_rtx_PLUS (Pmode, pic_offset_table_rtx, new);
if (TARGET_64BIT)
{
current_function_uses_pic_offset_table = 1;
- new = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), 15);
+ new = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_GOTPCREL);
new = gen_rtx_CONST (Pmode, new);
new = gen_rtx_MEM (Pmode, new);
RTX_UNCHANGING_P (new) = 1;
Global Offset Table (@GOT). */
current_function_uses_pic_offset_table = 1;
- new = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), 6);
+ new = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_GOT);
new = gen_rtx_CONST (Pmode, new);
new = gen_rtx_PLUS (Pmode, pic_offset_table_rtx, new);
new = gen_rtx_MEM (Pmode, new);
if (!TARGET_64BIT)
{
current_function_uses_pic_offset_table = 1;
- new = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, op0), 7);
+ new = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, op0),
+ UNSPEC_GOTOFF);
new = gen_rtx_PLUS (Pmode, new, op1);
new = gen_rtx_CONST (Pmode, new);
new = gen_rtx_PLUS (Pmode, pic_offset_table_rtx, new);
output_pic_addr_const (file, XVECEXP (x, 0, 0), code);
switch (XINT (x, 1))
{
- case 6:
+ case UNSPEC_GOT:
fputs ("@GOT", file);
break;
- case 7:
+ case UNSPEC_GOTOFF:
fputs ("@GOTOFF", file);
break;
- case 8:
+ case UNSPEC_PLT:
fputs ("@PLT", file);
break;
- case 15:
+ case UNSPEC_GOTPCREL:
fputs ("@GOTPCREL(%RIP)", file);
break;
default:
{
if (GET_CODE (x) != CONST
|| GET_CODE (XEXP (x, 0)) != UNSPEC
- || XINT (XEXP (x, 0), 1) != 15
+ || XINT (XEXP (x, 0), 1) != UNSPEC_GOTPCREL
|| GET_CODE (orig_x) != MEM)
return orig_x;
return XVECEXP (XEXP (x, 0), 0, 0);
x = XEXP (XEXP (x, 1), 0);
if (GET_CODE (x) == UNSPEC
- && ((XINT (x, 1) == 6 && GET_CODE (orig_x) == MEM)
- || (XINT (x, 1) == 7 && GET_CODE (orig_x) != MEM)))
+ && ((XINT (x, 1) == UNSPEC_GOT && GET_CODE (orig_x) == MEM)
+ || (XINT (x, 1) == UNSPEC_GOTOFF && GET_CODE (orig_x) != MEM)))
{
if (y)
return gen_rtx_PLUS (Pmode, y, XVECEXP (x, 0, 0));
if (GET_CODE (x) == PLUS
&& GET_CODE (XEXP (x, 0)) == UNSPEC
&& GET_CODE (XEXP (x, 1)) == CONST_INT
- && ((XINT (XEXP (x, 0), 1) == 6 && GET_CODE (orig_x) == MEM)
- || (XINT (XEXP (x, 0), 1) == 7 && GET_CODE (orig_x) != MEM)))
+ && ((XINT (XEXP (x, 0), 1) == UNSPEC_GOT && GET_CODE (orig_x) == MEM)
+ || (XINT (XEXP (x, 0), 1) == UNSPEC_GOTOFF
+ && GET_CODE (orig_x) != MEM)))
{
x = gen_rtx_PLUS (VOIDmode, XVECEXP (XEXP (x, 0), 0, 0), XEXP (x, 1));
if (y)
else
{
tmp = gen_rtx_COMPARE (fpcmp_mode, op0, op1);
- tmp2 = gen_rtx_UNSPEC (HImode, gen_rtvec (1, tmp), 9);
+ tmp2 = gen_rtx_UNSPEC (HImode, gen_rtvec (1, tmp), UNSPEC_FNSTSW);
if (!scratch)
scratch = gen_reg_rtx (HImode);
emit_insn (gen_rtx_SET (VOIDmode, scratch, tmp2));
{
/* Sadness wrt reg-stack pops killing fpsr -- gotta get fnstsw first. */
tmp = gen_rtx_COMPARE (fpcmp_mode, op0, op1);
- tmp2 = gen_rtx_UNSPEC (HImode, gen_rtvec (1, tmp), 9);
+ tmp2 = gen_rtx_UNSPEC (HImode, gen_rtvec (1, tmp), UNSPEC_FNSTSW);
if (!scratch)
scratch = gen_reg_rtx (HImode);
emit_insn (gen_rtx_SET (VOIDmode, scratch, tmp2));
;; 'k' Likewise, print the SImode name of the register.
;; 'h' Print the QImode name for a "high" register, either ah, bh, ch or dh.
;; 'y' Print "st(0)" instead of "st" as a register.
-;;
+
;; UNSPEC usage:
-;; 0 This is a `scas' operation. The mode of the UNSPEC is always SImode.
-;; operand 0 is the memory address to scan.
-;; operand 1 is a register containing the value to scan for. The mode
-;; of the scas opcode will be the same as the mode of this operand.
-;; operand 2 is the known alignment of operand 0.
-;; 1 This is a `sin' operation. The mode of the UNSPEC is MODE_FLOAT.
-;; operand 0 is the argument for `sin'.
-;; 2 This is a `cos' operation. The mode of the UNSPEC is MODE_FLOAT.
-;; operand 0 is the argument for `cos'.
-;; 3 This is part of a `stack probe' operation. The mode of the UNSPEC is
-;; always SImode. operand 0 is the size of the stack allocation.
-;; 4 This is the source of a fake SET of the frame pointer which is used to
-;; prevent insns referencing it being scheduled across the initial
-;; decrement of the stack pointer.
-;; 5 This is a `bsf' operation.
-;; 6 This is the @GOT offset of a PIC address.
-;; 7 This is the @GOTOFF offset of a PIC address.
-;; 8 This is a reference to a symbol's @PLT address.
-;; 9 This is an `fnstsw' operation.
-;; 10 This is a `sahf' operation.
-;; 11 This is a `fstcw' operation
-;; 12 This is behaviour of add when setting carry flag.
-;; 13 This is a `eh_return' placeholder.
-
-;; For SSE/MMX support:
-;; 30 This is `fix', guaranteed to be truncating.
-;; 31 This is a `emms' operation.
-;; 32 This is a `maskmov' operation.
-;; 33 This is a `movmsk' operation.
-;; 34 This is a `non-temporal' move.
-;; 36 This is used to distinguish COMISS from UCOMISS.
-;; 37 This is a `ldmxcsr' operation.
-;; 38 This is a forced `movaps' instruction (rather than whatever movti does)
-;; 39 This is a forced `movups' instruction (rather than whatever movti does)
-;; 40 This is a `stmxcsr' operation.
-;; 41 This is a `shuffle' operation.
-;; 42 This is a `rcp' operation.
-;; 43 This is a `rsqsrt' operation.
-;; 44 This is a `sfence' operation.
-;; 45 This is a noop to prevent excessive combiner cleverness.
-;; 46 This is a `femms' operation.
-;; 49 This is a 'pavgusb' operation.
-;; 50 This is a `pfrcp' operation.
-;; 51 This is a `pfrcpit1' operation.
-;; 52 This is a `pfrcpit2' operation.
-;; 53 This is a `pfrsqrt' operation.
-;; 54 This is a `pfrsqrit1' operation.
-;; 55 This is a `pshuflw' operation.
-;; 56 This is a `pshufhw' operation.
-;; 57 This is a `clflush' operation.
-;; 58 This is a `sfence' operation.
-;; 59 This is a `mfence' operation.
-;; 60 This is a `lfence' operation.
-;; 61 This is a `psadbw' operation.
+
+(define_constants
+ [(UNSPEC_SCAS 0)
+ (UNSPEC_SIN 1)
+ (UNSPEC_COS 2)
+ (UNSPEC_STACK_PROBE 3)
+ (UNSPEC_STACK_ALLOC 4)
+ (UNSPEC_BSF 5)
+ (UNSPEC_GOT 6)
+ (UNSPEC_GOTOFF 7)
+ (UNSPEC_PLT 8)
+ (UNSPEC_FNSTSW 9)
+ (UNSPEC_SAHF 10)
+ (UNSPEC_FSTCW 11)
+ (UNSPEC_ADD_CARRY 12)
+ (UNSPEC_SSE_PROLOGUE_SAVE 13)
+ (UNSPEC_FLDCW 14)
+ (UNSPEC_GOTPCREL 15)
+
+ ; For SSE/MMX support:
+ (UNSPEC_FIX 30)
+ (UNSPEC_MASKMOV 32)
+ (UNSPEC_MOVMSK 33)
+ (UNSPEC_MOVNT 34)
+ (UNSPEC_MOVA 38)
+ (UNSPEC_MOVU 39)
+ (UNSPEC_SHUFFLE 41)
+ (UNSPEC_RCP 42)
+ (UNSPEC_RSQRT 43)
+ (UNSPEC_SFENCE 44)
+ (UNSPEC_NOP 45) ; prevents combiner cleverness
+ (UNSPEC_PAVGUSB 49)
+ (UNSPEC_PFRCP 50)
+ (UNSPEC_PFRCPIT1 51)
+ (UNSPEC_PFRCPIT2 52)
+ (UNSPEC_PFRSQRT 53)
+ (UNSPEC_PFRSQIT1 54)
+ (UNSPEC_PSHUFLW 55)
+ (UNSPEC_PSHUFHW 56)
+ (UNSPEC_MFENCE 59)
+ (UNSPEC_LFENCE 60)
+ (UNSPEC_PSADBW 61)
+ ])
+
+(define_constants
+ [(UNSPECV_BLOCKAGE 0)
+ (UNSPECV_PROLOGUE_SET_GOT 1)
+ (UNSPECV_PROLOGUE_GET_PC 2)
+ (UNSPECV_EH_RETURN 13)
+ (UNSPECV_EMMS 31)
+ (UNSPECV_LDMXCSR 37)
+ (UNSPECV_STMXCSR 40)
+ (UNSPECV_FEMMS 46)
+ (UNSPECV_CLFLUSH 57)
+ ])
;; Insns whose names begin with "x86_" are emitted by gen_FOO calls
;; from i386.c.
[(set (match_operand:HI 0 "register_operand" "=a")
(unspec:HI
[(compare:CCFP (match_operand 1 "register_operand" "f")
- (match_operand 2 "const0_operand" "X"))] 9))]
+ (match_operand 2 "const0_operand" "X"))]
+ UNSPEC_FNSTSW))]
"TARGET_80387
&& FLOAT_MODE_P (GET_MODE (operands[1]))
&& GET_MODE (operands[1]) == GET_MODE (operands[2])"
(unspec:HI
[(compare:CCFP
(match_operand:SF 1 "register_operand" "f")
- (match_operand:SF 2 "nonimmediate_operand" "fm"))] 9))]
+ (match_operand:SF 2 "nonimmediate_operand" "fm"))]
+ UNSPEC_FNSTSW))]
"TARGET_80387"
"* return output_fp_compare (insn, operands, 2, 0);"
[(set_attr "type" "fcmp")
(unspec:HI
[(compare:CCFP
(match_operand:DF 1 "register_operand" "f")
- (match_operand:DF 2 "nonimmediate_operand" "fm"))] 9))]
+ (match_operand:DF 2 "nonimmediate_operand" "fm"))]
+ UNSPEC_FNSTSW))]
"TARGET_80387"
"* return output_fp_compare (insn, operands, 2, 0);"
[(set_attr "type" "multi")
(unspec:HI
[(compare:CCFP
(match_operand:XF 1 "register_operand" "f")
- (match_operand:XF 2 "register_operand" "f"))] 9))]
+ (match_operand:XF 2 "register_operand" "f"))]
+ UNSPEC_FNSTSW))]
"!TARGET_64BIT && TARGET_80387"
"* return output_fp_compare (insn, operands, 2, 0);"
[(set_attr "type" "multi")
(unspec:HI
[(compare:CCFP
(match_operand:TF 1 "register_operand" "f")
- (match_operand:TF 2 "register_operand" "f"))] 9))]
+ (match_operand:TF 2 "register_operand" "f"))]
+ UNSPEC_FNSTSW))]
"TARGET_80387"
"* return output_fp_compare (insn, operands, 2, 0);"
[(set_attr "type" "multi")
(unspec:HI
[(compare:CCFPU
(match_operand 1 "register_operand" "f")
- (match_operand 2 "register_operand" "f"))] 9))]
+ (match_operand 2 "register_operand" "f"))]
+ UNSPEC_FNSTSW))]
"TARGET_80387
&& FLOAT_MODE_P (GET_MODE (operands[1]))
&& GET_MODE (operands[1]) == GET_MODE (operands[2])"
(define_insn "x86_fnstsw_1"
[(set (match_operand:HI 0 "register_operand" "=a")
- (unspec:HI [(reg 18)] 9))]
+ (unspec:HI [(reg 18)] UNSPEC_FNSTSW))]
"TARGET_80387"
"fnstsw\t%0"
[(set_attr "length" "2")
(define_insn "x86_sahf_1"
[(set (reg:CC 17)
- (unspec:CC [(match_operand:HI 0 "register_operand" "a")] 10))]
+ (unspec:CC [(match_operand:HI 0 "register_operand" "a")] UNSPEC_SAHF))]
"!TARGET_64BIT"
"sahf"
[(set_attr "length" "1")
;; %% Not used yet.
(define_insn "x86_fnstcw_1"
[(set (match_operand:HI 0 "memory_operand" "=m")
- (unspec:HI [(reg:HI 18)] 11))]
+ (unspec:HI [(reg:HI 18)] UNSPEC_FSTCW))]
"TARGET_80387"
"fnstcw\t%0"
[(set_attr "length" "2")
(define_insn "x86_fldcw_1"
[(set (reg:HI 18)
- (unspec:HI [(match_operand:HI 0 "memory_operand" "m")] 12))]
+ (unspec:HI [(match_operand:HI 0 "memory_operand" "m")] UNSPEC_FLDCW))]
"TARGET_80387"
"fldcw\t%0"
[(set_attr "length" "2")
(match_operand:DI 2 "general_operand" "")))
(clobber (reg:CC 17))]
"!TARGET_64BIT && reload_completed"
- [(parallel [(set (reg:CC 17) (unspec:CC [(match_dup 1) (match_dup 2)] 12))
+ [(parallel [(set (reg:CC 17) (unspec:CC [(match_dup 1) (match_dup 2)]
+ UNSPEC_ADD_CARRY))
(set (match_dup 0) (plus:SI (match_dup 1) (match_dup 2)))])
(parallel [(set (match_dup 3)
(plus:SI (plus:SI (ltu:SI (reg:CC 17) (const_int 0))
(set_attr "ppro_uops" "few")])
(define_insn "*adddi3_cc_rex64"
- [(set (reg:CC 17) (unspec:CC [(match_operand:DI 1 "nonimmediate_operand" "%0,0")
- (match_operand:DI 2 "x86_64_general_operand" "re,rm")] 12))
+ [(set (reg:CC 17)
+ (unspec:CC [(match_operand:DI 1 "nonimmediate_operand" "%0,0")
+ (match_operand:DI 2 "x86_64_general_operand" "re,rm")]
+ UNSPEC_ADD_CARRY))
(set (match_operand:DI 0 "nonimmediate_operand" "=rm,r")
(plus:DI (match_dup 1) (match_dup 2)))]
"TARGET_64BIT && ix86_binary_operator_ok (PLUS, DImode, operands)"
(set_attr "ppro_uops" "few")])
(define_insn "*addsi3_cc"
- [(set (reg:CC 17) (unspec:CC [(match_operand:SI 1 "nonimmediate_operand" "%0,0")
- (match_operand:SI 2 "general_operand" "ri,rm")] 12))
+ [(set (reg:CC 17)
+ (unspec:CC [(match_operand:SI 1 "nonimmediate_operand" "%0,0")
+ (match_operand:SI 2 "general_operand" "ri,rm")]
+ UNSPEC_ADD_CARRY))
(set (match_operand:SI 0 "nonimmediate_operand" "=rm,r")
(plus:SI (match_dup 1) (match_dup 2)))]
"ix86_binary_operator_ok (PLUS, SImode, operands)"
(set_attr "mode" "SI")])
(define_insn "addqi3_cc"
- [(set (reg:CC 17) (unspec:CC [(match_operand:QI 1 "nonimmediate_operand" "%0,0")
- (match_operand:QI 2 "general_operand" "qi,qm")] 12))
+ [(set (reg:CC 17)
+ (unspec:CC [(match_operand:QI 1 "nonimmediate_operand" "%0,0")
+ (match_operand:QI 2 "general_operand" "qi,qm")]
+ UNSPEC_ADD_CARRY))
(set (match_operand:QI 0 "nonimmediate_operand" "=qm,q")
(plus:QI (match_dup 1) (match_dup 2)))]
"ix86_binary_operator_ok (PLUS, QImode, operands)"
;; all of memory. This blocks insns from being moved across this point.
(define_insn "blockage"
- [(unspec_volatile [(const_int 0)] 0)]
+ [(unspec_volatile [(const_int 0)] UNSPECV_BLOCKAGE)]
""
""
[(set_attr "length" "0")])
(unspec_volatile:SI
[(plus:SI (match_dup 0)
(plus:SI (match_operand:SI 1 "symbolic_operand" "")
- (minus:SI (pc) (match_operand 2 "" ""))))] 1))
+ (minus:SI (pc) (match_operand 2 "" ""))))]
+ UNSPECV_PROLOGUE_SET_GOT))
(clobber (reg:CC 17))]
"!TARGET_64BIT"
{
(define_insn "prologue_get_pc"
[(set (match_operand:SI 0 "register_operand" "=r")
- (unspec_volatile:SI [(plus:SI (pc) (match_operand 1 "" ""))] 2))]
+ (unspec_volatile:SI [(plus:SI (pc) (match_operand 1 "" ""))]
+ UNSPECV_PROLOGUE_GET_PC))]
"!TARGET_64BIT"
{
if (GET_CODE (operands[1]) == LABEL_REF)
})
(define_insn_and_split "eh_return_si"
- [(unspec_volatile [(match_operand:SI 0 "register_operand" "c")] 13)]
+ [(unspec_volatile [(match_operand:SI 0 "register_operand" "c")]
+ UNSPECV_EH_RETURN)]
"!TARGET_64BIT"
"#"
"reload_completed"
"ix86_expand_epilogue (2); DONE;")
(define_insn_and_split "eh_return_di"
- [(unspec_volatile [(match_operand:DI 0 "register_operand" "c")] 13)]
+ [(unspec_volatile [(match_operand:DI 0 "register_operand" "c")]
+ UNSPECV_EH_RETURN)]
"TARGET_64BIT"
"#"
"reload_completed"
(compare:CCZ (match_operand:SI 1 "nonimmediate_operand" "rm")
(const_int 0)))
(set (match_operand:SI 0 "register_operand" "=r")
- (unspec:SI [(match_dup 1)] 5))]
+ (unspec:SI [(match_dup 1)] UNSPEC_BSF))]
""
"bsf{l}\t{%1, %0|%0, %1}"
[(set_attr "prefix_0f" "1")
(define_insn "sindf2"
[(set (match_operand:DF 0 "register_operand" "=f")
- (unspec:DF [(match_operand:DF 1 "register_operand" "0")] 1))]
+ (unspec:DF [(match_operand:DF 1 "register_operand" "0")] UNSPEC_SIN))]
"! TARGET_NO_FANCY_MATH_387 && TARGET_80387
&& flag_unsafe_math_optimizations"
"fsin"
(define_insn "sinsf2"
[(set (match_operand:SF 0 "register_operand" "=f")
- (unspec:SF [(match_operand:SF 1 "register_operand" "0")] 1))]
+ (unspec:SF [(match_operand:SF 1 "register_operand" "0")] UNSPEC_SIN))]
"! TARGET_NO_FANCY_MATH_387 && TARGET_80387
&& flag_unsafe_math_optimizations"
"fsin"
(define_insn "*sinextendsfdf2"
[(set (match_operand:DF 0 "register_operand" "=f")
(unspec:DF [(float_extend:DF
- (match_operand:SF 1 "register_operand" "0"))] 1))]
+ (match_operand:SF 1 "register_operand" "0"))]
+ UNSPEC_SIN))]
"! TARGET_NO_FANCY_MATH_387 && TARGET_80387
&& flag_unsafe_math_optimizations"
"fsin"
(define_insn "sinxf2"
[(set (match_operand:XF 0 "register_operand" "=f")
- (unspec:XF [(match_operand:XF 1 "register_operand" "0")] 1))]
+ (unspec:XF [(match_operand:XF 1 "register_operand" "0")] UNSPEC_SIN))]
"!TARGET_64BIT && TARGET_80387 && !TARGET_NO_FANCY_MATH_387
&& flag_unsafe_math_optimizations"
"fsin"
(define_insn "sintf2"
[(set (match_operand:TF 0 "register_operand" "=f")
- (unspec:TF [(match_operand:TF 1 "register_operand" "0")] 1))]
+ (unspec:TF [(match_operand:TF 1 "register_operand" "0")] UNSPEC_SIN))]
"! TARGET_NO_FANCY_MATH_387 && TARGET_80387
&& flag_unsafe_math_optimizations"
"fsin"
(define_insn "cosdf2"
[(set (match_operand:DF 0 "register_operand" "=f")
- (unspec:DF [(match_operand:DF 1 "register_operand" "0")] 2))]
+ (unspec:DF [(match_operand:DF 1 "register_operand" "0")] UNSPEC_COS))]
"! TARGET_NO_FANCY_MATH_387 && TARGET_80387
&& flag_unsafe_math_optimizations"
"fcos"
(define_insn "cossf2"
[(set (match_operand:SF 0 "register_operand" "=f")
- (unspec:SF [(match_operand:SF 1 "register_operand" "0")] 2))]
+ (unspec:SF [(match_operand:SF 1 "register_operand" "0")] UNSPEC_COS))]
"! TARGET_NO_FANCY_MATH_387 && TARGET_80387
&& flag_unsafe_math_optimizations"
"fcos"
(define_insn "*cosextendsfdf2"
[(set (match_operand:DF 0 "register_operand" "=f")
(unspec:DF [(float_extend:DF
- (match_operand:SF 1 "register_operand" "0"))] 2))]
+ (match_operand:SF 1 "register_operand" "0"))]
+ UNSPEC_COS))]
"! TARGET_NO_FANCY_MATH_387 && TARGET_80387
&& flag_unsafe_math_optimizations"
"fcos"
(define_insn "cosxf2"
[(set (match_operand:XF 0 "register_operand" "=f")
- (unspec:XF [(match_operand:XF 1 "register_operand" "0")] 2))]
+ (unspec:XF [(match_operand:XF 1 "register_operand" "0")] UNSPEC_COS))]
"! TARGET_NO_FANCY_MATH_387 && TARGET_80387
&& flag_unsafe_math_optimizations"
"fcos"
(define_insn "costf2"
[(set (match_operand:TF 0 "register_operand" "=f")
- (unspec:TF [(match_operand:TF 1 "register_operand" "0")] 2))]
+ (unspec:TF [(match_operand:TF 1 "register_operand" "0")] UNSPEC_COS))]
"! TARGET_NO_FANCY_MATH_387 && TARGET_80387
&& flag_unsafe_math_optimizations"
"fcos"
[(set (match_operand:SI 0 "register_operand" "")
(unspec:SI [(match_operand:BLK 1 "general_operand" "")
(match_operand:QI 2 "immediate_operand" "")
- (match_operand 3 "immediate_operand" "")] 0))]
+ (match_operand 3 "immediate_operand" "")] UNSPEC_SCAS))]
""
{
if (ix86_expand_strlen (operands[0], operands[1], operands[2], operands[3]))
[(set (match_operand:DI 0 "register_operand" "")
(unspec:DI [(match_operand:BLK 1 "general_operand" "")
(match_operand:QI 2 "immediate_operand" "")
- (match_operand 3 "immediate_operand" "")] 0))]
+ (match_operand 3 "immediate_operand" "")] UNSPEC_SCAS))]
""
{
if (ix86_expand_strlen (operands[0], operands[1], operands[2], operands[3]))
(unspec:SI [(mem:BLK (match_operand:SI 5 "register_operand" "1"))
(match_operand:QI 2 "register_operand" "a")
(match_operand:SI 3 "immediate_operand" "i")
- (match_operand:SI 4 "register_operand" "0")] 0))
+ (match_operand:SI 4 "register_operand" "0")] UNSPEC_SCAS))
(use (reg:SI 19))
(clobber (match_operand:SI 1 "register_operand" "=D"))
(clobber (reg:CC 17))]
(unspec:DI [(mem:BLK (match_operand:DI 5 "register_operand" "1"))
(match_operand:QI 2 "register_operand" "a")
(match_operand:DI 3 "immediate_operand" "i")
- (match_operand:DI 4 "register_operand" "0")] 0))
+ (match_operand:DI 4 "register_operand" "0")] UNSPEC_SCAS))
(use (reg:SI 19))
(clobber (match_operand:DI 1 "register_operand" "=D"))
(clobber (reg:CC 17))]
})
(define_insn "allocate_stack_worker_1"
- [(unspec:SI [(match_operand:SI 0 "register_operand" "a")] 3)
+ [(unspec:SI [(match_operand:SI 0 "register_operand" "a")] UNSPEC_STACK_PROBE)
(set (reg:SI 7) (minus:SI (reg:SI 7) (match_dup 0)))
(clobber (match_dup 0))
(clobber (reg:CC 17))]
(set_attr "length" "5")])
(define_insn "allocate_stack_worker_rex64"
- [(unspec:DI [(match_operand:DI 0 "register_operand" "a")] 3)
+ [(unspec:DI [(match_operand:DI 0 "register_operand" "a")] UNSPEC_STACK_PROBE)
(set (reg:DI 7) (minus:DI (reg:DI 7) (match_dup 0)))
(clobber (match_dup 0))
(clobber (reg:CC 17))]
;; movaps or movups
(define_insn "sse_movaps"
[(set (match_operand:V4SF 0 "nonimmediate_operand" "=x,m")
- (unspec:V4SF
- [(match_operand:V4SF 1 "nonimmediate_operand" "xm,x")] 38))]
+ (unspec:V4SF [(match_operand:V4SF 1 "nonimmediate_operand" "xm,x")]
+ UNSPEC_MOVA))]
"TARGET_SSE"
"@
movaps\t{%1, %0|%0, %1}
(define_insn "sse_movups"
[(set (match_operand:V4SF 0 "nonimmediate_operand" "=x,m")
- (unspec:V4SF
- [(match_operand:V4SF 1 "nonimmediate_operand" "xm,x")] 39))]
+ (unspec:V4SF [(match_operand:V4SF 1 "nonimmediate_operand" "xm,x")]
+ UNSPEC_MOVU))]
"TARGET_SSE"
"@
movups\t{%1, %0|%0, %1}
(define_insn "sse_movmskps"
[(set (match_operand:SI 0 "register_operand" "=r")
- (unspec:SI [(match_operand:V4SF 1 "register_operand" "x")] 33))]
+ (unspec:SI [(match_operand:V4SF 1 "register_operand" "x")]
+ UNSPEC_MOVMSK))]
"TARGET_SSE"
"movmskps\t{%1, %0|%0, %1}"
[(set_attr "type" "ssecvt")
(define_insn "mmx_pmovmskb"
[(set (match_operand:SI 0 "register_operand" "=r")
- (unspec:SI [(match_operand:V8QI 1 "register_operand" "y")] 33))]
+ (unspec:SI [(match_operand:V8QI 1 "register_operand" "y")]
+ UNSPEC_MOVMSK))]
"TARGET_SSE || TARGET_3DNOW_A"
"pmovmskb\t{%1, %0|%0, %1}"
[(set_attr "type" "ssecvt")
(define_insn "mmx_maskmovq"
[(set (mem:V8QI (match_operand:SI 0 "register_operand" "D"))
(unspec:V8QI [(match_operand:V8QI 1 "register_operand" "y")
- (match_operand:V8QI 2 "register_operand" "y")] 32))]
+ (match_operand:V8QI 2 "register_operand" "y")]
+ UNSPEC_MASKMOV))]
"(TARGET_SSE || TARGET_3DNOW_A) && !TARGET_64BIT"
;; @@@ check ordering of operands in intel/nonintel syntax
"maskmovq\t{%2, %1|%1, %2}"
(define_insn "mmx_maskmovq_rex"
[(set (mem:V8QI (match_operand:DI 0 "register_operand" "D"))
(unspec:V8QI [(match_operand:V8QI 1 "register_operand" "y")
- (match_operand:V8QI 2 "register_operand" "y")] 32))]
+ (match_operand:V8QI 2 "register_operand" "y")]
+ UNSPEC_MASKMOV))]
"(TARGET_SSE || TARGET_3DNOW_A) && TARGET_64BIT"
;; @@@ check ordering of operands in intel/nonintel syntax
"maskmovq\t{%2, %1|%1, %2}"
(define_insn "sse_movntv4sf"
[(set (match_operand:V4SF 0 "memory_operand" "=m")
- (unspec:V4SF [(match_operand:V4SF 1 "register_operand" "x")] 34))]
+ (unspec:V4SF [(match_operand:V4SF 1 "register_operand" "x")]
+ UNSPEC_MOVNT))]
"TARGET_SSE"
"movntps\t{%1, %0|%0, %1}"
[(set_attr "type" "ssemov")
(define_insn "sse_movntdi"
[(set (match_operand:DI 0 "memory_operand" "=m")
- (unspec:DI [(match_operand:DI 1 "register_operand" "y")] 34))]
+ (unspec:DI [(match_operand:DI 1 "register_operand" "y")]
+ UNSPEC_MOVNT))]
"TARGET_SSE || TARGET_3DNOW_A"
"movntq\t{%1, %0|%0, %1}"
[(set_attr "type" "mmxmov")
[(set (match_operand:V4SF 0 "register_operand" "=x")
(unspec:V4SF [(match_operand:V4SF 1 "register_operand" "0")
(match_operand:V4SF 2 "nonimmediate_operand" "xm")
- (match_operand:SI 3 "immediate_operand" "i")] 41))]
+ (match_operand:SI 3 "immediate_operand" "i")]
+ UNSPEC_SHUFFLE))]
"TARGET_SSE"
;; @@@ check operand order for intel/nonintel syntax
"shufps\t{%3, %2, %0|%0, %2, %3}"
(define_insn "rcpv4sf2"
[(set (match_operand:V4SF 0 "register_operand" "=x")
(unspec:V4SF
- [(match_operand:V4SF 1 "nonimmediate_operand" "xm")] 42))]
+ [(match_operand:V4SF 1 "nonimmediate_operand" "xm")] UNSPEC_RCP))]
"TARGET_SSE"
"rcpps\t{%1, %0|%0, %1}"
[(set_attr "type" "sse")
(define_insn "vmrcpv4sf2"
[(set (match_operand:V4SF 0 "register_operand" "=x")
(vec_merge:V4SF
- (unspec:V4SF [(match_operand:V4SF 1 "nonimmediate_operand" "xm")] 42)
+ (unspec:V4SF [(match_operand:V4SF 1 "nonimmediate_operand" "xm")]
+ UNSPEC_RCP)
(match_operand:V4SF 2 "register_operand" "0")
(const_int 1)))]
"TARGET_SSE"
(define_insn "rsqrtv4sf2"
[(set (match_operand:V4SF 0 "register_operand" "=x")
(unspec:V4SF
- [(match_operand:V4SF 1 "nonimmediate_operand" "xm")] 43))]
+ [(match_operand:V4SF 1 "nonimmediate_operand" "xm")] UNSPEC_RSQRT))]
"TARGET_SSE"
"rsqrtps\t{%1, %0|%0, %1}"
[(set_attr "type" "sse")
(define_insn "vmrsqrtv4sf2"
[(set (match_operand:V4SF 0 "register_operand" "=x")
(vec_merge:V4SF
- (unspec:V4SF [(match_operand:V4SF 1 "nonimmediate_operand" "xm")] 43)
+ (unspec:V4SF [(match_operand:V4SF 1 "nonimmediate_operand" "xm")]
+ UNSPEC_RSQRT)
(match_operand:V4SF 2 "register_operand" "0")
(const_int 1)))]
"TARGET_SSE"
;; this insn.
(define_insn "sse_clrv4sf"
[(set (match_operand:V4SF 0 "register_operand" "=x")
- (unspec:V4SF [(const_int 0)] 45))]
+ (unspec:V4SF [(const_int 0)] UNSPEC_NOP))]
"TARGET_SSE"
"xorps\t{%0, %0|%0, %0}"
[(set_attr "type" "sselog")
(define_insn "cvttps2pi"
[(set (match_operand:V2SI 0 "register_operand" "=y")
(vec_select:V2SI
- (unspec:V4SI [(match_operand:V4SF 1 "nonimmediate_operand" "xm")] 30)
+ (unspec:V4SI [(match_operand:V4SF 1 "nonimmediate_operand" "xm")]
+ UNSPEC_FIX)
(parallel [(const_int 0) (const_int 1)])))]
"TARGET_SSE"
"cvttps2pi\t{%1, %0|%0, %1}"
(define_insn "cvttss2si"
[(set (match_operand:SI 0 "register_operand" "=r")
(vec_select:SI
- (unspec:V4SI [(match_operand:V4SF 1 "nonimmediate_operand" "xm")] 30)
+ (unspec:V4SI [(match_operand:V4SF 1 "nonimmediate_operand" "xm")]
+ UNSPEC_FIX)
(parallel [(const_int 0)])))]
"TARGET_SSE"
"cvttss2si\t{%1, %0|%0, %1}"
[(set (match_operand:DI 0 "register_operand" "=y")
(unspec:DI
[(ior:DI (match_operand:DI 1 "register_operand" "0")
- (match_operand:DI 2 "nonimmediate_operand" "ym"))] 45))]
+ (match_operand:DI 2 "nonimmediate_operand" "ym"))]
+ UNSPEC_NOP))]
"TARGET_MMX"
"por\t{%2, %0|%0, %2}"
[(set_attr "type" "mmxadd")
[(set (match_operand:DI 0 "register_operand" "=y")
(unspec:DI
[(xor:DI (match_operand:DI 1 "register_operand" "0")
- (match_operand:DI 2 "nonimmediate_operand" "ym"))] 45))]
+ (match_operand:DI 2 "nonimmediate_operand" "ym"))]
+ UNSPEC_NOP))]
"TARGET_MMX"
"pxor\t{%2, %0|%0, %2}"
[(set_attr "type" "mmxadd")
;; they are live.
(define_insn "mmx_clrdi"
[(set (match_operand:DI 0 "register_operand" "=y")
- (unspec:DI [(const_int 0)] 45))]
+ (unspec:DI [(const_int 0)] UNSPEC_NOP))]
"TARGET_MMX"
"pxor\t{%0, %0|%0, %0}"
[(set_attr "type" "mmxadd")
[(set (match_operand:DI 0 "register_operand" "=y")
(unspec:DI
[(and:DI (match_operand:DI 1 "register_operand" "0")
- (match_operand:DI 2 "nonimmediate_operand" "ym"))] 45))]
+ (match_operand:DI 2 "nonimmediate_operand" "ym"))]
+ UNSPEC_NOP))]
"TARGET_MMX"
"pand\t{%2, %0|%0, %2}"
[(set_attr "type" "mmxadd")
[(set (match_operand:DI 0 "register_operand" "=y")
(unspec:DI
[(and:DI (not:DI (match_operand:DI 1 "register_operand" "0"))
- (match_operand:DI 2 "nonimmediate_operand" "ym"))] 45))]
+ (match_operand:DI 2 "nonimmediate_operand" "ym"))]
+ UNSPEC_NOP))]
"TARGET_MMX"
"pandn\t{%2, %0|%0, %2}"
[(set_attr "type" "mmxadd")
(define_insn "mmx_psadbw"
[(set (match_operand:DI 0 "register_operand" "=y")
(unspec:DI [(match_operand:V8QI 1 "register_operand" "0")
- (match_operand:V8QI 2 "nonimmediate_operand" "ym")] 61))]
+ (match_operand:V8QI 2 "nonimmediate_operand" "ym")]
+ UNSPEC_PSADBW))]
"TARGET_SSE || TARGET_3DNOW_A"
"psadbw\t{%2, %0|%0, %2}"
[(set_attr "type" "mmxshft")
(define_insn "mmx_pshufw"
[(set (match_operand:V4HI 0 "register_operand" "=y")
(unspec:V4HI [(match_operand:V4HI 1 "register_operand" "0")
- (match_operand:SI 2 "immediate_operand" "i")] 41))]
+ (match_operand:SI 2 "immediate_operand" "i")]
+ UNSPEC_SHUFFLE))]
"TARGET_SSE || TARGET_3DNOW_A"
"pshufw\t{%2, %1, %0|%0, %1, %2}"
[(set_attr "type" "mmxcvt")
[(set (match_operand:DI 0 "register_operand" "=y")
(unspec:DI
[(lshiftrt:DI (match_operand:DI 1 "register_operand" "0")
- (match_operand:DI 2 "nonmemory_operand" "yi"))] 45))]
+ (match_operand:DI 2 "nonmemory_operand" "yi"))]
+ UNSPEC_NOP))]
"TARGET_MMX"
"psrlq\t{%2, %0|%0, %2}"
[(set_attr "type" "mmxshft")
[(set (match_operand:DI 0 "register_operand" "=y")
(unspec:DI
[(ashift:DI (match_operand:DI 1 "register_operand" "0")
- (match_operand:DI 2 "nonmemory_operand" "yi"))] 45))]
+ (match_operand:DI 2 "nonmemory_operand" "yi"))]
+ UNSPEC_NOP))]
"TARGET_MMX"
"psllq\t{%2, %0|%0, %2}"
[(set_attr "type" "mmxshft")
;; Miscellaneous stuff
(define_insn "emms"
- [(unspec_volatile [(const_int 0)] 31)
+ [(unspec_volatile [(const_int 0)] UNSPECV_EMMS)
(clobber (reg:XF 8))
(clobber (reg:XF 9))
(clobber (reg:XF 10))
(set_attr "memory" "unknown")])
(define_insn "ldmxcsr"
- [(unspec_volatile [(match_operand:SI 0 "memory_operand" "m")] 37)]
+ [(unspec_volatile [(match_operand:SI 0 "memory_operand" "m")]
+ UNSPECV_LDMXCSR)]
"TARGET_MMX"
"ldmxcsr\t%0"
[(set_attr "type" "mmx")
(define_insn "stmxcsr"
[(set (match_operand:SI 0 "memory_operand" "=m")
- (unspec_volatile:SI [(const_int 0)] 40))]
+ (unspec_volatile:SI [(const_int 0)] UNSPECV_STMXCSR))]
"TARGET_MMX"
"stmxcsr\t%0"
[(set_attr "type" "mmx")
(define_expand "sfence"
[(set (match_dup 0)
- (unspec:BLK [(match_dup 0)] 44))]
+ (unspec:BLK [(match_dup 0)] UNSPEC_SFENCE))]
"TARGET_SSE || TARGET_3DNOW_A"
{
operands[0] = gen_rtx_MEM (BLKmode, gen_rtx_SCRATCH (Pmode));
(define_insn "*sfence_insn"
[(set (match_operand:BLK 0 "" "")
- (unspec:BLK [(match_dup 0)] 44))]
+ (unspec:BLK [(match_dup 0)] UNSPEC_SFENCE))]
"TARGET_SSE || TARGET_3DNOW_A"
"sfence"
[(set_attr "type" "sse")
(reg:DI 25)
(reg:DI 26)
(reg:DI 27)
- (reg:DI 28)] 13))
+ (reg:DI 28)] UNSPEC_SSE_PROLOGUE_SAVE))
(use (match_operand:DI 1 "register_operand" ""))
(use (match_operand:DI 2 "immediate_operand" ""))
(use (label_ref:DI (match_operand 3 "" "")))])]
(reg:DI 25)
(reg:DI 26)
(reg:DI 27)
- (reg:DI 28)] 13))
+ (reg:DI 28)] UNSPEC_SSE_PROLOGUE_SAVE))
(use (match_operand:DI 1 "register_operand" "r"))
(use (match_operand:DI 2 "const_int_operand" "i"))
(use (label_ref:DI (match_operand 3 "" "X")))]
(set_attr "mode" "V2SF")])
(define_insn "femms"
- [(unspec_volatile [(const_int 0)] 46)
+ [(unspec_volatile [(const_int 0)] UNSPECV_FEMMS)
(clobber (reg:XF 8))
(clobber (reg:XF 9))
(clobber (reg:XF 10))
[(set (match_operand:V8QI 0 "register_operand" "=y")
(unspec:V8QI
[(match_operand:V8QI 1 "register_operand" "0")
- (match_operand:V8QI 2 "nonimmediate_operand" "ym")] 49))]
+ (match_operand:V8QI 2 "nonimmediate_operand" "ym")]
+ UNSPEC_PAVGUSB))]
"TARGET_3DNOW"
"pavgusb\\t{%2, %0|%0, %2}"
[(set_attr "type" "mmxshft")
(define_insn "pfrcpv2sf2"
[(set (match_operand:V2SF 0 "register_operand" "=y")
- (unspec:V2SF [(match_operand:V2SF 1 "nonimmediate_operand" "ym")] 50))]
+ (unspec:V2SF [(match_operand:V2SF 1 "nonimmediate_operand" "ym")]
+ UNSPEC_PFRCP))]
"TARGET_3DNOW"
"pfrcp\\t{%1, %0|%0, %1}"
[(set_attr "type" "mmx")
(define_insn "pfrcpit1v2sf3"
[(set (match_operand:V2SF 0 "register_operand" "=y")
(unspec:V2SF [(match_operand:V2SF 1 "register_operand" "0")
- (match_operand:V2SF 2 "nonimmediate_operand" "ym")] 51))]
+ (match_operand:V2SF 2 "nonimmediate_operand" "ym")]
+ UNSPEC_PFRCPIT1))]
"TARGET_3DNOW"
"pfrcpit1\\t{%2, %0|%0, %2}"
[(set_attr "type" "mmx")
(define_insn "pfrcpit2v2sf3"
[(set (match_operand:V2SF 0 "register_operand" "=y")
(unspec:V2SF [(match_operand:V2SF 1 "register_operand" "0")
- (match_operand:V2SF 2 "nonimmediate_operand" "ym")] 52))]
+ (match_operand:V2SF 2 "nonimmediate_operand" "ym")]
+ UNSPEC_PFRCPIT2))]
"TARGET_3DNOW"
"pfrcpit2\\t{%2, %0|%0, %2}"
[(set_attr "type" "mmx")
(define_insn "pfrsqrtv2sf2"
[(set (match_operand:V2SF 0 "register_operand" "=y")
- (unspec:V2SF [(match_operand:V2SF 1 "nonimmediate_operand" "ym")] 53))]
+ (unspec:V2SF [(match_operand:V2SF 1 "nonimmediate_operand" "ym")]
+ UNSPEC_PFRSQRT))]
"TARGET_3DNOW"
"pfrsqrt\\t{%1, %0|%0, %1}"
[(set_attr "type" "mmx")
(define_insn "pfrsqit1v2sf3"
[(set (match_operand:V2SF 0 "register_operand" "=y")
(unspec:V2SF [(match_operand:V2SF 1 "register_operand" "0")
- (match_operand:V2SF 2 "nonimmediate_operand" "ym")] 54))]
+ (match_operand:V2SF 2 "nonimmediate_operand" "ym")]
+ UNSPEC_PFRSQIT1))]
"TARGET_3DNOW"
"pfrsqit1\\t{%2, %0|%0, %2}"
[(set_attr "type" "mmx")
(define_insn "sse2_movmskpd"
[(set (match_operand:SI 0 "register_operand" "=r")
- (unspec:SI [(match_operand:V2DF 1 "register_operand" "x")] 33))]
+ (unspec:SI [(match_operand:V2DF 1 "register_operand" "x")]
+ UNSPEC_MOVMSK))]
"TARGET_SSE2"
"movmskpd\t{%1, %0|%0, %1}"
[(set_attr "type" "ssecvt")
(define_insn "sse2_pmovmskb"
[(set (match_operand:SI 0 "register_operand" "=r")
- (unspec:SI [(match_operand:V16QI 1 "register_operand" "x")] 33))]
+ (unspec:SI [(match_operand:V16QI 1 "register_operand" "x")]
+ UNSPEC_MOVMSK))]
"TARGET_SSE2"
"pmovmskb\t{%1, %0|%0, %1}"
[(set_attr "type" "ssecvt")
(define_insn "sse2_maskmovdqu"
[(set (mem:V16QI (match_operand:SI 0 "register_operand" "D"))
(unspec:V16QI [(match_operand:V16QI 1 "register_operand" "x")
- (match_operand:V16QI 2 "register_operand" "x")] 32))]
+ (match_operand:V16QI 2 "register_operand" "x")]
+ UNSPEC_MASKMOV))]
"TARGET_SSE2"
;; @@@ check ordering of operands in intel/nonintel syntax
"maskmovdqu\t{%2, %1|%1, %2}"
(define_insn "sse2_movntv2df"
[(set (match_operand:V2DF 0 "memory_operand" "=m")
- (unspec:V2DF [(match_operand:V2DF 1 "register_operand" "x")] 34))]
+ (unspec:V2DF [(match_operand:V2DF 1 "register_operand" "x")]
+ UNSPEC_MOVNT))]
"TARGET_SSE2"
"movntpd\t{%1, %0|%0, %1}"
[(set_attr "type" "ssecvt")
(define_insn "sse2_movntv2di"
[(set (match_operand:V2DI 0 "memory_operand" "=m")
- (unspec:V2DI [(match_operand:V2DI 1 "register_operand" "x")] 34))]
+ (unspec:V2DI [(match_operand:V2DI 1 "register_operand" "x")]
+ UNSPEC_MOVNT))]
"TARGET_SSE2"
"movntdq\t{%1, %0|%0, %1}"
[(set_attr "type" "ssecvt")
(define_insn "sse2_movntsi"
[(set (match_operand:SI 0 "memory_operand" "=m")
- (unspec:SI [(match_operand:SI 1 "register_operand" "r")] 34))]
+ (unspec:SI [(match_operand:SI 1 "register_operand" "r")]
+ UNSPEC_MOVNT))]
"TARGET_SSE2"
"movnti\t{%1, %0|%0, %1}"
[(set_attr "type" "ssecvt")
(define_insn "cvttps2dq"
[(set (match_operand:V4SI 0 "register_operand" "=x")
- (unspec:V4SI [(match_operand:V4SF 1 "nonimmediate_operand" "xm")] 30))]
+ (unspec:V4SI [(match_operand:V4SF 1 "nonimmediate_operand" "xm")]
+ UNSPEC_FIX))]
"TARGET_SSE2"
"cvttps2dq\t{%1, %0|%0, %1}"
[(set_attr "type" "ssecvt")
(define_insn "cvttpd2dq"
[(set (match_operand:V4SI 0 "register_operand" "=x")
(vec_concat:V4SI
- (unspec:V2SI [(match_operand:V2DF 1 "nonimmediate_operand" "xm")] 30)
+ (unspec:V2SI [(match_operand:V2DF 1 "nonimmediate_operand" "xm")]
+ UNSPEC_FIX)
(const_vector:V2SI [(const_int 0) (const_int 0)])))]
"TARGET_SSE2"
"cvttpd2dq\t{%1, %0|%0, %1}"
(define_insn "cvttpd2pi"
[(set (match_operand:V2SI 0 "register_operand" "=y")
- (unspec:V2SI [(match_operand:V2DF 1 "nonimmediate_operand" "xm")] 30))]
+ (unspec:V2SI [(match_operand:V2DF 1 "nonimmediate_operand" "xm")]
+ UNSPEC_FIX))]
"TARGET_SSE2"
"cvttpd2pi\t{%1, %0|%0, %1}"
[(set_attr "type" "ssecvt")
(define_insn "cvttsd2si"
[(set (match_operand:SI 0 "register_operand" "=r")
(unspec:SI [(vec_select:DF (match_operand:V2DF 1 "register_operand" "xm")
- (parallel [(const_int 0)]))] 30))]
+ (parallel [(const_int 0)]))] UNSPEC_FIX))]
"TARGET_SSE2"
"cvttsd2si\t{%1, %0|%0, %1}"
[(set_attr "type" "ssecvt")
(define_insn "sse2_psadbw"
[(set (match_operand:V2DI 0 "register_operand" "=x")
(unspec:V2DI [(match_operand:V16QI 1 "register_operand" "0")
- (match_operand:V16QI 2 "nonimmediate_operand" "ym")] 61))]
+ (match_operand:V16QI 2 "nonimmediate_operand" "ym")]
+ UNSPEC_PSADBW))]
"TARGET_SSE2"
"psadbw\t{%2, %0|%0, %2}"
[(set_attr "type" "sseiadd")
(define_insn "sse2_pshufd"
[(set (match_operand:V4SI 0 "register_operand" "=x")
(unspec:V4SI [(match_operand:V4SI 1 "register_operand" "0")
- (match_operand:SI 2 "immediate_operand" "i")] 41))]
+ (match_operand:SI 2 "immediate_operand" "i")]
+ UNSPEC_SHUFFLE))]
"TARGET_SSE2"
"pshufd\t{%2, %1, %0|%0, %1, %2}"
[(set_attr "type" "ssecvt")
(define_insn "sse2_pshuflw"
[(set (match_operand:V8HI 0 "register_operand" "=x")
(unspec:V8HI [(match_operand:V8HI 1 "register_operand" "0")
- (match_operand:SI 2 "immediate_operand" "i")] 55))]
+ (match_operand:SI 2 "immediate_operand" "i")]
+ UNSPEC_PSHUFLW))]
"TARGET_SSE2"
"pshuflw\t{%2, %1, %0|%0, %1, %2}"
[(set_attr "type" "ssecvt")
(define_insn "sse2_pshufhw"
[(set (match_operand:V8HI 0 "register_operand" "=x")
(unspec:V8HI [(match_operand:V8HI 1 "register_operand" "0")
- (match_operand:SI 2 "immediate_operand" "i")] 56))]
+ (match_operand:SI 2 "immediate_operand" "i")]
+ UNSPEC_PSHUFHW))]
"TARGET_SSE2"
"pshufhw\t{%2, %1, %0|%0, %1, %2}"
[(set_attr "type" "ssecvt")
(unspec:TI
[(ashift:TI (match_operand:TI 1 "register_operand" "0")
(mult:SI (match_operand:SI 2 "immediate_operand" "i")
- (const_int 8)))] 30))]
+ (const_int 8)))] UNSPEC_NOP))]
"TARGET_SSE2"
"pslldq\t{%2, %0|%0, %2}"
[(set_attr "type" "sseishft")
(unspec:TI
[(lshiftrt:TI (match_operand:TI 1 "register_operand" "0")
(mult:SI (match_operand:SI 2 "immediate_operand" "i")
- (const_int 8)))] 30))]
+ (const_int 8)))] UNSPEC_NOP))]
"TARGET_SSE2"
"pslrdq\t{%2, %0|%0, %2}"
[(set_attr "type" "sseishft")
(define_insn "sse2_movapd"
[(set (match_operand:V2DF 0 "nonimmediate_operand" "=x,m")
- (unspec:V2DF [(match_operand:V2DF 1 "general_operand" "xm,x")] 38))]
+ (unspec:V2DF [(match_operand:V2DF 1 "general_operand" "xm,x")]
+ UNSPEC_MOVA))]
"TARGET_SSE2"
"@
movapd\t{%1, %0|%0, %1}
(define_insn "sse2_movupd"
[(set (match_operand:V2DF 0 "nonimmediate_operand" "=x,m")
- (unspec:V2DF [(match_operand:V2DF 1 "general_operand" "xm,x")] 39))]
+ (unspec:V2DF [(match_operand:V2DF 1 "general_operand" "xm,x")]
+ UNSPEC_MOVU))]
"TARGET_SSE2"
"@
movupd\t{%1, %0|%0, %1}
(define_insn "sse2_movdqa"
[(set (match_operand:TI 0 "nonimmediate_operand" "=x,m")
- (unspec:TI [(match_operand:TI 1 "general_operand" "xm,x")] 38))]
+ (unspec:TI [(match_operand:TI 1 "general_operand" "xm,x")]
+ UNSPEC_MOVA))]
"TARGET_SSE2"
"@
movdqa\t{%1, %0|%0, %1}
(define_insn "sse2_movdqu"
[(set (match_operand:TI 0 "nonimmediate_operand" "=x,m")
- (unspec:TI [(match_operand:TI 1 "general_operand" "xm,x")] 39))]
+ (unspec:TI [(match_operand:TI 1 "general_operand" "xm,x")]
+ UNSPEC_MOVU))]
"TARGET_SSE2"
"@
movdqu\t{%1, %0|%0, %1}
[(set (match_operand:V2DF 0 "register_operand" "=x")
(unspec:V2DF [(match_operand:V2DF 1 "register_operand" "0")
(match_operand:V2DF 2 "nonimmediate_operand" "xm")
- (match_operand:SI 3 "immediate_operand" "i")] 41))]
+ (match_operand:SI 3 "immediate_operand" "i")]
+ UNSPEC_SHUFFLE))]
"TARGET_SSE2"
;; @@@ check operand order for intel/nonintel syntax
"shufpd\t{%3, %2, %0|%0, %2, %3}"
(set_attr "mode" "V2DF")])
(define_insn "sse2_clflush"
- [(unspec_volatile [(match_operand:SI 0 "address_operand" "p")] 57)]
+ [(unspec_volatile [(match_operand:SI 0 "address_operand" "p")]
+ UNSPECV_CLFLUSH)]
"TARGET_SSE2"
"clflush %0"
[(set_attr "type" "sse")
(define_expand "sse2_mfence"
[(set (match_dup 0)
- (unspec:BLK [(match_dup 0)] 59))]
+ (unspec:BLK [(match_dup 0)] UNSPEC_MFENCE))]
"TARGET_SSE2"
{
operands[0] = gen_rtx_MEM (BLKmode, gen_rtx_SCRATCH (Pmode));
(define_insn "*mfence_insn"
[(set (match_operand:BLK 0 "" "")
- (unspec:BLK [(match_dup 0)] 59))]
+ (unspec:BLK [(match_dup 0)] UNSPEC_MFENCE))]
"TARGET_SSE2"
"mfence"
[(set_attr "type" "sse")
(define_expand "sse2_lfence"
[(set (match_dup 0)
- (unspec:BLK [(match_dup 0)] 60))]
+ (unspec:BLK [(match_dup 0)] UNSPEC_LFENCE))]
"TARGET_SSE2"
{
operands[0] = gen_rtx_MEM (BLKmode, gen_rtx_SCRATCH (Pmode));
(define_insn "*lfence_insn"
[(set (match_operand:BLK 0 "" "")
- (unspec:BLK [(match_dup 0)] 60))]
+ (unspec:BLK [(match_dup 0)] UNSPEC_LFENCE))]
"TARGET_SSE2"
"lfence"
[(set_attr "type" "sse")
git://gcc.gnu.org / gcc.git / commitdiff