r3900.h (ASM_OUTPUT_DEF,SUPPORTS_WEAK, [...]): Add.

        * config/mips/r3900.h (ASM_OUTPUT_DEF,SUPPORTS_WEAK,
        ASM_WEAKEN_LABEL): Add.

From-SVN: r19057

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 9e8dbb7cb2d17a13828f7f9d4b6ab6875cf5c580..323b0c865af390eed4dbea7821a6f331aeefd79e 100644 (file)
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,8 @@
+Wed Apr  8 23:13:50 1998  Gavin Koch  <gavin@cygnus.com>
+
+       * config/mips/r3900.h (ASM_OUTPUT_DEF,SUPPORTS_WEAK,
+       ASM_WEAKEN_LABEL): Add.
+
 Wed Apr  8 18:21:30 1998  Richard Henderson  <rth@cygnus.com>
 
        * alpha/crtbegin.asm, alpha/crtend.asm, alpha/t-crtb: New files.

diff --git a/gcc/config/mips/r3900.h b/gcc/config/mips/r3900.h
index 41c2fe2632dc7c54eb978fce8ce1498b764bb587..f1a0d21bfb1bbac63d39153aabd3e533beeb99eb 100644 (file)
--- a/gcc/config/mips/r3900.h
+++ b/gcc/config/mips/r3900.h
@@ -69,3 +69,21 @@ Boston, MA 02111-1307, USA.  */
 %{gstabs+:-g} %{gstabs+0:-g0} %{gstabs+1:-g1} %{gstabs+2:-g2} %{gstabs+3:-g3} \
 %{gcoff:-g} %{gcoff0:-g0} %{gcoff1:-g1} %{gcoff2:-g2} %{gcoff3:-g3}"
 
+/* This is how to equate one symbol to another symbol.  The syntax used is
+   `SYM1=SYM2'.  Note that this is different from the way equates are done
+   with most svr4 assemblers, where the syntax is `.set SYM1,SYM2'.  */
+
+#define ASM_OUTPUT_DEF(FILE,LABEL1,LABEL2)                            \
+ do { fprintf ((FILE), "\t");                                         \
+      assemble_name (FILE, LABEL1);                                   \
+      fprintf (FILE, " = ");                                          \
+      assemble_name (FILE, LABEL2);                                   \
+      fprintf (FILE, "\n");                                           \
+ } while (0)
+
+#define SUPPORTS_WEAK 1
+#define ASM_WEAKEN_LABEL(FILE,NAME)                                   \
+ do { fprintf ((FILE), "\t.weak\t");                                  \
+      assemble_name (FILE, NAME);                                     \
+      fprintf (FILE, "\n");                                           \
+ } while (0)