(eq_attr "type" "imov,test")
(symbol_ref "ix86_attr_length_immediate_default (insn, false)")
(eq_attr "type" "call")
- (if_then_else (match_operand 0 "constant_call_address_operand" "")
+ (if_then_else (match_operand 0 "constant_call_address_operand")
(const_int 4)
(const_int 0))
(eq_attr "type" "callv")
- (if_then_else (match_operand 1 "constant_call_address_operand" "")
+ (if_then_else (match_operand 1 "constant_call_address_operand")
(const_int 4)
(const_int 0))
;; We don't know the size before shorten_branches. Expect
(cond [(eq_attr "type" "str,other,multi,fxch")
(const_int 0)
(and (eq_attr "type" "call")
- (match_operand 0 "constant_call_address_operand" ""))
+ (match_operand 0 "constant_call_address_operand"))
(const_int 0)
(and (eq_attr "type" "callv")
- (match_operand 1 "constant_call_address_operand" ""))
+ (match_operand 1 "constant_call_address_operand"))
(const_int 0)
]
(symbol_ref "ix86_attr_length_address_default (insn)")))
(match_test "x86_extended_reg_mentioned_p (insn)")
(const_int 1)
(and (eq_attr "type" "imovx")
- (match_operand:QI 1 "ext_QIreg_operand" ""))
+ (match_operand:QI 1 "ext_QIreg_operand"))
(const_int 1)
]
(const_int 0)))
(const_int 0)
(and (eq_attr "type" "incdec")
(and (not (match_test "TARGET_64BIT"))
- (ior (match_operand:SI 1 "register_operand" "")
- (match_operand:HI 1 "register_operand" ""))))
+ (ior (match_operand:SI 1 "register_operand")
+ (match_operand:HI 1 "register_operand"))))
(const_int 0)
(and (eq_attr "type" "push")
- (not (match_operand 1 "memory_operand" "")))
+ (not (match_operand 1 "memory_operand")))
(const_int 0)
(and (eq_attr "type" "pop")
- (not (match_operand 0 "memory_operand" "")))
+ (not (match_operand 0 "memory_operand")))
(const_int 0)
(and (eq_attr "type" "imov")
(and (not (eq_attr "mode" "DI"))
- (ior (and (match_operand 0 "register_operand" "")
- (match_operand 1 "immediate_operand" ""))
- (ior (and (match_operand 0 "ax_reg_operand" "")
- (match_operand 1 "memory_displacement_only_operand" ""))
- (and (match_operand 0 "memory_displacement_only_operand" "")
- (match_operand 1 "ax_reg_operand" ""))))))
+ (ior (and (match_operand 0 "register_operand")
+ (match_operand 1 "immediate_operand"))
+ (ior (and (match_operand 0 "ax_reg_operand")
+ (match_operand 1 "memory_displacement_only_operand"))
+ (and (match_operand 0 "memory_displacement_only_operand")
+ (match_operand 1 "ax_reg_operand"))))))
(const_int 0)
(and (eq_attr "type" "call")
- (match_operand 0 "constant_call_address_operand" ""))
+ (match_operand 0 "constant_call_address_operand"))
(const_int 0)
(and (eq_attr "type" "callv")
- (match_operand 1 "constant_call_address_operand" ""))
+ (match_operand 1 "constant_call_address_operand"))
(const_int 0)
(and (eq_attr "type" "alu,alu1,icmp,test")
- (match_operand 0 "ax_reg_operand" ""))
+ (match_operand 0 "ax_reg_operand"))
(symbol_ref "(get_attr_length_immediate (insn) <= (get_attr_mode (insn) != MODE_QI))")
]
(const_int 1)))
(eq_attr "type" "frndint")
(const_string "load")
(eq_attr "type" "push")
- (if_then_else (match_operand 1 "memory_operand" "")
+ (if_then_else (match_operand 1 "memory_operand")
(const_string "both")
(const_string "store"))
(eq_attr "type" "pop")
- (if_then_else (match_operand 0 "memory_operand" "")
+ (if_then_else (match_operand 0 "memory_operand")
(const_string "both")
(const_string "load"))
(eq_attr "type" "setcc")
- (if_then_else (match_operand 0 "memory_operand" "")
+ (if_then_else (match_operand 0 "memory_operand")
(const_string "store")
(const_string "none"))
(eq_attr "type" "icmp,test,ssecmp,ssecomi,mmxcmp,fcmp")
- (if_then_else (ior (match_operand 0 "memory_operand" "")
- (match_operand 1 "memory_operand" ""))
+ (if_then_else (ior (match_operand 0 "memory_operand")
+ (match_operand 1 "memory_operand"))
(const_string "load")
(const_string "none"))
(eq_attr "type" "ibr")
- (if_then_else (match_operand 0 "memory_operand" "")
+ (if_then_else (match_operand 0 "memory_operand")
(const_string "load")
(const_string "none"))
(eq_attr "type" "call")
- (if_then_else (match_operand 0 "constant_call_address_operand" "")
+ (if_then_else (match_operand 0 "constant_call_address_operand")
(const_string "none")
(const_string "load"))
(eq_attr "type" "callv")
- (if_then_else (match_operand 1 "constant_call_address_operand" "")
+ (if_then_else (match_operand 1 "constant_call_address_operand")
(const_string "none")
(const_string "load"))
(and (eq_attr "type" "alu1,negnot,ishift1,sselog1")
- (match_operand 1 "memory_operand" ""))
+ (match_operand 1 "memory_operand"))
(const_string "both")
- (and (match_operand 0 "memory_operand" "")
- (match_operand 1 "memory_operand" ""))
+ (and (match_operand 0 "memory_operand")
+ (match_operand 1 "memory_operand"))
(const_string "both")
- (match_operand 0 "memory_operand" "")
+ (match_operand 0 "memory_operand")
(const_string "store")
- (match_operand 1 "memory_operand" "")
+ (match_operand 1 "memory_operand")
(const_string "load")
(and (eq_attr "type"
"!alu1,negnot,ishift1,
fmov,fcmp,fsgn,
sse,ssemov,ssecmp,ssecomi,ssecvt,ssecvt1,sseicvt,sselog1,
sseiadd1,mmx,mmxmov,mmxcmp,mmxcvt")
- (match_operand 2 "memory_operand" ""))
+ (match_operand 2 "memory_operand"))
(const_string "load")
(and (eq_attr "type" "icmov,ssemuladd,sse4arg")
- (match_operand 3 "memory_operand" ""))
+ (match_operand 3 "memory_operand"))
(const_string "load")
]
(const_string "none")))
(cond [(eq_attr "type" "other,multi")
(const_string "unknown")
(and (eq_attr "type" "icmp,test,imov,alu1,ishift1,rotate1")
- (and (match_operand 0 "memory_displacement_operand" "")
- (match_operand 1 "immediate_operand" "")))
+ (and (match_operand 0 "memory_displacement_operand")
+ (match_operand 1 "immediate_operand")))
(const_string "true")
(and (eq_attr "type" "alu,ishift,ishiftx,rotate,rotatex,imul,idiv")
- (and (match_operand 0 "memory_displacement_operand" "")
- (match_operand 2 "immediate_operand" "")))
+ (and (match_operand 0 "memory_displacement_operand")
+ (match_operand 2 "immediate_operand")))
(const_string "true")
]
(const_string "false")))
(define_expand "cbranch<mode>4"
[(set (reg:CC FLAGS_REG)
- (compare:CC (match_operand:SDWIM 1 "nonimmediate_operand" "")
- (match_operand:SDWIM 2 "<general_operand>" "")))
+ (compare:CC (match_operand:SDWIM 1 "nonimmediate_operand")
+ (match_operand:SDWIM 2 "<general_operand>")))
(set (pc) (if_then_else
(match_operator 0 "ordered_comparison_operator"
[(reg:CC FLAGS_REG) (const_int 0)])
- (label_ref (match_operand 3 "" ""))
+ (label_ref (match_operand 3))
(pc)))]
""
{
(define_expand "cstore<mode>4"
[(set (reg:CC FLAGS_REG)
- (compare:CC (match_operand:SWIM 2 "nonimmediate_operand" "")
- (match_operand:SWIM 3 "<general_operand>" "")))
- (set (match_operand:QI 0 "register_operand" "")
+ (compare:CC (match_operand:SWIM 2 "nonimmediate_operand")
+ (match_operand:SWIM 3 "<general_operand>")))
+ (set (match_operand:QI 0 "register_operand")
(match_operator 1 "ordered_comparison_operator"
[(reg:CC FLAGS_REG) (const_int 0)]))]
""
(define_expand "cmp<mode>_1"
[(set (reg:CC FLAGS_REG)
- (compare:CC (match_operand:SWI48 0 "nonimmediate_operand" "")
- (match_operand:SWI48 1 "<general_operand>" "")))])
+ (compare:CC (match_operand:SWI48 0 "nonimmediate_operand")
+ (match_operand:SWI48 1 "<general_operand>")))])
(define_insn "*cmp<mode>_ccno_1"
[(set (reg FLAGS_REG)
(compare (match_operand:SWI 0 "nonimmediate_operand" "<r>,?m<r>")
- (match_operand:SWI 1 "const0_operand" "")))]
+ (match_operand:SWI 1 "const0_operand")))]
"ix86_match_ccmode (insn, CCNOmode)"
"@
test{<imodesuffix>}\t%0, %0
(match_operand 0 "ext_register_operand" "Q")
(const_int 8)
(const_int 8)) 0)
- (match_operand:QI 1 "const0_operand" "")))]
+ (match_operand:QI 1 "const0_operand")))]
"ix86_match_ccmode (insn, CCNOmode)"
"test{b}\t%h0, %h0"
[(set_attr "type" "test")
(compare:CC
(subreg:QI
(zero_extract:SI
- (match_operand 0 "ext_register_operand" "")
+ (match_operand 0 "ext_register_operand")
(const_int 8)
(const_int 8)) 0)
- (match_operand:QI 1 "immediate_operand" "")))])
+ (match_operand:QI 1 "immediate_operand")))])
(define_insn "*cmpqi_ext_3_insn"
[(set (reg FLAGS_REG)
(define_expand "cbranchxf4"
[(set (reg:CC FLAGS_REG)
- (compare:CC (match_operand:XF 1 "nonmemory_operand" "")
- (match_operand:XF 2 "nonmemory_operand" "")))
+ (compare:CC (match_operand:XF 1 "nonmemory_operand")
+ (match_operand:XF 2 "nonmemory_operand")))
(set (pc) (if_then_else
(match_operator 0 "ix86_fp_comparison_operator"
[(reg:CC FLAGS_REG)
(const_int 0)])
- (label_ref (match_operand 3 "" ""))
+ (label_ref (match_operand 3))
(pc)))]
"TARGET_80387"
{
(define_expand "cstorexf4"
[(set (reg:CC FLAGS_REG)
- (compare:CC (match_operand:XF 2 "nonmemory_operand" "")
- (match_operand:XF 3 "nonmemory_operand" "")))
- (set (match_operand:QI 0 "register_operand" "")
+ (compare:CC (match_operand:XF 2 "nonmemory_operand")
+ (match_operand:XF 3 "nonmemory_operand")))
+ (set (match_operand:QI 0 "register_operand")
(match_operator 1 "ix86_fp_comparison_operator"
[(reg:CC FLAGS_REG)
(const_int 0)]))]
(define_expand "cbranch<mode>4"
[(set (reg:CC FLAGS_REG)
- (compare:CC (match_operand:MODEF 1 "cmp_fp_expander_operand" "")
- (match_operand:MODEF 2 "cmp_fp_expander_operand" "")))
+ (compare:CC (match_operand:MODEF 1 "cmp_fp_expander_operand")
+ (match_operand:MODEF 2 "cmp_fp_expander_operand")))
(set (pc) (if_then_else
(match_operator 0 "ix86_fp_comparison_operator"
[(reg:CC FLAGS_REG)
(const_int 0)])
- (label_ref (match_operand 3 "" ""))
+ (label_ref (match_operand 3))
(pc)))]
"TARGET_80387 || (SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH)"
{
(define_expand "cstore<mode>4"
[(set (reg:CC FLAGS_REG)
- (compare:CC (match_operand:MODEF 2 "cmp_fp_expander_operand" "")
- (match_operand:MODEF 3 "cmp_fp_expander_operand" "")))
- (set (match_operand:QI 0 "register_operand" "")
+ (compare:CC (match_operand:MODEF 2 "cmp_fp_expander_operand")
+ (match_operand:MODEF 3 "cmp_fp_expander_operand")))
+ (set (match_operand:QI 0 "register_operand")
(match_operator 1 "ix86_fp_comparison_operator"
[(reg:CC FLAGS_REG)
(const_int 0)]))]
(define_expand "cbranchcc4"
[(set (pc) (if_then_else
(match_operator 0 "comparison_operator"
- [(match_operand 1 "flags_reg_operand" "")
- (match_operand 2 "const0_operand" "")])
- (label_ref (match_operand 3 "" ""))
+ [(match_operand 1 "flags_reg_operand")
+ (match_operand 2 "const0_operand")])
+ (label_ref (match_operand 3))
(pc)))]
""
{
})
(define_expand "cstorecc4"
- [(set (match_operand:QI 0 "register_operand" "")
+ [(set (match_operand:QI 0 "register_operand")
(match_operator 1 "comparison_operator"
- [(match_operand 2 "flags_reg_operand" "")
- (match_operand 3 "const0_operand" "")]))]
+ [(match_operand 2 "flags_reg_operand")
+ (match_operand 3 "const0_operand")]))]
""
{
ix86_expand_setcc (operands[0], GET_CODE (operands[1]),
(unspec:HI
[(compare:CCFP
(match_operand 1 "register_operand" "f")
- (match_operand 2 "const0_operand" ""))]
+ (match_operand 2 "const0_operand"))]
UNSPEC_FNSTSW))]
"X87_FLOAT_MODE_P (GET_MODE (operands[1]))
&& GET_MODE (operands[1]) == GET_MODE (operands[2])"
[(set_attr "type" "multi")
(set_attr "unit" "i387")
(set (attr "mode")
- (cond [(match_operand:SF 1 "" "")
+ (cond [(match_operand:SF 1)
(const_string "SF")
- (match_operand:DF 1 "" "")
+ (match_operand:DF 1)
(const_string "DF")
]
(const_string "XF")))])
[(set (reg:CCFP FLAGS_REG)
(compare:CCFP
(match_operand 1 "register_operand" "f")
- (match_operand 2 "const0_operand" "")))
+ (match_operand 2 "const0_operand")))
(clobber (match_operand:HI 0 "register_operand" "=a"))]
"X87_FLOAT_MODE_P (GET_MODE (operands[1]))
&& TARGET_SAHF && !TARGET_CMOVE
[(set_attr "type" "multi")
(set_attr "unit" "i387")
(set (attr "mode")
- (cond [(match_operand:SF 1 "" "")
+ (cond [(match_operand:SF 1)
(const_string "SF")
- (match_operand:DF 1 "" "")
+ (match_operand:DF 1)
(const_string "DF")
]
(const_string "XF")))])
[(set_attr "type" "multi")
(set_attr "unit" "i387")
(set (attr "mode")
- (cond [(match_operand:SF 1 "" "")
+ (cond [(match_operand:SF 1)
(const_string "SF")
- (match_operand:DF 1 "" "")
+ (match_operand:DF 1)
(const_string "DF")
]
(const_string "XF")))])
[(set_attr "type" "multi")
(set_attr "unit" "i387")
(set (attr "mode")
- (cond [(match_operand:SF 1 "" "")
+ (cond [(match_operand:SF 1)
(const_string "SF")
- (match_operand:DF 1 "" "")
+ (match_operand:DF 1)
(const_string "DF")
]
(const_string "XF")))])
[(set_attr "type" "fcmp,ssecomi")
(set_attr "prefix" "orig,maybe_vex")
(set (attr "mode")
- (if_then_else (match_operand:SF 1 "" "")
+ (if_then_else (match_operand:SF 1)
(const_string "SF")
(const_string "DF")))
(set (attr "prefix_rep")
[(set_attr "type" "ssecomi")
(set_attr "prefix" "maybe_vex")
(set (attr "mode")
- (if_then_else (match_operand:SF 1 "" "")
+ (if_then_else (match_operand:SF 1)
(const_string "SF")
(const_string "DF")))
(set_attr "prefix_rep" "0")
"* return output_fp_compare (insn, operands, true, false);"
[(set_attr "type" "fcmp")
(set (attr "mode")
- (cond [(match_operand:SF 1 "" "")
+ (cond [(match_operand:SF 1)
(const_string "SF")
- (match_operand:DF 1 "" "")
+ (match_operand:DF 1)
(const_string "DF")
]
(const_string "XF")))
[(set_attr "type" "fcmp,ssecomi")
(set_attr "prefix" "orig,maybe_vex")
(set (attr "mode")
- (if_then_else (match_operand:SF 1 "" "")
+ (if_then_else (match_operand:SF 1)
(const_string "SF")
(const_string "DF")))
(set (attr "prefix_rep")
[(set_attr "type" "ssecomi")
(set_attr "prefix" "maybe_vex")
(set (attr "mode")
- (if_then_else (match_operand:SF 1 "" "")
+ (if_then_else (match_operand:SF 1)
(const_string "SF")
(const_string "DF")))
(set_attr "prefix_rep" "0")
"* return output_fp_compare (insn, operands, true, true);"
[(set_attr "type" "fcmp")
(set (attr "mode")
- (cond [(match_operand:SF 1 "" "")
+ (cond [(match_operand:SF 1)
(const_string "SF")
- (match_operand:DF 1 "" "")
+ (match_operand:DF 1)
(const_string "DF")
]
(const_string "XF")))
(set_attr "mode" "<MODE>")])
(define_split
- [(set (match_operand:TI 0 "push_operand" "")
- (match_operand:TI 1 "general_operand" ""))]
+ [(set (match_operand:TI 0 "push_operand")
+ (match_operand:TI 1 "general_operand"))]
"TARGET_64BIT && reload_completed
&& !SSE_REG_P (operands[1])"
[(const_int 0)]
;; upper part by 32bit move.
(define_peephole2
[(match_scratch:DI 2 "r")
- (set (match_operand:DI 0 "push_operand" "")
- (match_operand:DI 1 "immediate_operand" ""))]
+ (set (match_operand:DI 0 "push_operand")
+ (match_operand:DI 1 "immediate_operand"))]
"TARGET_64BIT && !symbolic_operand (operands[1], DImode)
&& !x86_64_immediate_operand (operands[1], DImode)"
[(set (match_dup 2) (match_dup 1))
;; peephole2 pass is not run.
;; "&& 1" is needed to keep it from matching the previous pattern.
(define_peephole2
- [(set (match_operand:DI 0 "push_operand" "")
- (match_operand:DI 1 "immediate_operand" ""))]
+ [(set (match_operand:DI 0 "push_operand")
+ (match_operand:DI 1 "immediate_operand"))]
"TARGET_64BIT && !symbolic_operand (operands[1], DImode)
&& !x86_64_immediate_operand (operands[1], DImode) && 1"
[(set (match_dup 0) (match_dup 1))
})
(define_split
- [(set (match_operand:DI 0 "push_operand" "")
- (match_operand:DI 1 "immediate_operand" ""))]
+ [(set (match_operand:DI 0 "push_operand")
+ (match_operand:DI 1 "immediate_operand"))]
"TARGET_64BIT && ((optimize > 0 && flag_peephole2)
? epilogue_completed : reload_completed)
&& !symbolic_operand (operands[1], DImode)
})
(define_split
- [(set (match_operand:DI 0 "push_operand" "")
- (match_operand:DI 1 "general_operand" ""))]
+ [(set (match_operand:DI 0 "push_operand")
+ (match_operand:DI 1 "general_operand"))]
"!TARGET_64BIT && reload_completed
&& !(MMX_REG_P (operands[1]) || SSE_REG_P (operands[1]))"
[(const_int 0)]
;; Move instructions.
(define_expand "movoi"
- [(set (match_operand:OI 0 "nonimmediate_operand" "")
- (match_operand:OI 1 "general_operand" ""))]
+ [(set (match_operand:OI 0 "nonimmediate_operand")
+ (match_operand:OI 1 "general_operand"))]
"TARGET_AVX"
"ix86_expand_move (OImode, operands); DONE;")
(define_expand "movti"
- [(set (match_operand:TI 0 "nonimmediate_operand" "")
- (match_operand:TI 1 "nonimmediate_operand" ""))]
+ [(set (match_operand:TI 0 "nonimmediate_operand")
+ (match_operand:TI 1 "nonimmediate_operand"))]
"TARGET_64BIT || TARGET_SSE"
{
if (TARGET_64BIT)
;; 32-bit targets when SSE is present, but doesn't seem to be harmful
;; to have around all the time.
(define_expand "movcdi"
- [(set (match_operand:CDI 0 "nonimmediate_operand" "")
- (match_operand:CDI 1 "general_operand" ""))]
+ [(set (match_operand:CDI 0 "nonimmediate_operand")
+ (match_operand:CDI 1 "general_operand"))]
""
{
if (push_operand (operands[0], CDImode))
})
(define_expand "mov<mode>"
- [(set (match_operand:SWI1248x 0 "nonimmediate_operand" "")
- (match_operand:SWI1248x 1 "general_operand" ""))]
+ [(set (match_operand:SWI1248x 0 "nonimmediate_operand")
+ (match_operand:SWI1248x 1 "general_operand"))]
""
"ix86_expand_move (<MODE>mode, operands); DONE;")
(define_insn "*mov<mode>_xor"
[(set (match_operand:SWI48 0 "register_operand" "=r")
- (match_operand:SWI48 1 "const0_operand" ""))
+ (match_operand:SWI48 1 "const0_operand"))
(clobber (reg:CC FLAGS_REG))]
"reload_completed"
"xor{l}\t%k0, %k0"
(define_insn "*mov<mode>_or"
[(set (match_operand:SWI48 0 "register_operand" "=r")
- (match_operand:SWI48 1 "const_int_operand" ""))
+ (match_operand:SWI48 1 "const_int_operand"))
(clobber (reg:CC FLAGS_REG))]
"reload_completed
&& operands[1] == constm1_rtx"
(const_string "DI")))])
(define_split
- [(set (match_operand:TI 0 "nonimmediate_operand" "")
- (match_operand:TI 1 "general_operand" ""))]
+ [(set (match_operand:TI 0 "nonimmediate_operand")
+ (match_operand:TI 1 "general_operand"))]
"reload_completed
&& !SSE_REG_P (operands[0]) && !SSE_REG_P (operands[1])"
[(const_int 0)]
(const_string "ssemov")
(eq_attr "alternative" "16,17")
(const_string "ssecvt")
- (match_operand 1 "pic_32bit_operand" "")
+ (match_operand 1 "pic_32bit_operand")
(const_string "lea")
]
(const_string "imov")))
;; fails, move by 32bit parts.
(define_peephole2
[(match_scratch:DI 2 "r")
- (set (match_operand:DI 0 "memory_operand" "")
- (match_operand:DI 1 "immediate_operand" ""))]
+ (set (match_operand:DI 0 "memory_operand")
+ (match_operand:DI 1 "immediate_operand"))]
"TARGET_64BIT && !symbolic_operand (operands[1], DImode)
&& !x86_64_immediate_operand (operands[1], DImode)"
[(set (match_dup 2) (match_dup 1))
;; peephole2 pass is not run.
;; "&& 1" is needed to keep it from matching the previous pattern.
(define_peephole2
- [(set (match_operand:DI 0 "memory_operand" "")
- (match_operand:DI 1 "immediate_operand" ""))]
+ [(set (match_operand:DI 0 "memory_operand")
+ (match_operand:DI 1 "immediate_operand"))]
"TARGET_64BIT && !symbolic_operand (operands[1], DImode)
&& !x86_64_immediate_operand (operands[1], DImode) && 1"
[(set (match_dup 2) (match_dup 3))
"split_double_mode (DImode, &operands[0], 2, &operands[2], &operands[4]);")
(define_split
- [(set (match_operand:DI 0 "memory_operand" "")
- (match_operand:DI 1 "immediate_operand" ""))]
+ [(set (match_operand:DI 0 "memory_operand")
+ (match_operand:DI 1 "immediate_operand"))]
"TARGET_64BIT && ((optimize > 0 && flag_peephole2)
? epilogue_completed : reload_completed)
&& !symbolic_operand (operands[1], DImode)
(set_attr "mode" "DI,DI,DI,DI,DI,TI,DI,TI,DI,V4SF,V2SF,V4SF,V2SF,DI,DI")])
(define_split
- [(set (match_operand:DI 0 "nonimmediate_operand" "")
- (match_operand:DI 1 "general_operand" ""))]
+ [(set (match_operand:DI 0 "nonimmediate_operand")
+ (match_operand:DI 1 "general_operand"))]
"!TARGET_64BIT && reload_completed
&& !(MMX_REG_P (operands[0]) || SSE_REG_P (operands[0]))
&& !(MMX_REG_P (operands[1]) || SSE_REG_P (operands[1]))"
(const_string "sselog1")
(eq_attr "alternative" "7,8,9,10,11")
(const_string "ssemov")
- (match_operand 1 "pic_32bit_operand" "")
+ (match_operand 1 "pic_32bit_operand")
(const_string "lea")
]
(const_string "imov")))
(not (match_test "TARGET_HIMODE_MATH"))))
(const_string "imov")
(and (eq_attr "alternative" "1,2")
- (match_operand:HI 1 "aligned_operand" ""))
+ (match_operand:HI 1 "aligned_operand"))
(const_string "imov")
(and (match_test "TARGET_MOVX")
(eq_attr "alternative" "0,2"))
(cond [(eq_attr "type" "imovx")
(const_string "SI")
(and (eq_attr "alternative" "1,2")
- (match_operand:HI 1 "aligned_operand" ""))
+ (match_operand:HI 1 "aligned_operand"))
(const_string "SI")
(and (eq_attr "alternative" "0")
(ior (not (match_test "TARGET_PARTIAL_REG_STALL"))
}
[(set (attr "type")
(cond [(and (eq_attr "alternative" "5")
- (not (match_operand:QI 1 "aligned_operand" "")))
+ (not (match_operand:QI 1 "aligned_operand")))
(const_string "imovx")
(match_test "optimize_function_for_size_p (cfun)")
(const_string "imov")
(set_attr "athlon_decode" "vector")])
(define_expand "movstrict<mode>"
- [(set (strict_low_part (match_operand:SWI12 0 "nonimmediate_operand" ""))
- (match_operand:SWI12 1 "general_operand" ""))]
+ [(set (strict_low_part (match_operand:SWI12 0 "nonimmediate_operand"))
+ (match_operand:SWI12 1 "general_operand"))]
""
{
if (TARGET_PARTIAL_REG_STALL && optimize_function_for_speed_p (cfun))
(define_insn "*movstrict<mode>_xor"
[(set (strict_low_part (match_operand:SWI12 0 "register_operand" "+<r>"))
- (match_operand:SWI12 1 "const0_operand" ""))
+ (match_operand:SWI12 1 "const0_operand"))
(clobber (reg:CC FLAGS_REG))]
"reload_completed"
"xor{<imodesuffix>}\t%0, %0"
}
}
[(set (attr "type")
- (if_then_else (ior (not (match_operand:QI 0 "QIreg_operand" ""))
+ (if_then_else (ior (not (match_operand:QI 0 "QIreg_operand"))
(match_test "TARGET_MOVX"))
(const_string "imovx")
(const_string "imov")))
}
}
[(set (attr "type")
- (if_then_else (and (match_operand:QI 0 "register_operand" "")
- (ior (not (match_operand:QI 0 "QIreg_operand" ""))
+ (if_then_else (and (match_operand:QI 0 "register_operand")
+ (ior (not (match_operand:QI 0 "QIreg_operand"))
(match_test "TARGET_MOVX")))
(const_string "imovx")
(const_string "imov")))
}
}
[(set (attr "type")
- (if_then_else (ior (not (match_operand:QI 0 "QIreg_operand" ""))
+ (if_then_else (ior (not (match_operand:QI 0 "QIreg_operand"))
(match_test "TARGET_MOVX"))
(const_string "imovx")
(const_string "imov")))
}
}
[(set (attr "type")
- (if_then_else (and (match_operand:QI 0 "register_operand" "")
- (ior (not (match_operand:QI 0 "QIreg_operand" ""))
+ (if_then_else (and (match_operand:QI 0 "register_operand")
+ (ior (not (match_operand:QI 0 "QIreg_operand"))
(match_test "TARGET_MOVX")))
(const_string "imovx")
(const_string "imov")))
(const_string "QI")))])
(define_expand "mov<mode>_insv_1"
- [(set (zero_extract:SWI48 (match_operand 0 "ext_register_operand" "")
+ [(set (zero_extract:SWI48 (match_operand 0 "ext_register_operand")
(const_int 8)
(const_int 8))
- (match_operand:SWI48 1 "nonmemory_operand" ""))])
+ (match_operand:SWI48 1 "nonmemory_operand"))])
(define_insn "*mov<mode>_insv_1_rex64"
[(set (zero_extract:SWI48x (match_operand 0 "ext_register_operand" "+Q")
;; %%% Kill this when call knows how to work this out.
(define_split
- [(set (match_operand:TF 0 "push_operand" "")
- (match_operand:TF 1 "sse_reg_operand" ""))]
+ [(set (match_operand:TF 0 "push_operand")
+ (match_operand:TF 1 "sse_reg_operand"))]
"TARGET_SSE2 && reload_completed"
[(set (reg:P SP_REG) (plus:P (reg:P SP_REG) (const_int -16)))
(set (mem:TF (reg:P SP_REG)) (match_dup 1))])
;; %%% Kill this when call knows how to work this out.
(define_split
- [(set (match_operand:XF 0 "push_operand" "")
- (match_operand:XF 1 "fp_register_operand" ""))]
+ [(set (match_operand:XF 0 "push_operand")
+ (match_operand:XF 1 "fp_register_operand"))]
"reload_completed"
[(set (reg:P SP_REG) (plus:P (reg:P SP_REG) (match_dup 2)))
(set (mem:XF (reg:P SP_REG)) (match_dup 1))]
;; %%% Kill this when call knows how to work this out.
(define_split
- [(set (match_operand:DF 0 "push_operand" "")
- (match_operand:DF 1 "any_fp_register_operand" ""))]
+ [(set (match_operand:DF 0 "push_operand")
+ (match_operand:DF 1 "any_fp_register_operand"))]
"reload_completed"
[(set (reg:P SP_REG) (plus:P (reg:P SP_REG) (const_int -8)))
(set (mem:DF (reg:P SP_REG)) (match_dup 1))])
;; %%% Kill this when call knows how to work this out.
(define_split
- [(set (match_operand:SF 0 "push_operand" "")
- (match_operand:SF 1 "any_fp_register_operand" ""))]
+ [(set (match_operand:SF 0 "push_operand")
+ (match_operand:SF 1 "any_fp_register_operand"))]
"reload_completed"
[(set (reg:P SP_REG) (plus:P (reg:P SP_REG) (match_dup 2)))
(set (mem:SF (reg:P SP_REG)) (match_dup 1))]
"operands[2] = GEN_INT (-GET_MODE_SIZE (<P:MODE>mode));")
(define_split
- [(set (match_operand:SF 0 "push_operand" "")
- (match_operand:SF 1 "memory_operand" ""))]
+ [(set (match_operand:SF 0 "push_operand")
+ (match_operand:SF 1 "memory_operand"))]
"reload_completed
&& (operands[2] = find_constant_src (insn))"
[(set (match_dup 0) (match_dup 2))])
(define_split
- [(set (match_operand 0 "push_operand" "")
- (match_operand 1 "general_operand" ""))]
+ [(set (match_operand 0 "push_operand")
+ (match_operand 1 "general_operand"))]
"reload_completed
&& (GET_MODE (operands[0]) == TFmode
|| GET_MODE (operands[0]) == XFmode
;; Floating point move instructions.
(define_expand "movtf"
- [(set (match_operand:TF 0 "nonimmediate_operand" "")
- (match_operand:TF 1 "nonimmediate_operand" ""))]
+ [(set (match_operand:TF 0 "nonimmediate_operand")
+ (match_operand:TF 1 "nonimmediate_operand"))]
"TARGET_SSE2"
{
ix86_expand_move (TFmode, operands);
})
(define_expand "mov<mode>"
- [(set (match_operand:X87MODEF 0 "nonimmediate_operand" "")
- (match_operand:X87MODEF 1 "general_operand" ""))]
+ [(set (match_operand:X87MODEF 0 "nonimmediate_operand")
+ (match_operand:X87MODEF 1 "general_operand"))]
""
"ix86_expand_move (<MODE>mode, operands); DONE;")
(const_string "SF")))])
(define_split
- [(set (match_operand 0 "any_fp_register_operand" "")
- (match_operand 1 "memory_operand" ""))]
+ [(set (match_operand 0 "any_fp_register_operand")
+ (match_operand 1 "memory_operand"))]
"reload_completed
&& (GET_MODE (operands[0]) == TFmode
|| GET_MODE (operands[0]) == XFmode
})
(define_split
- [(set (match_operand 0 "any_fp_register_operand" "")
- (float_extend (match_operand 1 "memory_operand" "")))]
+ [(set (match_operand 0 "any_fp_register_operand")
+ (float_extend (match_operand 1 "memory_operand")))]
"reload_completed
&& (GET_MODE (operands[0]) == TFmode
|| GET_MODE (operands[0]) == XFmode
;; Split the load of -0.0 or -1.0 into fldz;fchs or fld1;fchs sequence
(define_split
- [(set (match_operand:X87MODEF 0 "fp_register_operand" "")
- (match_operand:X87MODEF 1 "immediate_operand" ""))]
+ [(set (match_operand:X87MODEF 0 "fp_register_operand")
+ (match_operand:X87MODEF 1 "immediate_operand"))]
"reload_completed
&& (standard_80387_constant_p (operands[1]) == 8
|| standard_80387_constant_p (operands[1]) == 9)"
})
(define_split
- [(set (match_operand 0 "nonimmediate_operand" "")
- (match_operand 1 "general_operand" ""))]
+ [(set (match_operand 0 "nonimmediate_operand")
+ (match_operand 1 "general_operand"))]
"reload_completed
&& (GET_MODE (operands[0]) == TFmode
|| GET_MODE (operands[0]) == XFmode
;; Zero extension instructions
(define_expand "zero_extendsidi2"
- [(set (match_operand:DI 0 "nonimmediate_operand" "")
- (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "")))])
+ [(set (match_operand:DI 0 "nonimmediate_operand")
+ (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand")))])
(define_insn "*zero_extendsidi2_rex64"
[(set (match_operand:DI 0 "nonimmediate_operand"
(set_attr "mode" "SI,SI,SI,DI,DI,TI,TI")])
(define_split
- [(set (match_operand:DI 0 "memory_operand" "")
- (zero_extend:DI (match_operand:SI 1 "memory_operand" "")))]
+ [(set (match_operand:DI 0 "memory_operand")
+ (zero_extend:DI (match_operand:SI 1 "memory_operand")))]
"reload_completed"
[(set (match_dup 4) (const_int 0))]
"split_double_mode (DImode, &operands[0], 1, &operands[3], &operands[4]);")
(define_split
- [(set (match_operand:DI 0 "register_operand" "")
- (zero_extend:DI (match_operand:SI 1 "register_operand" "")))]
+ [(set (match_operand:DI 0 "register_operand")
+ (zero_extend:DI (match_operand:SI 1 "register_operand")))]
"!TARGET_64BIT && reload_completed
&& !(MMX_REG_P (operands[0]) || SSE_REG_P (operands[0]))
&& true_regnum (operands[0]) == true_regnum (operands[1])"
"split_double_mode (DImode, &operands[0], 1, &operands[3], &operands[4]);")
(define_split
- [(set (match_operand:DI 0 "nonimmediate_operand" "")
- (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "")))]
+ [(set (match_operand:DI 0 "nonimmediate_operand")
+ (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand")))]
"!TARGET_64BIT && reload_completed
&& !(MEM_P (operands[0]) && MEM_P (operands[1]))
&& !(MMX_REG_P (operands[0]) || SSE_REG_P (operands[0]))"
(set_attr "mode" "SI")])
(define_expand "zero_extend<mode>si2"
- [(set (match_operand:SI 0 "register_operand" "")
- (zero_extend:SI (match_operand:SWI12 1 "nonimmediate_operand" "")))]
+ [(set (match_operand:SI 0 "register_operand")
+ (zero_extend:SI (match_operand:SWI12 1 "nonimmediate_operand")))]
""
{
if (TARGET_ZERO_EXTEND_WITH_AND && optimize_function_for_speed_p (cfun))
(set_attr "mode" "SI")])
(define_expand "zero_extendqihi2"
- [(set (match_operand:HI 0 "register_operand" "")
- (zero_extend:HI (match_operand:QI 1 "nonimmediate_operand" "")))]
+ [(set (match_operand:HI 0 "register_operand")
+ (zero_extend:HI (match_operand:QI 1 "nonimmediate_operand")))]
""
{
if (TARGET_ZERO_EXTEND_WITH_AND && optimize_function_for_speed_p (cfun))
;; Sign extension instructions
(define_expand "extendsidi2"
- [(set (match_operand:DI 0 "register_operand" "")
- (sign_extend:DI (match_operand:SI 1 "register_operand" "")))]
+ [(set (match_operand:DI 0 "register_operand")
+ (sign_extend:DI (match_operand:SI 1 "register_operand")))]
""
{
if (!TARGET_64BIT)
;; Extend to memory case when source register does die.
(define_split
- [(set (match_operand:DI 0 "memory_operand" "")
- (sign_extend:DI (match_operand:SI 1 "register_operand" "")))
+ [(set (match_operand:DI 0 "memory_operand")
+ (sign_extend:DI (match_operand:SI 1 "register_operand")))
(clobber (reg:CC FLAGS_REG))
- (clobber (match_operand:SI 2 "register_operand" ""))]
+ (clobber (match_operand:SI 2 "register_operand"))]
"(reload_completed
&& dead_or_set_p (insn, operands[1])
&& !reg_mentioned_p (operands[1], operands[0]))"
;; Extend to memory case when source register does not die.
(define_split
- [(set (match_operand:DI 0 "memory_operand" "")
- (sign_extend:DI (match_operand:SI 1 "register_operand" "")))
+ [(set (match_operand:DI 0 "memory_operand")
+ (sign_extend:DI (match_operand:SI 1 "register_operand")))
(clobber (reg:CC FLAGS_REG))
- (clobber (match_operand:SI 2 "register_operand" ""))]
+ (clobber (match_operand:SI 2 "register_operand"))]
"reload_completed"
[(const_int 0)]
{
;; Extend to register case. Optimize case where source and destination
;; registers match and cases where we can use cltd.
(define_split
- [(set (match_operand:DI 0 "register_operand" "")
- (sign_extend:DI (match_operand:SI 1 "register_operand" "")))
+ [(set (match_operand:DI 0 "register_operand")
+ (sign_extend:DI (match_operand:SI 1 "register_operand")))
(clobber (reg:CC FLAGS_REG))
- (clobber (match_scratch:SI 2 ""))]
+ (clobber (match_scratch:SI 2))]
"reload_completed"
[(const_int 0)]
{
;; %%% Kill these when call knows how to work out a DFmode push earlier.
(define_split
- [(set (match_operand:DF 0 "push_operand" "")
- (float_extend:DF (match_operand:SF 1 "fp_register_operand" "")))]
+ [(set (match_operand:DF 0 "push_operand")
+ (float_extend:DF (match_operand:SF 1 "fp_register_operand")))]
"reload_completed"
[(set (reg:P SP_REG) (plus:P (reg:P SP_REG) (const_int -8)))
(set (mem:DF (reg:P SP_REG)) (float_extend:DF (match_dup 1)))])
(define_split
- [(set (match_operand:XF 0 "push_operand" "")
- (float_extend:XF (match_operand:MODEF 1 "fp_register_operand" "")))]
+ [(set (match_operand:XF 0 "push_operand")
+ (float_extend:XF (match_operand:MODEF 1 "fp_register_operand")))]
"reload_completed"
[(set (reg:P SP_REG) (plus:P (reg:P SP_REG) (match_dup 2)))
(set (mem:XF (reg:P SP_REG)) (float_extend:XF (match_dup 1)))]
"operands[2] = GEN_INT (-GET_MODE_SIZE (XFmode));")
(define_expand "extendsfdf2"
- [(set (match_operand:DF 0 "nonimmediate_operand" "")
- (float_extend:DF (match_operand:SF 1 "general_operand" "")))]
+ [(set (match_operand:DF 0 "nonimmediate_operand")
+ (float_extend:DF (match_operand:SF 1 "general_operand")))]
"TARGET_80387 || (TARGET_SSE2 && TARGET_SSE_MATH)"
{
/* ??? Needed for compress_float_constant since all fp constants
that might lead to ICE on 32bit target. The sequence unlikely combine
anyway. */
(define_split
- [(set (match_operand:DF 0 "register_operand" "")
+ [(set (match_operand:DF 0 "register_operand")
(float_extend:DF
- (match_operand:SF 1 "nonimmediate_operand" "")))]
+ (match_operand:SF 1 "nonimmediate_operand")))]
"TARGET_USE_VECTOR_FP_CONVERTS
&& optimize_insn_for_speed_p ()
&& reload_completed && SSE_REG_P (operands[0])"
(set_attr "mode" "SF,XF")])
(define_expand "extend<mode>xf2"
- [(set (match_operand:XF 0 "nonimmediate_operand" "")
- (float_extend:XF (match_operand:MODEF 1 "general_operand" "")))]
+ [(set (match_operand:XF 0 "nonimmediate_operand")
+ (float_extend:XF (match_operand:MODEF 1 "general_operand")))]
"TARGET_80387"
{
/* ??? Needed for compress_float_constant since all fp constants
;; Conversion from DFmode to SFmode.
(define_expand "truncdfsf2"
- [(set (match_operand:SF 0 "nonimmediate_operand" "")
+ [(set (match_operand:SF 0 "nonimmediate_operand")
(float_truncate:SF
- (match_operand:DF 1 "nonimmediate_operand" "")))]
+ (match_operand:DF 1 "nonimmediate_operand")))]
"TARGET_80387 || (TARGET_SSE2 && TARGET_SSE_MATH)"
{
if (TARGET_SSE2 && TARGET_SSE_MATH && !TARGET_MIX_SSE_I387)
that might lead to ICE on 32bit target. The sequence unlikely combine
anyway. */
(define_split
- [(set (match_operand:SF 0 "register_operand" "")
+ [(set (match_operand:SF 0 "register_operand")
(float_truncate:SF
- (match_operand:DF 1 "nonimmediate_operand" "")))]
+ (match_operand:DF 1 "nonimmediate_operand")))]
"TARGET_USE_VECTOR_FP_CONVERTS
&& optimize_insn_for_speed_p ()
&& reload_completed && SSE_REG_P (operands[0])"
})
(define_expand "truncdfsf2_with_temp"
- [(parallel [(set (match_operand:SF 0 "" "")
- (float_truncate:SF (match_operand:DF 1 "" "")))
- (clobber (match_operand:SF 2 "" ""))])])
+ [(parallel [(set (match_operand:SF 0)
+ (float_truncate:SF (match_operand:DF 1)))
+ (clobber (match_operand:SF 2))])])
(define_insn "*truncdfsf_fast_mixed"
[(set (match_operand:SF 0 "nonimmediate_operand" "=fm,x")
(set_attr "mode" "SF")])
(define_split
- [(set (match_operand:SF 0 "register_operand" "")
+ [(set (match_operand:SF 0 "register_operand")
(float_truncate:SF
- (match_operand:DF 1 "fp_register_operand" "")))
- (clobber (match_operand 2 "" ""))]
+ (match_operand:DF 1 "fp_register_operand")))
+ (clobber (match_operand 2))]
"reload_completed"
[(set (match_dup 2) (match_dup 1))
(set (match_dup 0) (match_dup 2))]
;; Conversion from XFmode to {SF,DF}mode
(define_expand "truncxf<mode>2"
- [(parallel [(set (match_operand:MODEF 0 "nonimmediate_operand" "")
+ [(parallel [(set (match_operand:MODEF 0 "nonimmediate_operand")
(float_truncate:MODEF
- (match_operand:XF 1 "register_operand" "")))
+ (match_operand:XF 1 "register_operand")))
(clobber (match_dup 2))])]
"TARGET_80387"
{
(set_attr "mode" "<MODE>")])
(define_split
- [(set (match_operand:MODEF 0 "register_operand" "")
+ [(set (match_operand:MODEF 0 "register_operand")
(float_truncate:MODEF
- (match_operand:XF 1 "register_operand" "")))
- (clobber (match_operand:MODEF 2 "memory_operand" ""))]
+ (match_operand:XF 1 "register_operand")))
+ (clobber (match_operand:MODEF 2 "memory_operand"))]
"TARGET_80387 && reload_completed"
[(set (match_dup 2) (float_truncate:MODEF (match_dup 1)))
(set (match_dup 0) (match_dup 2))])
(define_split
- [(set (match_operand:MODEF 0 "memory_operand" "")
+ [(set (match_operand:MODEF 0 "memory_operand")
(float_truncate:MODEF
- (match_operand:XF 1 "register_operand" "")))
- (clobber (match_operand:MODEF 2 "memory_operand" ""))]
+ (match_operand:XF 1 "register_operand")))
+ (clobber (match_operand:MODEF 2 "memory_operand"))]
"TARGET_80387"
[(set (match_dup 0) (float_truncate:MODEF (match_dup 1)))])
\f
;; Signed conversion to DImode.
(define_expand "fix_truncxfdi2"
- [(parallel [(set (match_operand:DI 0 "nonimmediate_operand" "")
- (fix:DI (match_operand:XF 1 "register_operand" "")))
+ [(parallel [(set (match_operand:DI 0 "nonimmediate_operand")
+ (fix:DI (match_operand:XF 1 "register_operand")))
(clobber (reg:CC FLAGS_REG))])]
"TARGET_80387"
{
})
(define_expand "fix_trunc<mode>di2"
- [(parallel [(set (match_operand:DI 0 "nonimmediate_operand" "")
- (fix:DI (match_operand:MODEF 1 "register_operand" "")))
+ [(parallel [(set (match_operand:DI 0 "nonimmediate_operand")
+ (fix:DI (match_operand:MODEF 1 "register_operand")))
(clobber (reg:CC FLAGS_REG))])]
"TARGET_80387 || (TARGET_64BIT && SSE_FLOAT_MODE_P (<MODE>mode))"
{
;; Signed conversion to SImode.
(define_expand "fix_truncxfsi2"
- [(parallel [(set (match_operand:SI 0 "nonimmediate_operand" "")
- (fix:SI (match_operand:XF 1 "register_operand" "")))
+ [(parallel [(set (match_operand:SI 0 "nonimmediate_operand")
+ (fix:SI (match_operand:XF 1 "register_operand")))
(clobber (reg:CC FLAGS_REG))])]
"TARGET_80387"
{
})
(define_expand "fix_trunc<mode>si2"
- [(parallel [(set (match_operand:SI 0 "nonimmediate_operand" "")
- (fix:SI (match_operand:MODEF 1 "register_operand" "")))
+ [(parallel [(set (match_operand:SI 0 "nonimmediate_operand")
+ (fix:SI (match_operand:MODEF 1 "register_operand")))
(clobber (reg:CC FLAGS_REG))])]
"TARGET_80387 || SSE_FLOAT_MODE_P (<MODE>mode)"
{
;; Signed conversion to HImode.
(define_expand "fix_trunc<mode>hi2"
- [(parallel [(set (match_operand:HI 0 "nonimmediate_operand" "")
- (fix:HI (match_operand:X87MODEF 1 "register_operand" "")))
+ [(parallel [(set (match_operand:HI 0 "nonimmediate_operand")
+ (fix:HI (match_operand:X87MODEF 1 "register_operand")))
(clobber (reg:CC FLAGS_REG))])]
"TARGET_80387
&& !(SSE_FLOAT_MODE_P (<MODE>mode) && (!TARGET_FISTTP || TARGET_SSE_MATH))"
(define_expand "fixuns_trunc<mode>si2"
[(parallel
- [(set (match_operand:SI 0 "register_operand" "")
+ [(set (match_operand:SI 0 "register_operand")
(unsigned_fix:SI
- (match_operand:MODEF 1 "nonimmediate_operand" "")))
+ (match_operand:MODEF 1 "nonimmediate_operand")))
(use (match_dup 2))
- (clobber (match_scratch:<ssevecmode> 3 ""))
- (clobber (match_scratch:<ssevecmode> 4 ""))])]
+ (clobber (match_scratch:<ssevecmode> 3))
+ (clobber (match_scratch:<ssevecmode> 4))])]
"!TARGET_64BIT && TARGET_SSE2 && TARGET_SSE_MATH"
{
enum machine_mode mode = <MODE>mode;
(define_expand "fixuns_trunc<mode>hi2"
[(set (match_dup 2)
- (fix:SI (match_operand:MODEF 1 "nonimmediate_operand" "")))
- (set (match_operand:HI 0 "nonimmediate_operand" "")
+ (fix:SI (match_operand:MODEF 1 "nonimmediate_operand")))
+ (set (match_operand:HI 0 "nonimmediate_operand")
(subreg:HI (match_dup 2) 0))]
"SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH"
"operands[2] = gen_reg_rtx (SImode);")
;; Shorten x87->SSE reload sequences of fix_trunc?f?i_sse patterns.
(define_peephole2
- [(set (match_operand:MODEF 0 "register_operand" "")
- (match_operand:MODEF 1 "memory_operand" ""))
- (set (match_operand:SWI48x 2 "register_operand" "")
+ [(set (match_operand:MODEF 0 "register_operand")
+ (match_operand:MODEF 1 "memory_operand"))
+ (set (match_operand:SWI48x 2 "register_operand")
(fix:SWI48x (match_dup 0)))]
"TARGET_SHORTEN_X87_SSE
&& !(TARGET_AVOID_VECTOR_DECODE && optimize_insn_for_speed_p ())
;; Avoid vector decoded forms of the instruction.
(define_peephole2
[(match_scratch:DF 2 "x")
- (set (match_operand:SWI48x 0 "register_operand" "")
- (fix:SWI48x (match_operand:DF 1 "memory_operand" "")))]
+ (set (match_operand:SWI48x 0 "register_operand")
+ (fix:SWI48x (match_operand:DF 1 "memory_operand")))]
"TARGET_SSE2 && TARGET_AVOID_VECTOR_DECODE && optimize_insn_for_speed_p ()"
[(set (match_dup 2) (match_dup 1))
(set (match_dup 0) (fix:SWI48x (match_dup 2)))])
(define_peephole2
[(match_scratch:SF 2 "x")
- (set (match_operand:SWI48x 0 "register_operand" "")
- (fix:SWI48x (match_operand:SF 1 "memory_operand" "")))]
+ (set (match_operand:SWI48x 0 "register_operand")
+ (fix:SWI48x (match_operand:SF 1 "memory_operand")))]
"TARGET_AVOID_VECTOR_DECODE && optimize_insn_for_speed_p ()"
[(set (match_dup 2) (match_dup 1))
(set (match_dup 0) (fix:SWI48x (match_dup 2)))])
(define_insn_and_split "fix_trunc<mode>_fisttp_i387_1"
- [(set (match_operand:SWI248x 0 "nonimmediate_operand" "")
- (fix:SWI248x (match_operand 1 "register_operand" "")))]
+ [(set (match_operand:SWI248x 0 "nonimmediate_operand")
+ (fix:SWI248x (match_operand 1 "register_operand")))]
"X87_FLOAT_MODE_P (GET_MODE (operands[1]))
&& TARGET_FISTTP
&& !((SSE_FLOAT_MODE_P (GET_MODE (operands[1]))
(set_attr "mode" "<MODE>")])
(define_split
- [(set (match_operand:SWI248x 0 "register_operand" "")
- (fix:SWI248x (match_operand 1 "register_operand" "")))
- (clobber (match_operand:SWI248x 2 "memory_operand" ""))
- (clobber (match_scratch 3 ""))]
+ [(set (match_operand:SWI248x 0 "register_operand")
+ (fix:SWI248x (match_operand 1 "register_operand")))
+ (clobber (match_operand:SWI248x 2 "memory_operand"))
+ (clobber (match_scratch 3))]
"reload_completed"
[(parallel [(set (match_dup 2) (fix:SWI248x (match_dup 1)))
(clobber (match_dup 3))])
(set (match_dup 0) (match_dup 2))])
(define_split
- [(set (match_operand:SWI248x 0 "memory_operand" "")
- (fix:SWI248x (match_operand 1 "register_operand" "")))
- (clobber (match_operand:SWI248x 2 "memory_operand" ""))
- (clobber (match_scratch 3 ""))]
+ [(set (match_operand:SWI248x 0 "memory_operand")
+ (fix:SWI248x (match_operand 1 "register_operand")))
+ (clobber (match_operand:SWI248x 2 "memory_operand"))
+ (clobber (match_scratch 3))]
"reload_completed"
[(parallel [(set (match_dup 0) (fix:SWI248x (match_dup 1)))
(clobber (match_dup 3))])])
;; clobbering insns can be used. Look at emit_i387_cw_initialization ()
;; function in i386.c.
(define_insn_and_split "*fix_trunc<mode>_i387_1"
- [(set (match_operand:SWI248x 0 "nonimmediate_operand" "")
- (fix:SWI248x (match_operand 1 "register_operand" "")))
+ [(set (match_operand:SWI248x 0 "nonimmediate_operand")
+ (fix:SWI248x (match_operand 1 "register_operand")))
(clobber (reg:CC FLAGS_REG))]
"X87_FLOAT_MODE_P (GET_MODE (operands[1]))
&& !TARGET_FISTTP
(set_attr "mode" "DI")])
(define_split
- [(set (match_operand:DI 0 "register_operand" "")
- (fix:DI (match_operand 1 "register_operand" "")))
- (use (match_operand:HI 2 "memory_operand" ""))
- (use (match_operand:HI 3 "memory_operand" ""))
- (clobber (match_operand:DI 4 "memory_operand" ""))
- (clobber (match_scratch 5 ""))]
+ [(set (match_operand:DI 0 "register_operand")
+ (fix:DI (match_operand 1 "register_operand")))
+ (use (match_operand:HI 2 "memory_operand"))
+ (use (match_operand:HI 3 "memory_operand"))
+ (clobber (match_operand:DI 4 "memory_operand"))
+ (clobber (match_scratch 5))]
"reload_completed"
[(parallel [(set (match_dup 4) (fix:DI (match_dup 1)))
(use (match_dup 2))
(set (match_dup 0) (match_dup 4))])
(define_split
- [(set (match_operand:DI 0 "memory_operand" "")
- (fix:DI (match_operand 1 "register_operand" "")))
- (use (match_operand:HI 2 "memory_operand" ""))
- (use (match_operand:HI 3 "memory_operand" ""))
- (clobber (match_operand:DI 4 "memory_operand" ""))
- (clobber (match_scratch 5 ""))]
+ [(set (match_operand:DI 0 "memory_operand")
+ (fix:DI (match_operand 1 "register_operand")))
+ (use (match_operand:HI 2 "memory_operand"))
+ (use (match_operand:HI 3 "memory_operand"))
+ (clobber (match_operand:DI 4 "memory_operand"))
+ (clobber (match_scratch 5))]
"reload_completed"
[(parallel [(set (match_dup 0) (fix:DI (match_dup 1)))
(use (match_dup 2))
(set_attr "mode" "<MODE>")])
(define_split
- [(set (match_operand:SWI24 0 "register_operand" "")
- (fix:SWI24 (match_operand 1 "register_operand" "")))
- (use (match_operand:HI 2 "memory_operand" ""))
- (use (match_operand:HI 3 "memory_operand" ""))
- (clobber (match_operand:SWI24 4 "memory_operand" ""))]
+ [(set (match_operand:SWI24 0 "register_operand")
+ (fix:SWI24 (match_operand 1 "register_operand")))
+ (use (match_operand:HI 2 "memory_operand"))
+ (use (match_operand:HI 3 "memory_operand"))
+ (clobber (match_operand:SWI24 4 "memory_operand"))]
"reload_completed"
[(parallel [(set (match_dup 4) (fix:SWI24 (match_dup 1)))
(use (match_dup 2))
(set (match_dup 0) (match_dup 4))])
(define_split
- [(set (match_operand:SWI24 0 "memory_operand" "")
- (fix:SWI24 (match_operand 1 "register_operand" "")))
- (use (match_operand:HI 2 "memory_operand" ""))
- (use (match_operand:HI 3 "memory_operand" ""))
- (clobber (match_operand:SWI24 4 "memory_operand" ""))]
+ [(set (match_operand:SWI24 0 "memory_operand")
+ (fix:SWI24 (match_operand 1 "register_operand")))
+ (use (match_operand:HI 2 "memory_operand"))
+ (use (match_operand:HI 3 "memory_operand"))
+ (clobber (match_operand:SWI24 4 "memory_operand"))]
"reload_completed"
[(parallel [(set (match_dup 0) (fix:SWI24 (match_dup 1)))
(use (match_dup 2))
;; wants to be able to do this between registers.
(define_expand "floathi<mode>2"
- [(set (match_operand:X87MODEF 0 "register_operand" "")
- (float:X87MODEF (match_operand:HI 1 "nonimmediate_operand" "")))]
+ [(set (match_operand:X87MODEF 0 "register_operand")
+ (float:X87MODEF (match_operand:HI 1 "nonimmediate_operand")))]
"TARGET_80387
&& (!(SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH)
|| TARGET_MIX_SSE_I387)")
;; Pre-reload splitter to add memory clobber to the pattern.
(define_insn_and_split "*floathi<mode>2_1"
- [(set (match_operand:X87MODEF 0 "register_operand" "")
- (float:X87MODEF (match_operand:HI 1 "register_operand" "")))]
+ [(set (match_operand:X87MODEF 0 "register_operand")
+ (float:X87MODEF (match_operand:HI 1 "register_operand")))]
"TARGET_80387
&& (!(SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH)
|| TARGET_MIX_SSE_I387)
(set_attr "fp_int_src" "true")])
(define_split
- [(set (match_operand:X87MODEF 0 "register_operand" "")
- (float:X87MODEF (match_operand:HI 1 "register_operand" "")))
- (clobber (match_operand:HI 2 "memory_operand" ""))]
+ [(set (match_operand:X87MODEF 0 "register_operand")
+ (float:X87MODEF (match_operand:HI 1 "register_operand")))
+ (clobber (match_operand:HI 2 "memory_operand"))]
"TARGET_80387
&& (!(SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH)
|| TARGET_MIX_SSE_I387)
(set (match_dup 0) (float:X87MODEF (match_dup 2)))])
(define_split
- [(set (match_operand:X87MODEF 0 "register_operand" "")
- (float:X87MODEF (match_operand:HI 1 "memory_operand" "")))
- (clobber (match_operand:HI 2 "memory_operand" ""))]
+ [(set (match_operand:X87MODEF 0 "register_operand")
+ (float:X87MODEF (match_operand:HI 1 "memory_operand")))
+ (clobber (match_operand:HI 2 "memory_operand"))]
"TARGET_80387
&& (!(SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH)
|| TARGET_MIX_SSE_I387)
[(set (match_dup 0) (float:X87MODEF (match_dup 1)))])
(define_expand "float<SWI48x:mode><X87MODEF:mode>2"
- [(set (match_operand:X87MODEF 0 "register_operand" "")
+ [(set (match_operand:X87MODEF 0 "register_operand")
(float:X87MODEF
- (match_operand:SWI48x 1 "nonimmediate_operand" "")))]
+ (match_operand:SWI48x 1 "nonimmediate_operand")))]
"TARGET_80387
|| ((<SWI48x:MODE>mode != DImode || TARGET_64BIT)
&& SSE_FLOAT_MODE_P (<X87MODEF:MODE>mode) && TARGET_SSE_MATH)"
;; Pre-reload splitter to add memory clobber to the pattern.
(define_insn_and_split "*float<SWI48x:mode><X87MODEF:mode>2_1"
- [(set (match_operand:X87MODEF 0 "register_operand" "")
- (float:X87MODEF (match_operand:SWI48x 1 "register_operand" "")))]
+ [(set (match_operand:X87MODEF 0 "register_operand")
+ (float:X87MODEF (match_operand:SWI48x 1 "register_operand")))]
"((TARGET_80387
&& X87_ENABLE_FLOAT (<X87MODEF:MODE>mode, <SWI48x:MODE>mode)
&& (!((<SWI48x:MODE>mode != DImode || TARGET_64BIT)
(set_attr "fp_int_src" "true")])
(define_split
- [(set (match_operand:MODEF 0 "register_operand" "")
- (float:MODEF (match_operand:SWI48x 1 "register_operand" "")))
- (clobber (match_operand:SWI48x 2 "memory_operand" ""))]
+ [(set (match_operand:MODEF 0 "register_operand")
+ (float:MODEF (match_operand:SWI48x 1 "register_operand")))
+ (clobber (match_operand:SWI48x 2 "memory_operand"))]
"(<SWI48x:MODE>mode != DImode || TARGET_64BIT)
&& SSE_FLOAT_MODE_P (<MODEF:MODE>mode) && TARGET_MIX_SSE_I387
&& TARGET_INTER_UNIT_CONVERSIONS
[(set (match_dup 0) (float:MODEF (match_dup 1)))])
(define_split
- [(set (match_operand:MODEF 0 "register_operand" "")
- (float:MODEF (match_operand:SWI48x 1 "register_operand" "")))
- (clobber (match_operand:SWI48x 2 "memory_operand" ""))]
+ [(set (match_operand:MODEF 0 "register_operand")
+ (float:MODEF (match_operand:SWI48x 1 "register_operand")))
+ (clobber (match_operand:SWI48x 2 "memory_operand"))]
"(<SWI48x:MODE>mode != DImode || TARGET_64BIT)
&& SSE_FLOAT_MODE_P (<MODEF:MODE>mode) && TARGET_MIX_SSE_I387
&& !(TARGET_INTER_UNIT_CONVERSIONS || optimize_function_for_size_p (cfun))
(set_attr "fp_int_src" "true")])
(define_split
- [(set (match_operand:MODEF 0 "register_operand" "")
- (float:MODEF (match_operand:SI 1 "register_operand" "")))
- (clobber (match_operand:SI 2 "memory_operand" ""))]
+ [(set (match_operand:MODEF 0 "register_operand")
+ (float:MODEF (match_operand:SI 1 "register_operand")))
+ (clobber (match_operand:SI 2 "memory_operand"))]
"TARGET_SSE2 && TARGET_SSE_MATH
&& TARGET_USE_VECTOR_CONVERTS && optimize_function_for_speed_p (cfun)
&& reload_completed
})
(define_split
- [(set (match_operand:MODEF 0 "register_operand" "")
- (float:MODEF (match_operand:SI 1 "memory_operand" "")))
- (clobber (match_operand:SI 2 "memory_operand" ""))]
+ [(set (match_operand:MODEF 0 "register_operand")
+ (float:MODEF (match_operand:SI 1 "memory_operand")))
+ (clobber (match_operand:SI 2 "memory_operand"))]
"TARGET_SSE2 && TARGET_SSE_MATH
&& TARGET_USE_VECTOR_CONVERTS && optimize_function_for_speed_p (cfun)
&& reload_completed
})
(define_split
- [(set (match_operand:MODEF 0 "register_operand" "")
- (float:MODEF (match_operand:SI 1 "register_operand" "")))]
+ [(set (match_operand:MODEF 0 "register_operand")
+ (float:MODEF (match_operand:SI 1 "register_operand")))]
"TARGET_SSE2 && TARGET_SSE_MATH
&& TARGET_USE_VECTOR_CONVERTS && optimize_function_for_speed_p (cfun)
&& reload_completed
})
(define_split
- [(set (match_operand:MODEF 0 "register_operand" "")
- (float:MODEF (match_operand:SI 1 "memory_operand" "")))]
+ [(set (match_operand:MODEF 0 "register_operand")
+ (float:MODEF (match_operand:SI 1 "memory_operand")))]
"TARGET_SSE2 && TARGET_SSE_MATH
&& TARGET_USE_VECTOR_CONVERTS && optimize_function_for_speed_p (cfun)
&& reload_completed
(set_attr "fp_int_src" "true")])
(define_split
- [(set (match_operand:MODEF 0 "register_operand" "")
- (float:MODEF (match_operand:SWI48x 1 "nonimmediate_operand" "")))
- (clobber (match_operand:SWI48x 2 "memory_operand" ""))]
+ [(set (match_operand:MODEF 0 "register_operand")
+ (float:MODEF (match_operand:SWI48x 1 "nonimmediate_operand")))
+ (clobber (match_operand:SWI48x 2 "memory_operand"))]
"(<SWI48x:MODE>mode != DImode || TARGET_64BIT)
&& SSE_FLOAT_MODE_P (<MODEF:MODE>mode) && TARGET_SSE_MATH
&& (TARGET_INTER_UNIT_CONVERSIONS || optimize_function_for_size_p (cfun))
(set_attr "fp_int_src" "true")])
(define_split
- [(set (match_operand:MODEF 0 "register_operand" "")
- (float:MODEF (match_operand:SWI48x 1 "register_operand" "")))
- (clobber (match_operand:SWI48x 2 "memory_operand" ""))]
+ [(set (match_operand:MODEF 0 "register_operand")
+ (float:MODEF (match_operand:SWI48x 1 "register_operand")))
+ (clobber (match_operand:SWI48x 2 "memory_operand"))]
"(<SWI48x:MODE>mode != DImode || TARGET_64BIT)
&& SSE_FLOAT_MODE_P (<MODEF:MODE>mode) && TARGET_SSE_MATH
&& !(TARGET_INTER_UNIT_CONVERSIONS || optimize_function_for_size_p (cfun))
(set (match_dup 0) (float:MODEF (match_dup 2)))])
(define_split
- [(set (match_operand:MODEF 0 "register_operand" "")
- (float:MODEF (match_operand:SWI48x 1 "memory_operand" "")))
- (clobber (match_operand:SWI48x 2 "memory_operand" ""))]
+ [(set (match_operand:MODEF 0 "register_operand")
+ (float:MODEF (match_operand:SWI48x 1 "memory_operand")))
+ (clobber (match_operand:SWI48x 2 "memory_operand"))]
"(<SWI48x:MODE>mode != DImode || TARGET_64BIT)
&& SSE_FLOAT_MODE_P (<MODEF:MODE>mode) && TARGET_SSE_MATH
&& reload_completed
(set_attr "fp_int_src" "true")])
(define_split
- [(set (match_operand:X87MODEF 0 "fp_register_operand" "")
- (float:X87MODEF (match_operand:SWI48x 1 "register_operand" "")))
- (clobber (match_operand:SWI48x 2 "memory_operand" ""))]
+ [(set (match_operand:X87MODEF 0 "fp_register_operand")
+ (float:X87MODEF (match_operand:SWI48x 1 "register_operand")))
+ (clobber (match_operand:SWI48x 2 "memory_operand"))]
"TARGET_80387
&& X87_ENABLE_FLOAT (<X87MODEF:MODE>mode, <SWI48x:MODE>mode)
&& reload_completed"
(set (match_dup 0) (float:X87MODEF (match_dup 2)))])
(define_split
- [(set (match_operand:X87MODEF 0 "fp_register_operand" "")
- (float:X87MODEF (match_operand:SWI48x 1 "memory_operand" "")))
- (clobber (match_operand:SWI48x 2 "memory_operand" ""))]
+ [(set (match_operand:X87MODEF 0 "fp_register_operand")
+ (float:X87MODEF (match_operand:SWI48x 1 "memory_operand")))
+ (clobber (match_operand:SWI48x 2 "memory_operand"))]
"TARGET_80387
&& X87_ENABLE_FLOAT (<X87MODEF:MODE>mode, <SWI48x:MODE>mode)
&& reload_completed"
(set_attr "fp_int_src" "true")])
(define_split
- [(set (match_operand:X87MODEF 0 "fp_register_operand" "")
- (float:X87MODEF (match_operand:DI 1 "register_operand" "")))
- (clobber (match_scratch:V4SI 3 ""))
- (clobber (match_scratch:V4SI 4 ""))
- (clobber (match_operand:DI 2 "memory_operand" ""))]
+ [(set (match_operand:X87MODEF 0 "fp_register_operand")
+ (float:X87MODEF (match_operand:DI 1 "register_operand")))
+ (clobber (match_scratch:V4SI 3))
+ (clobber (match_scratch:V4SI 4))
+ (clobber (match_operand:DI 2 "memory_operand"))]
"TARGET_80387 && X87_ENABLE_FLOAT (<X87MODEF:MODE>mode, DImode)
&& TARGET_SSE2 && TARGET_INTER_UNIT_MOVES
&& !TARGET_64BIT && optimize_function_for_speed_p (cfun)
})
(define_split
- [(set (match_operand:X87MODEF 0 "fp_register_operand" "")
- (float:X87MODEF (match_operand:DI 1 "memory_operand" "")))
- (clobber (match_scratch:V4SI 3 ""))
- (clobber (match_scratch:V4SI 4 ""))
- (clobber (match_operand:DI 2 "memory_operand" ""))]
+ [(set (match_operand:X87MODEF 0 "fp_register_operand")
+ (float:X87MODEF (match_operand:DI 1 "memory_operand")))
+ (clobber (match_scratch:V4SI 3))
+ (clobber (match_scratch:V4SI 4))
+ (clobber (match_operand:DI 2 "memory_operand"))]
"TARGET_80387 && X87_ENABLE_FLOAT (<X87MODEF:MODE>mode, DImode)
&& TARGET_SSE2 && TARGET_INTER_UNIT_MOVES
&& !TARGET_64BIT && optimize_function_for_speed_p (cfun)
(set_attr "mode" "<MODE>")])
(define_split
- [(set (match_operand:X87MODEF 0 "register_operand" "")
+ [(set (match_operand:X87MODEF 0 "register_operand")
(unsigned_float:X87MODEF
- (match_operand:SI 1 "register_operand" "")))
- (clobber (match_operand:DI 2 "memory_operand" ""))
- (clobber (match_scratch:SI 3 ""))]
+ (match_operand:SI 1 "register_operand")))
+ (clobber (match_operand:DI 2 "memory_operand"))
+ (clobber (match_scratch:SI 3))]
"!TARGET_64BIT
&& TARGET_80387 && X87_ENABLE_FLOAT (<X87MODEF:MODE>mode, DImode)
&& TARGET_SSE
"operands[1] = simplify_gen_subreg (DImode, operands[1], SImode, 0);")
(define_split
- [(set (match_operand:X87MODEF 0 "register_operand" "")
+ [(set (match_operand:X87MODEF 0 "register_operand")
(unsigned_float:X87MODEF
- (match_operand:SI 1 "memory_operand" "")))
- (clobber (match_operand:DI 2 "memory_operand" ""))
- (clobber (match_scratch:SI 3 ""))]
+ (match_operand:SI 1 "memory_operand")))
+ (clobber (match_operand:DI 2 "memory_operand"))
+ (clobber (match_scratch:SI 3))]
"!TARGET_64BIT
&& TARGET_80387 && X87_ENABLE_FLOAT (<X87MODEF:MODE>mode, DImode)
&& TARGET_SSE
(define_expand "floatunssi<mode>2"
[(parallel
- [(set (match_operand:X87MODEF 0 "register_operand" "")
+ [(set (match_operand:X87MODEF 0 "register_operand")
(unsigned_float:X87MODEF
- (match_operand:SI 1 "nonimmediate_operand" "")))
+ (match_operand:SI 1 "nonimmediate_operand")))
(clobber (match_dup 2))
- (clobber (match_scratch:SI 3 ""))])]
+ (clobber (match_scratch:SI 3))])]
"!TARGET_64BIT
&& ((TARGET_80387 && X87_ENABLE_FLOAT (<X87MODEF:MODE>mode, DImode)
&& TARGET_SSE)
})
(define_expand "floatunsdisf2"
- [(use (match_operand:SF 0 "register_operand" ""))
- (use (match_operand:DI 1 "nonimmediate_operand" ""))]
+ [(use (match_operand:SF 0 "register_operand"))
+ (use (match_operand:DI 1 "nonimmediate_operand"))]
"TARGET_64BIT && TARGET_SSE_MATH"
"x86_emit_floatuns (operands); DONE;")
(define_expand "floatunsdidf2"
- [(use (match_operand:DF 0 "register_operand" ""))
- (use (match_operand:DI 1 "nonimmediate_operand" ""))]
+ [(use (match_operand:DF 0 "register_operand"))
+ (use (match_operand:DI 1 "nonimmediate_operand"))]
"(TARGET_64BIT || TARGET_KEEPS_VECTOR_ALIGNED_STACK)
&& TARGET_SSE2 && TARGET_SSE_MATH"
{
;; Add instructions
(define_expand "add<mode>3"
- [(set (match_operand:SDWIM 0 "nonimmediate_operand" "")
- (plus:SDWIM (match_operand:SDWIM 1 "nonimmediate_operand" "")
- (match_operand:SDWIM 2 "<general_operand>" "")))]
+ [(set (match_operand:SDWIM 0 "nonimmediate_operand")
+ (plus:SDWIM (match_operand:SDWIM 1 "nonimmediate_operand")
+ (match_operand:SDWIM 2 "<general_operand>")))]
""
"ix86_expand_binary_operator (PLUS, <MODE>mode, operands); DONE;")
[(set (attr "type")
(cond [(eq_attr "alternative" "3")
(const_string "lea")
- (match_operand:SWI48 2 "incdec_operand" "")
+ (match_operand:SWI48 2 "incdec_operand")
(const_string "incdec")
]
(const_string "alu")))
(set (attr "length_immediate")
(if_then_else
- (and (eq_attr "type" "alu") (match_operand 2 "const128_operand" ""))
+ (and (eq_attr "type" "alu") (match_operand 2 "const128_operand"))
(const_string "1")
(const_string "*")))
(set_attr "mode" "<MODE>")])
[(set (attr "type")
(cond [(eq_attr "alternative" "2")
(const_string "lea")
- (match_operand:SI 2 "incdec_operand" "")
+ (match_operand:SI 2 "incdec_operand")
(const_string "incdec")
]
(const_string "alu")))
(set (attr "length_immediate")
(if_then_else
- (and (eq_attr "type" "alu") (match_operand 2 "const128_operand" ""))
+ (and (eq_attr "type" "alu") (match_operand 2 "const128_operand"))
(const_string "1")
(const_string "*")))
(set_attr "mode" "SI")])
[(set (attr "type")
(cond [(eq_attr "alternative" "3")
(const_string "lea")
- (match_operand:HI 2 "incdec_operand" "")
+ (match_operand:HI 2 "incdec_operand")
(const_string "incdec")
]
(const_string "alu")))
(set (attr "length_immediate")
(if_then_else
- (and (eq_attr "type" "alu") (match_operand 2 "const128_operand" ""))
+ (and (eq_attr "type" "alu") (match_operand 2 "const128_operand"))
(const_string "1")
(const_string "*")))
(set_attr "mode" "HI,HI,HI,SI")])
[(set (attr "type")
(cond [(eq_attr "alternative" "5")
(const_string "lea")
- (match_operand:QI 2 "incdec_operand" "")
+ (match_operand:QI 2 "incdec_operand")
(const_string "incdec")
]
(const_string "alu")))
(set (attr "length_immediate")
(if_then_else
- (and (eq_attr "type" "alu") (match_operand 2 "const128_operand" ""))
+ (and (eq_attr "type" "alu") (match_operand 2 "const128_operand"))
(const_string "1")
(const_string "*")))
(set_attr "mode" "QI,QI,QI,SI,SI,SI")])
}
}
[(set (attr "type")
- (if_then_else (match_operand:QI 1 "incdec_operand" "")
+ (if_then_else (match_operand:QI 1 "incdec_operand")
(const_string "incdec")
(const_string "alu1")))
(set (attr "memory")
- (if_then_else (match_operand 1 "memory_operand" "")
+ (if_then_else (match_operand 1 "memory_operand")
(const_string "load")
(const_string "none")))
(set_attr "mode" "QI")])
;; Split non destructive adds if we cannot use lea.
(define_split
- [(set (match_operand:SWI48 0 "register_operand" "")
- (plus:SWI48 (match_operand:SWI48 1 "register_operand" "")
- (match_operand:SWI48 2 "nonmemory_operand" "")))
+ [(set (match_operand:SWI48 0 "register_operand")
+ (plus:SWI48 (match_operand:SWI48 1 "register_operand")
+ (match_operand:SWI48 2 "nonmemory_operand")))
(clobber (reg:CC FLAGS_REG))]
"reload_completed && ix86_avoid_lea_for_add (insn, operands)"
[(set (match_dup 0) (match_dup 1))
;; Convert add to the lea pattern to avoid flags dependency.
(define_split
- [(set (match_operand:SWI 0 "register_operand" "")
- (plus:SWI (match_operand:SWI 1 "register_operand" "")
- (match_operand:SWI 2 "<nonmemory_operand>" "")))
+ [(set (match_operand:SWI 0 "register_operand")
+ (plus:SWI (match_operand:SWI 1 "register_operand")
+ (match_operand:SWI 2 "<nonmemory_operand>")))
(clobber (reg:CC FLAGS_REG))]
"reload_completed && ix86_lea_for_add_ok (insn, operands)"
[(const_int 0)]
;; Convert add to the lea pattern to avoid flags dependency.
(define_split
- [(set (match_operand:DI 0 "register_operand" "")
+ [(set (match_operand:DI 0 "register_operand")
(zero_extend:DI
- (plus:SI (match_operand:SI 1 "register_operand" "")
- (match_operand:SI 2 "x86_64_nonmemory_operand" ""))))
+ (plus:SI (match_operand:SI 1 "register_operand")
+ (match_operand:SI 2 "x86_64_nonmemory_operand"))))
(clobber (reg:CC FLAGS_REG))]
"TARGET_64BIT && reload_completed && ix86_lea_for_add_ok (insn, operands)"
[(set (match_dup 0)
}
}
[(set (attr "type")
- (if_then_else (match_operand:SWI 2 "incdec_operand" "")
+ (if_then_else (match_operand:SWI 2 "incdec_operand")
(const_string "incdec")
(const_string "alu")))
(set (attr "length_immediate")
(if_then_else
- (and (eq_attr "type" "alu") (match_operand 2 "const128_operand" ""))
+ (and (eq_attr "type" "alu") (match_operand 2 "const128_operand"))
(const_string "1")
(const_string "*")))
(set_attr "mode" "<MODE>")])
}
}
[(set (attr "type")
- (if_then_else (match_operand:SI 2 "incdec_operand" "")
+ (if_then_else (match_operand:SI 2 "incdec_operand")
(const_string "incdec")
(const_string "alu")))
(set (attr "length_immediate")
(if_then_else
- (and (eq_attr "type" "alu") (match_operand 2 "const128_operand" ""))
+ (and (eq_attr "type" "alu") (match_operand 2 "const128_operand"))
(const_string "1")
(const_string "*")))
(set_attr "mode" "SI")])
}
}
[(set (attr "type")
- (if_then_else (match_operand:SWI 2 "incdec_operand" "")
+ (if_then_else (match_operand:SWI 2 "incdec_operand")
(const_string "incdec")
(const_string "alu")))
(set (attr "length_immediate")
(if_then_else
- (and (eq_attr "type" "alu") (match_operand 2 "const128_operand" ""))
+ (and (eq_attr "type" "alu") (match_operand 2 "const128_operand"))
(const_string "1")
(const_string "*")))
(set_attr "mode" "<MODE>")])
}
}
[(set (attr "type")
- (if_then_else (match_operand:SI 2 "incdec_operand" "")
+ (if_then_else (match_operand:SI 2 "incdec_operand")
(const_string "incdec")
(const_string "alu")))
(set (attr "length_immediate")
(if_then_else
- (and (eq_attr "type" "alu") (match_operand 2 "const128_operand" ""))
+ (and (eq_attr "type" "alu") (match_operand 2 "const128_operand"))
(const_string "1")
(const_string "*")))
(set_attr "mode" "SI")])
}
}
[(set (attr "type")
- (if_then_else (match_operand:DI 2 "incdec_operand" "")
+ (if_then_else (match_operand:DI 2 "incdec_operand")
(const_string "incdec")
(const_string "alu")))
(set (attr "length_immediate")
(if_then_else
- (and (eq_attr "type" "alu") (match_operand 2 "const128_operand" ""))
+ (and (eq_attr "type" "alu") (match_operand 2 "const128_operand"))
(const_string "1")
(const_string "*")))
(set_attr "mode" "DI")])
}
}
[(set (attr "type")
- (if_then_else (match_operand:<MODE> 2 "incdec_operand" "")
+ (if_then_else (match_operand:<MODE> 2 "incdec_operand")
(const_string "incdec")
(const_string "alu")))
(set (attr "length_immediate")
(if_then_else
- (and (eq_attr "type" "alu") (match_operand 2 "const128_operand" ""))
+ (and (eq_attr "type" "alu") (match_operand 2 "const128_operand"))
(const_string "1")
(const_string "*")))
(set_attr "mode" "<MODE>")])
}
}
[(set (attr "type")
- (if_then_else (match_operand:SWI 2 "incdec_operand" "")
+ (if_then_else (match_operand:SWI 2 "incdec_operand")
(const_string "incdec")
(const_string "alu")))
(set (attr "length_immediate")
(if_then_else
- (and (eq_attr "type" "alu") (match_operand 2 "const128_operand" ""))
+ (and (eq_attr "type" "alu") (match_operand 2 "const128_operand"))
(const_string "1")
(const_string "*")))
(set_attr "mode" "<MODE>")])
}
}
[(set (attr "type")
- (if_then_else (match_operand:QI 2 "incdec_operand" "")
+ (if_then_else (match_operand:QI 2 "incdec_operand")
(const_string "incdec")
(const_string "alu")))
(set_attr "modrm" "1")
}
}
[(set (attr "type")
- (if_then_else (match_operand:QI 2 "incdec_operand" "")
+ (if_then_else (match_operand:QI 2 "incdec_operand")
(const_string "incdec")
(const_string "alu")))
(set_attr "modrm" "1")
}
[(set_attr "type" "lea")
(set (attr "mode")
- (if_then_else (match_operand:DI 0 "" "")
+ (if_then_else (match_operand:DI 0)
(const_string "DI")
(const_string "SI")))])
\f
;; Subtract instructions
(define_expand "sub<mode>3"
- [(set (match_operand:SDWIM 0 "nonimmediate_operand" "")
- (minus:SDWIM (match_operand:SDWIM 1 "nonimmediate_operand" "")
- (match_operand:SDWIM 2 "<general_operand>" "")))]
+ [(set (match_operand:SDWIM 0 "nonimmediate_operand")
+ (minus:SDWIM (match_operand:SDWIM 1 "nonimmediate_operand")
+ (match_operand:SDWIM 2 "<general_operand>")))]
""
"ix86_expand_binary_operator (MINUS, <MODE>mode, operands); DONE;")
(define_expand "<plusminus_insn><mode>3_carry"
[(parallel
- [(set (match_operand:SWI 0 "nonimmediate_operand" "")
+ [(set (match_operand:SWI 0 "nonimmediate_operand")
(plusminus:SWI
- (match_operand:SWI 1 "nonimmediate_operand" "")
+ (match_operand:SWI 1 "nonimmediate_operand")
(plus:SWI (match_operator:SWI 4 "ix86_carry_flag_operator"
- [(match_operand 3 "flags_reg_operand" "")
+ [(match_operand 3 "flags_reg_operand")
(const_int 0)])
- (match_operand:SWI 2 "<general_operand>" ""))))
+ (match_operand:SWI 2 "<general_operand>"))))
(clobber (reg:CC FLAGS_REG))])]
"ix86_binary_operator_ok (<CODE>, <MODE>mode, operands)")
;; The patterns that match these are at the end of this file.
(define_expand "<plusminus_insn>xf3"
- [(set (match_operand:XF 0 "register_operand" "")
+ [(set (match_operand:XF 0 "register_operand")
(plusminus:XF
- (match_operand:XF 1 "register_operand" "")
- (match_operand:XF 2 "register_operand" "")))]
+ (match_operand:XF 1 "register_operand")
+ (match_operand:XF 2 "register_operand")))]
"TARGET_80387")
(define_expand "<plusminus_insn><mode>3"
- [(set (match_operand:MODEF 0 "register_operand" "")
+ [(set (match_operand:MODEF 0 "register_operand")
(plusminus:MODEF
- (match_operand:MODEF 1 "register_operand" "")
- (match_operand:MODEF 2 "nonimmediate_operand" "")))]
+ (match_operand:MODEF 1 "register_operand")
+ (match_operand:MODEF 2 "nonimmediate_operand")))]
"(TARGET_80387 && X87_ENABLE_ARITH (<MODE>mode))
|| (SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH)")
\f
;; Multiply instructions
(define_expand "mul<mode>3"
- [(parallel [(set (match_operand:SWIM248 0 "register_operand" "")
+ [(parallel [(set (match_operand:SWIM248 0 "register_operand")
(mult:SWIM248
- (match_operand:SWIM248 1 "register_operand" "")
- (match_operand:SWIM248 2 "<general_operand>" "")))
+ (match_operand:SWIM248 1 "register_operand")
+ (match_operand:SWIM248 2 "<general_operand>")))
(clobber (reg:CC FLAGS_REG))])])
(define_expand "mulqi3"
- [(parallel [(set (match_operand:QI 0 "register_operand" "")
+ [(parallel [(set (match_operand:QI 0 "register_operand")
(mult:QI
- (match_operand:QI 1 "register_operand" "")
- (match_operand:QI 2 "nonimmediate_operand" "")))
+ (match_operand:QI 1 "register_operand")
+ (match_operand:QI 2 "nonimmediate_operand")))
(clobber (reg:CC FLAGS_REG))])]
"TARGET_QIMODE_MATH")
(eq_attr "alternative" "1")
(const_string "vector")
(and (eq_attr "alternative" "2")
- (match_operand 1 "memory_operand" ""))
+ (match_operand 1 "memory_operand"))
(const_string "vector")]
(const_string "direct")))
(set (attr "amdfam10_decode")
(cond [(and (eq_attr "alternative" "0,1")
- (match_operand 1 "memory_operand" ""))
+ (match_operand 1 "memory_operand"))
(const_string "vector")]
(const_string "direct")))
(set_attr "bdver1_decode" "direct")
(eq_attr "alternative" "1")
(const_string "vector")
(and (eq_attr "alternative" "2")
- (match_operand 1 "memory_operand" ""))
+ (match_operand 1 "memory_operand"))
(const_string "vector")]
(const_string "direct")))
(set (attr "amdfam10_decode")
(cond [(and (eq_attr "alternative" "0,1")
- (match_operand 1 "memory_operand" ""))
+ (match_operand 1 "memory_operand"))
(const_string "vector")]
(const_string "direct")))
(set_attr "bdver1_decode" "direct")
(set_attr "mode" "QI")])
(define_expand "<u>mul<mode><dwi>3"
- [(parallel [(set (match_operand:<DWI> 0 "register_operand" "")
+ [(parallel [(set (match_operand:<DWI> 0 "register_operand")
(mult:<DWI>
(any_extend:<DWI>
- (match_operand:DWIH 1 "nonimmediate_operand" ""))
+ (match_operand:DWIH 1 "nonimmediate_operand"))
(any_extend:<DWI>
- (match_operand:DWIH 2 "register_operand" ""))))
+ (match_operand:DWIH 2 "register_operand"))))
(clobber (reg:CC FLAGS_REG))])])
(define_expand "<u>mulqihi3"
- [(parallel [(set (match_operand:HI 0 "register_operand" "")
+ [(parallel [(set (match_operand:HI 0 "register_operand")
(mult:HI
(any_extend:HI
- (match_operand:QI 1 "nonimmediate_operand" ""))
+ (match_operand:QI 1 "nonimmediate_operand"))
(any_extend:HI
- (match_operand:QI 2 "register_operand" ""))))
+ (match_operand:QI 2 "register_operand"))))
(clobber (reg:CC FLAGS_REG))])]
"TARGET_QIMODE_MATH")
;; Convert mul to the mulx pattern to avoid flags dependency.
(define_split
- [(set (match_operand:<DWI> 0 "register_operand" "")
+ [(set (match_operand:<DWI> 0 "register_operand")
(mult:<DWI>
(zero_extend:<DWI>
- (match_operand:DWIH 1 "register_operand" ""))
+ (match_operand:DWIH 1 "register_operand"))
(zero_extend:<DWI>
- (match_operand:DWIH 2 "nonimmediate_operand" ""))))
+ (match_operand:DWIH 2 "nonimmediate_operand"))))
(clobber (reg:CC FLAGS_REG))]
"TARGET_BMI2 && reload_completed
&& true_regnum (operands[1]) == DX_REG"
(set_attr "mode" "QI")])
(define_expand "<s>mul<mode>3_highpart"
- [(parallel [(set (match_operand:SWI48 0 "register_operand" "")
+ [(parallel [(set (match_operand:SWI48 0 "register_operand")
(truncate:SWI48
(lshiftrt:<DWI>
(mult:<DWI>
(any_extend:<DWI>
- (match_operand:SWI48 1 "nonimmediate_operand" ""))
+ (match_operand:SWI48 1 "nonimmediate_operand"))
(any_extend:<DWI>
- (match_operand:SWI48 2 "register_operand" "")))
+ (match_operand:SWI48 2 "register_operand")))
(match_dup 4))))
- (clobber (match_scratch:SWI48 3 ""))
+ (clobber (match_scratch:SWI48 3))
(clobber (reg:CC FLAGS_REG))])]
""
"operands[4] = GEN_INT (GET_MODE_BITSIZE (<MODE>mode));")
;; The patterns that match these are at the end of this file.
(define_expand "mulxf3"
- [(set (match_operand:XF 0 "register_operand" "")
- (mult:XF (match_operand:XF 1 "register_operand" "")
- (match_operand:XF 2 "register_operand" "")))]
+ [(set (match_operand:XF 0 "register_operand")
+ (mult:XF (match_operand:XF 1 "register_operand")
+ (match_operand:XF 2 "register_operand")))]
"TARGET_80387")
(define_expand "mul<mode>3"
- [(set (match_operand:MODEF 0 "register_operand" "")
- (mult:MODEF (match_operand:MODEF 1 "register_operand" "")
- (match_operand:MODEF 2 "nonimmediate_operand" "")))]
+ [(set (match_operand:MODEF 0 "register_operand")
+ (mult:MODEF (match_operand:MODEF 1 "register_operand")
+ (match_operand:MODEF 2 "nonimmediate_operand")))]
"(TARGET_80387 && X87_ENABLE_ARITH (<MODE>mode))
|| (SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH)")
\f
;; The patterns that match these are at the end of this file.
(define_expand "divxf3"
- [(set (match_operand:XF 0 "register_operand" "")
- (div:XF (match_operand:XF 1 "register_operand" "")
- (match_operand:XF 2 "register_operand" "")))]
+ [(set (match_operand:XF 0 "register_operand")
+ (div:XF (match_operand:XF 1 "register_operand")
+ (match_operand:XF 2 "register_operand")))]
"TARGET_80387")
(define_expand "divdf3"
- [(set (match_operand:DF 0 "register_operand" "")
- (div:DF (match_operand:DF 1 "register_operand" "")
- (match_operand:DF 2 "nonimmediate_operand" "")))]
+ [(set (match_operand:DF 0 "register_operand")
+ (div:DF (match_operand:DF 1 "register_operand")
+ (match_operand:DF 2 "nonimmediate_operand")))]
"(TARGET_80387 && X87_ENABLE_ARITH (DFmode))
|| (TARGET_SSE2 && TARGET_SSE_MATH)")
(define_expand "divsf3"
- [(set (match_operand:SF 0 "register_operand" "")
- (div:SF (match_operand:SF 1 "register_operand" "")
- (match_operand:SF 2 "nonimmediate_operand" "")))]
+ [(set (match_operand:SF 0 "register_operand")
+ (div:SF (match_operand:SF 1 "register_operand")
+ (match_operand:SF 2 "nonimmediate_operand")))]
"(TARGET_80387 && X87_ENABLE_ARITH (SFmode))
|| TARGET_SSE_MATH"
{
;; Divmod instructions.
(define_expand "divmod<mode>4"
- [(parallel [(set (match_operand:SWIM248 0 "register_operand" "")
+ [(parallel [(set (match_operand:SWIM248 0 "register_operand")
(div:SWIM248
- (match_operand:SWIM248 1 "register_operand" "")
- (match_operand:SWIM248 2 "nonimmediate_operand" "")))
- (set (match_operand:SWIM248 3 "register_operand" "")
+ (match_operand:SWIM248 1 "register_operand")
+ (match_operand:SWIM248 2 "nonimmediate_operand")))
+ (set (match_operand:SWIM248 3 "register_operand")
(mod:SWIM248 (match_dup 1) (match_dup 2)))
(clobber (reg:CC FLAGS_REG))])])
;; else
;; use original integer divide
(define_split
- [(set (match_operand:SWI48 0 "register_operand" "")
- (div:SWI48 (match_operand:SWI48 2 "register_operand" "")
- (match_operand:SWI48 3 "nonimmediate_operand" "")))
- (set (match_operand:SWI48 1 "register_operand" "")
+ [(set (match_operand:SWI48 0 "register_operand")
+ (div:SWI48 (match_operand:SWI48 2 "register_operand")
+ (match_operand:SWI48 3 "nonimmediate_operand")))
+ (set (match_operand:SWI48 1 "register_operand")
(mod:SWI48 (match_dup 2) (match_dup 3)))
(clobber (reg:CC FLAGS_REG))]
"TARGET_USE_8BIT_IDIV
(set_attr "mode" "<MODE>")])
(define_expand "divmodqi4"
- [(parallel [(set (match_operand:QI 0 "register_operand" "")
+ [(parallel [(set (match_operand:QI 0 "register_operand")
(div:QI
- (match_operand:QI 1 "register_operand" "")
- (match_operand:QI 2 "nonimmediate_operand" "")))
- (set (match_operand:QI 3 "register_operand" "")
+ (match_operand:QI 1 "register_operand")
+ (match_operand:QI 2 "nonimmediate_operand")))
+ (set (match_operand:QI 3 "register_operand")
(mod:QI (match_dup 1) (match_dup 2)))
(clobber (reg:CC FLAGS_REG))])]
"TARGET_QIMODE_MATH"
(set_attr "mode" "QI")])
(define_expand "udivmod<mode>4"
- [(parallel [(set (match_operand:SWIM248 0 "register_operand" "")
+ [(parallel [(set (match_operand:SWIM248 0 "register_operand")
(udiv:SWIM248
- (match_operand:SWIM248 1 "register_operand" "")
- (match_operand:SWIM248 2 "nonimmediate_operand" "")))
- (set (match_operand:SWIM248 3 "register_operand" "")
+ (match_operand:SWIM248 1 "register_operand")
+ (match_operand:SWIM248 2 "nonimmediate_operand")))
+ (set (match_operand:SWIM248 3 "register_operand")
(umod:SWIM248 (match_dup 1) (match_dup 2)))
(clobber (reg:CC FLAGS_REG))])])
;; else
;; use original integer divide
(define_split
- [(set (match_operand:SWI48 0 "register_operand" "")
- (udiv:SWI48 (match_operand:SWI48 2 "register_operand" "")
- (match_operand:SWI48 3 "nonimmediate_operand" "")))
- (set (match_operand:SWI48 1 "register_operand" "")
+ [(set (match_operand:SWI48 0 "register_operand")
+ (udiv:SWI48 (match_operand:SWI48 2 "register_operand")
+ (match_operand:SWI48 3 "nonimmediate_operand")))
+ (set (match_operand:SWI48 1 "register_operand")
(umod:SWI48 (match_dup 2) (match_dup 3)))
(clobber (reg:CC FLAGS_REG))]
"TARGET_USE_8BIT_IDIV
(set_attr "mode" "<MODE>")])
(define_expand "udivmodqi4"
- [(parallel [(set (match_operand:QI 0 "register_operand" "")
+ [(parallel [(set (match_operand:QI 0 "register_operand")
(udiv:QI
- (match_operand:QI 1 "register_operand" "")
- (match_operand:QI 2 "nonimmediate_operand" "")))
- (set (match_operand:QI 3 "register_operand" "")
+ (match_operand:QI 1 "register_operand")
+ (match_operand:QI 2 "nonimmediate_operand")))
+ (set (match_operand:QI 3 "register_operand")
(umod:QI (match_dup 1) (match_dup 2)))
(clobber (reg:CC FLAGS_REG))])]
"TARGET_QIMODE_MATH"
(define_expand "testsi_ccno_1"
[(set (reg:CCNO FLAGS_REG)
(compare:CCNO
- (and:SI (match_operand:SI 0 "nonimmediate_operand" "")
- (match_operand:SI 1 "x86_64_nonmemory_operand" ""))
+ (and:SI (match_operand:SI 0 "nonimmediate_operand")
+ (match_operand:SI 1 "x86_64_nonmemory_operand"))
(const_int 0)))])
(define_expand "testqi_ccz_1"
[(set (reg:CCZ FLAGS_REG)
- (compare:CCZ (and:QI (match_operand:QI 0 "nonimmediate_operand" "")
- (match_operand:QI 1 "nonmemory_operand" ""))
+ (compare:CCZ (and:QI (match_operand:QI 0 "nonimmediate_operand")
+ (match_operand:QI 1 "nonmemory_operand"))
(const_int 0)))])
(define_expand "testdi_ccno_1"
[(set (reg:CCNO FLAGS_REG)
(compare:CCNO
- (and:DI (match_operand:DI 0 "nonimmediate_operand" "")
- (match_operand:DI 1 "x86_64_szext_general_operand" ""))
+ (and:DI (match_operand:DI 0 "nonimmediate_operand")
+ (match_operand:DI 1 "x86_64_szext_general_operand"))
(const_int 0)))]
"TARGET_64BIT && !(MEM_P (operands[0]) && MEM_P (operands[1]))")
(compare:CCNO
(and:SI
(zero_extract:SI
- (match_operand 0 "ext_register_operand" "")
+ (match_operand 0 "ext_register_operand")
(const_int 8)
(const_int 8))
- (match_operand 1 "const_int_operand" ""))
+ (match_operand 1 "const_int_operand"))
(const_int 0)))])
(define_insn "*testqi_ext_0"
[(set (reg FLAGS_REG)
(compare (zero_extract:DI
(match_operand 0 "nonimmediate_operand" "rm")
- (match_operand:DI 1 "const_int_operand" "")
- (match_operand:DI 2 "const_int_operand" ""))
+ (match_operand:DI 1 "const_int_operand")
+ (match_operand:DI 2 "const_int_operand"))
(const_int 0)))]
"TARGET_64BIT
&& ix86_match_ccmode (insn, CCNOmode)
[(set (reg FLAGS_REG)
(compare (zero_extract:SI
(match_operand 0 "nonimmediate_operand" "rm")
- (match_operand:SI 1 "const_int_operand" "")
- (match_operand:SI 2 "const_int_operand" ""))
+ (match_operand:SI 1 "const_int_operand")
+ (match_operand:SI 2 "const_int_operand"))
(const_int 0)))]
"ix86_match_ccmode (insn, CCNOmode)
&& INTVAL (operands[1]) > 0
"#")
(define_split
- [(set (match_operand 0 "flags_reg_operand" "")
+ [(set (match_operand 0 "flags_reg_operand")
(match_operator 1 "compare_operator"
[(zero_extract
- (match_operand 2 "nonimmediate_operand" "")
- (match_operand 3 "const_int_operand" "")
- (match_operand 4 "const_int_operand" ""))
+ (match_operand 2 "nonimmediate_operand")
+ (match_operand 3 "const_int_operand")
+ (match_operand 4 "const_int_operand"))
(const_int 0)]))]
"ix86_match_ccmode (insn, CCNOmode)"
[(set (match_dup 0) (match_op_dup 1 [(match_dup 2) (const_int 0)]))]
;; Do the conversion only post-reload to avoid limiting of the register class
;; to QI regs.
(define_split
- [(set (match_operand 0 "flags_reg_operand" "")
+ [(set (match_operand 0 "flags_reg_operand")
(match_operator 1 "compare_operator"
- [(and (match_operand 2 "register_operand" "")
- (match_operand 3 "const_int_operand" ""))
+ [(and (match_operand 2 "register_operand")
+ (match_operand 3 "const_int_operand"))
(const_int 0)]))]
"reload_completed
&& QI_REG_P (operands[2])
})
(define_split
- [(set (match_operand 0 "flags_reg_operand" "")
+ [(set (match_operand 0 "flags_reg_operand")
(match_operator 1 "compare_operator"
- [(and (match_operand 2 "nonimmediate_operand" "")
- (match_operand 3 "const_int_operand" ""))
+ [(and (match_operand 2 "nonimmediate_operand")
+ (match_operand 3 "const_int_operand"))
(const_int 0)]))]
"reload_completed
&& GET_MODE (operands[2]) != QImode
;; it should be done with splitters.
(define_expand "and<mode>3"
- [(set (match_operand:SWIM 0 "nonimmediate_operand" "")
- (and:SWIM (match_operand:SWIM 1 "nonimmediate_operand" "")
- (match_operand:SWIM 2 "<general_szext_operand>" "")))]
+ [(set (match_operand:SWIM 0 "nonimmediate_operand")
+ (and:SWIM (match_operand:SWIM 1 "nonimmediate_operand")
+ (match_operand:SWIM 2 "<general_szext_operand>")))]
""
"ix86_expand_binary_operator (AND, <MODE>mode, operands); DONE;")
(if_then_else
(and (eq_attr "type" "imovx")
(and (match_test "INTVAL (operands[2]) == 0xff")
- (match_operand 1 "ext_QIreg_operand" "")))
+ (match_operand 1 "ext_QIreg_operand")))
(const_string "1")
(const_string "*")))
(set_attr "mode" "SI,DI,DI,SI")])
(if_then_else
(and (eq_attr "type" "imovx")
(and (match_test "INTVAL (operands[2]) == 0xff")
- (match_operand 1 "ext_QIreg_operand" "")))
+ (match_operand 1 "ext_QIreg_operand")))
(const_string "1")
(const_string "*")))
(set_attr "length_immediate" "*,*,0")
(set (attr "prefix_rex")
(if_then_else
(and (eq_attr "type" "imovx")
- (match_operand 1 "ext_QIreg_operand" ""))
+ (match_operand 1 "ext_QIreg_operand"))
(const_string "1")
(const_string "*")))
(set_attr "mode" "HI,HI,SI")])
(set_attr "mode" "QI")])
(define_split
- [(set (match_operand:SWI248 0 "register_operand" "")
- (and:SWI248 (match_operand:SWI248 1 "nonimmediate_operand" "")
- (match_operand:SWI248 2 "const_int_operand" "")))
+ [(set (match_operand:SWI248 0 "register_operand")
+ (and:SWI248 (match_operand:SWI248 1 "nonimmediate_operand")
+ (match_operand:SWI248 2 "const_int_operand")))
(clobber (reg:CC FLAGS_REG))]
"reload_completed
&& true_regnum (operands[0]) != true_regnum (operands[1])"
})
(define_split
- [(set (match_operand 0 "register_operand" "")
+ [(set (match_operand 0 "register_operand")
(and (match_dup 0)
(const_int -65536)))
(clobber (reg:CC FLAGS_REG))]
"operands[1] = gen_lowpart (HImode, operands[0]);")
(define_split
- [(set (match_operand 0 "ext_register_operand" "")
+ [(set (match_operand 0 "ext_register_operand")
(and (match_dup 0)
(const_int -256)))
(clobber (reg:CC FLAGS_REG))]
"operands[1] = gen_lowpart (QImode, operands[0]);")
(define_split
- [(set (match_operand 0 "ext_register_operand" "")
+ [(set (match_operand 0 "ext_register_operand")
(and (match_dup 0)
(const_int -65281)))
(clobber (reg:CC FLAGS_REG))]
;; of memory mismatch stalls. We may want to do the splitting for optimizing
;; for size, but that can (should?) be handled by generic code instead.
(define_split
- [(set (match_operand 0 "register_operand" "")
- (and (match_operand 1 "register_operand" "")
- (match_operand 2 "const_int_operand" "")))
+ [(set (match_operand 0 "register_operand")
+ (and (match_operand 1 "register_operand")
+ (match_operand 2 "const_int_operand")))
(clobber (reg:CC FLAGS_REG))]
"reload_completed
&& QI_REG_P (operands[0])
;; Since AND can be encoded with sign extended immediate, this is only
;; profitable when 7th bit is not set.
(define_split
- [(set (match_operand 0 "register_operand" "")
- (and (match_operand 1 "general_operand" "")
- (match_operand 2 "const_int_operand" "")))
+ [(set (match_operand 0 "register_operand")
+ (and (match_operand 1 "general_operand")
+ (match_operand 2 "const_int_operand")))
(clobber (reg:CC FLAGS_REG))]
"reload_completed
&& ANY_QI_REG_P (operands[0])
;; If this is considered useful, it should be done with splitters.
(define_expand "<code><mode>3"
- [(set (match_operand:SWIM 0 "nonimmediate_operand" "")
- (any_or:SWIM (match_operand:SWIM 1 "nonimmediate_operand" "")
- (match_operand:SWIM 2 "<general_operand>" "")))]
+ [(set (match_operand:SWIM 0 "nonimmediate_operand")
+ (any_or:SWIM (match_operand:SWIM 1 "nonimmediate_operand")
+ (match_operand:SWIM 2 "<general_operand>")))]
""
"ix86_expand_binary_operator (<CODE>, <MODE>mode, operands); DONE;")
(set_attr "mode" "QI")])
(define_split
- [(set (match_operand 0 "register_operand" "")
- (any_or (match_operand 1 "register_operand" "")
- (match_operand 2 "const_int_operand" "")))
+ [(set (match_operand 0 "register_operand")
+ (any_or (match_operand 1 "register_operand")
+ (match_operand 2 "const_int_operand")))
(clobber (reg:CC FLAGS_REG))]
"reload_completed
&& QI_REG_P (operands[0])
;; Since OR can be encoded with sign extended immediate, this is only
;; profitable when 7th bit is set.
(define_split
- [(set (match_operand 0 "register_operand" "")
- (any_or (match_operand 1 "general_operand" "")
- (match_operand 2 "const_int_operand" "")))
+ [(set (match_operand 0 "register_operand")
+ (any_or (match_operand 1 "general_operand")
+ (match_operand 2 "const_int_operand")))
(clobber (reg:CC FLAGS_REG))]
"reload_completed
&& ANY_QI_REG_P (operands[0])
(compare:CCNO
(xor:SI
(zero_extract:SI
- (match_operand 1 "ext_register_operand" "")
+ (match_operand 1 "ext_register_operand")
(const_int 8)
(const_int 8))
- (match_operand:QI 2 "general_operand" ""))
+ (match_operand:QI 2 "general_operand"))
(const_int 0)))
- (set (zero_extract:SI (match_operand 0 "ext_register_operand" "")
+ (set (zero_extract:SI (match_operand 0 "ext_register_operand")
(const_int 8)
(const_int 8))
(xor:SI
;; Negation instructions
(define_expand "neg<mode>2"
- [(set (match_operand:SDWIM 0 "nonimmediate_operand" "")
- (neg:SDWIM (match_operand:SDWIM 1 "nonimmediate_operand" "")))]
+ [(set (match_operand:SDWIM 0 "nonimmediate_operand")
+ (neg:SDWIM (match_operand:SDWIM 1 "nonimmediate_operand")))]
""
"ix86_expand_unary_operator (NEG, <MODE>mode, operands); DONE;")
;; Changing of sign for FP values is doable using integer unit too.
(define_expand "<code><mode>2"
- [(set (match_operand:X87MODEF 0 "register_operand" "")
- (absneg:X87MODEF (match_operand:X87MODEF 1 "register_operand" "")))]
+ [(set (match_operand:X87MODEF 0 "register_operand")
+ (absneg:X87MODEF (match_operand:X87MODEF 1 "register_operand")))]
"TARGET_80387 || (SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH)"
"ix86_expand_fp_absneg_operator (<CODE>, <MODE>mode, operands); DONE;")
[(set (match_operand:X87MODEF 0 "register_operand" "=f,!r")
(match_operator:X87MODEF 3 "absneg_operator"
[(match_operand:X87MODEF 1 "register_operand" "0,0")]))
- (use (match_operand 2 "" ""))
+ (use (match_operand 2))
(clobber (reg:CC FLAGS_REG))]
"TARGET_80387 && !(SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH)"
"#")
(define_expand "<code>tf2"
- [(set (match_operand:TF 0 "register_operand" "")
- (absneg:TF (match_operand:TF 1 "register_operand" "")))]
+ [(set (match_operand:TF 0 "register_operand")
+ (absneg:TF (match_operand:TF 1 "register_operand")))]
"TARGET_SSE2"
"ix86_expand_fp_absneg_operator (<CODE>, TFmode, operands); DONE;")
;; Splitters for fp abs and neg.
(define_split
- [(set (match_operand 0 "fp_register_operand" "")
+ [(set (match_operand 0 "fp_register_operand")
(match_operator 1 "absneg_operator" [(match_dup 0)]))
- (use (match_operand 2 "" ""))
+ (use (match_operand 2))
(clobber (reg:CC FLAGS_REG))]
"reload_completed"
[(set (match_dup 0) (match_op_dup 1 [(match_dup 0)]))])
(define_split
- [(set (match_operand 0 "register_operand" "")
+ [(set (match_operand 0 "register_operand")
(match_operator 3 "absneg_operator"
- [(match_operand 1 "register_operand" "")]))
- (use (match_operand 2 "nonimmediate_operand" ""))
+ [(match_operand 1 "register_operand")]))
+ (use (match_operand 2 "nonimmediate_operand"))
(clobber (reg:CC FLAGS_REG))]
"reload_completed && SSE_REG_P (operands[0])"
[(set (match_dup 0) (match_dup 3))]
})
(define_split
- [(set (match_operand:SF 0 "register_operand" "")
+ [(set (match_operand:SF 0 "register_operand")
(match_operator:SF 1 "absneg_operator" [(match_dup 0)]))
- (use (match_operand:V4SF 2 "" ""))
+ (use (match_operand:V4SF 2))
(clobber (reg:CC FLAGS_REG))]
"reload_completed"
[(parallel [(set (match_dup 0) (match_dup 1))
})
(define_split
- [(set (match_operand:DF 0 "register_operand" "")
+ [(set (match_operand:DF 0 "register_operand")
(match_operator:DF 1 "absneg_operator" [(match_dup 0)]))
- (use (match_operand 2 "" ""))
+ (use (match_operand 2))
(clobber (reg:CC FLAGS_REG))]
"reload_completed"
[(parallel [(set (match_dup 0) (match_dup 1))
})
(define_split
- [(set (match_operand:XF 0 "register_operand" "")
+ [(set (match_operand:XF 0 "register_operand")
(match_operator:XF 1 "absneg_operator" [(match_dup 0)]))
- (use (match_operand 2 "" ""))
+ (use (match_operand 2))
(clobber (reg:CC FLAGS_REG))]
"reload_completed"
[(parallel [(set (match_dup 0) (match_dup 1))
(define_mode_attr CSGNVMODE [(SF "V4SF") (DF "V2DF") (TF "TF")])
(define_expand "copysign<mode>3"
- [(match_operand:CSGNMODE 0 "register_operand" "")
- (match_operand:CSGNMODE 1 "nonmemory_operand" "")
- (match_operand:CSGNMODE 2 "register_operand" "")]
+ [(match_operand:CSGNMODE 0 "register_operand")
+ (match_operand:CSGNMODE 1 "nonmemory_operand")
+ (match_operand:CSGNMODE 2 "register_operand")]
"(SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH)
|| (TARGET_SSE2 && (<MODE>mode == TFmode))"
"ix86_expand_copysign (operands); DONE;")
"#")
(define_split
- [(set (match_operand:CSGNMODE 0 "register_operand" "")
+ [(set (match_operand:CSGNMODE 0 "register_operand")
(unspec:CSGNMODE
- [(match_operand:CSGNMODE 2 "register_operand" "")
- (match_operand:CSGNMODE 3 "register_operand" "")
- (match_operand:<CSGNVMODE> 4 "" "")
- (match_operand:<CSGNVMODE> 5 "" "")]
+ [(match_operand:CSGNMODE 2 "register_operand")
+ (match_operand:CSGNMODE 3 "register_operand")
+ (match_operand:<CSGNVMODE> 4)
+ (match_operand:<CSGNVMODE> 5)]
UNSPEC_COPYSIGN))
- (clobber (match_scratch:<CSGNVMODE> 1 ""))]
+ (clobber (match_scratch:<CSGNVMODE> 1))]
"((SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH)
|| (TARGET_SSE2 && (<MODE>mode == TFmode)))
&& reload_completed"
;; One complement instructions
(define_expand "one_cmpl<mode>2"
- [(set (match_operand:SWIM 0 "nonimmediate_operand" "")
- (not:SWIM (match_operand:SWIM 1 "nonimmediate_operand" "")))]
+ [(set (match_operand:SWIM 0 "nonimmediate_operand")
+ (not:SWIM (match_operand:SWIM 1 "nonimmediate_operand")))]
""
"ix86_expand_unary_operator (NOT, <MODE>mode, operands); DONE;")
(set_attr "mode" "<MODE>")])
(define_split
- [(set (match_operand 0 "flags_reg_operand" "")
+ [(set (match_operand 0 "flags_reg_operand")
(match_operator 2 "compare_operator"
- [(not:SWI (match_operand:SWI 3 "nonimmediate_operand" ""))
+ [(not:SWI (match_operand:SWI 3 "nonimmediate_operand"))
(const_int 0)]))
- (set (match_operand:SWI 1 "nonimmediate_operand" "")
+ (set (match_operand:SWI 1 "nonimmediate_operand")
(not:SWI (match_dup 3)))]
"ix86_match_ccmode (insn, CCNOmode)"
[(parallel [(set (match_dup 0)
(set_attr "mode" "SI")])
(define_split
- [(set (match_operand 0 "flags_reg_operand" "")
+ [(set (match_operand 0 "flags_reg_operand")
(match_operator 2 "compare_operator"
- [(not:SI (match_operand:SI 3 "register_operand" ""))
+ [(not:SI (match_operand:SI 3 "register_operand"))
(const_int 0)]))
- (set (match_operand:DI 1 "register_operand" "")
+ (set (match_operand:DI 1 "register_operand")
(zero_extend:DI (not:SI (match_dup 3))))]
"ix86_match_ccmode (insn, CCNOmode)"
[(parallel [(set (match_dup 0)
;; than 31.
(define_expand "ashl<mode>3"
- [(set (match_operand:SDWIM 0 "<shift_operand>" "")
- (ashift:SDWIM (match_operand:SDWIM 1 "<ashl_input_operand>" "")
- (match_operand:QI 2 "nonmemory_operand" "")))]
+ [(set (match_operand:SDWIM 0 "<shift_operand>")
+ (ashift:SDWIM (match_operand:SDWIM 1 "<ashl_input_operand>")
+ (match_operand:QI 2 "nonmemory_operand")))]
""
"ix86_expand_binary_operator (ASHIFT, <MODE>mode, operands); DONE;")
[(set_attr "type" "multi")])
(define_split
- [(set (match_operand:DWI 0 "register_operand" "")
- (ashift:DWI (match_operand:DWI 1 "nonmemory_operand" "")
- (match_operand:QI 2 "nonmemory_operand" "")))
+ [(set (match_operand:DWI 0 "register_operand")
+ (ashift:DWI (match_operand:DWI 1 "nonmemory_operand")
+ (match_operand:QI 2 "nonmemory_operand")))
(clobber (reg:CC FLAGS_REG))]
"(optimize && flag_peephole2) ? epilogue_completed : reload_completed"
[(const_int 0)]
(define_peephole2
[(match_scratch:DWIH 3 "r")
- (parallel [(set (match_operand:<DWI> 0 "register_operand" "")
+ (parallel [(set (match_operand:<DWI> 0 "register_operand")
(ashift:<DWI>
- (match_operand:<DWI> 1 "nonmemory_operand" "")
- (match_operand:QI 2 "nonmemory_operand" "")))
+ (match_operand:<DWI> 1 "nonmemory_operand")
+ (match_operand:QI 2 "nonmemory_operand")))
(clobber (reg:CC FLAGS_REG))])
(match_dup 3)]
"TARGET_CMOVE"
(define_expand "x86_shift<mode>_adj_1"
[(set (reg:CCZ FLAGS_REG)
- (compare:CCZ (and:QI (match_operand:QI 2 "register_operand" "")
+ (compare:CCZ (and:QI (match_operand:QI 2 "register_operand")
(match_dup 4))
(const_int 0)))
- (set (match_operand:SWI48 0 "register_operand" "")
+ (set (match_operand:SWI48 0 "register_operand")
(if_then_else:SWI48 (ne (reg:CCZ FLAGS_REG) (const_int 0))
- (match_operand:SWI48 1 "register_operand" "")
+ (match_operand:SWI48 1 "register_operand")
(match_dup 0)))
(set (match_dup 1)
(if_then_else:SWI48 (ne (reg:CCZ FLAGS_REG) (const_int 0))
- (match_operand:SWI48 3 "register_operand" "")
+ (match_operand:SWI48 3 "register_operand")
(match_dup 1)))]
"TARGET_CMOVE"
"operands[4] = GEN_INT (GET_MODE_BITSIZE (<MODE>mode));")
(define_expand "x86_shift<mode>_adj_2"
- [(use (match_operand:SWI48 0 "register_operand" ""))
- (use (match_operand:SWI48 1 "register_operand" ""))
- (use (match_operand:QI 2 "register_operand" ""))]
+ [(use (match_operand:SWI48 0 "register_operand"))
+ (use (match_operand:SWI48 1 "register_operand"))
+ (use (match_operand:QI 2 "register_operand"))]
""
{
rtx label = gen_label_rtx ();
(eq_attr "alternative" "2")
(const_string "ishiftx")
(and (and (match_test "TARGET_DOUBLE_WITH_ADD")
- (match_operand 0 "register_operand" ""))
- (match_operand 2 "const1_operand" ""))
+ (match_operand 0 "register_operand"))
+ (match_operand 2 "const1_operand"))
(const_string "alu")
]
(const_string "ishift")))
(if_then_else
(ior (eq_attr "type" "alu")
(and (eq_attr "type" "ishift")
- (and (match_operand 2 "const1_operand" "")
+ (and (match_operand 2 "const1_operand")
(ior (match_test "TARGET_SHIFT1")
(match_test "optimize_function_for_size_p (cfun)")))))
(const_string "0")
;; Convert shift to the shiftx pattern to avoid flags dependency.
(define_split
- [(set (match_operand:SWI48 0 "register_operand" "")
- (ashift:SWI48 (match_operand:SWI48 1 "nonimmediate_operand" "")
- (match_operand:QI 2 "register_operand" "")))
+ [(set (match_operand:SWI48 0 "register_operand")
+ (ashift:SWI48 (match_operand:SWI48 1 "nonimmediate_operand")
+ (match_operand:QI 2 "register_operand")))
(clobber (reg:CC FLAGS_REG))]
"TARGET_BMI2 && reload_completed"
[(set (match_dup 0)
(eq_attr "alternative" "2")
(const_string "ishiftx")
(and (match_test "TARGET_DOUBLE_WITH_ADD")
- (match_operand 2 "const1_operand" ""))
+ (match_operand 2 "const1_operand"))
(const_string "alu")
]
(const_string "ishift")))
(if_then_else
(ior (eq_attr "type" "alu")
(and (eq_attr "type" "ishift")
- (and (match_operand 2 "const1_operand" "")
+ (and (match_operand 2 "const1_operand")
(ior (match_test "TARGET_SHIFT1")
(match_test "optimize_function_for_size_p (cfun)")))))
(const_string "0")
;; Convert shift to the shiftx pattern to avoid flags dependency.
(define_split
- [(set (match_operand:DI 0 "register_operand" "")
+ [(set (match_operand:DI 0 "register_operand")
(zero_extend:DI
- (ashift:SI (match_operand:SI 1 "nonimmediate_operand" "")
- (match_operand:QI 2 "register_operand" ""))))
+ (ashift:SI (match_operand:SI 1 "nonimmediate_operand")
+ (match_operand:QI 2 "register_operand"))))
(clobber (reg:CC FLAGS_REG))]
"TARGET_64BIT && TARGET_BMI2 && reload_completed"
[(set (match_dup 0)
(cond [(eq_attr "alternative" "1")
(const_string "lea")
(and (and (match_test "TARGET_DOUBLE_WITH_ADD")
- (match_operand 0 "register_operand" ""))
- (match_operand 2 "const1_operand" ""))
+ (match_operand 0 "register_operand"))
+ (match_operand 2 "const1_operand"))
(const_string "alu")
]
(const_string "ishift")))
(if_then_else
(ior (eq_attr "type" "alu")
(and (eq_attr "type" "ishift")
- (and (match_operand 2 "const1_operand" "")
+ (and (match_operand 2 "const1_operand")
(ior (match_test "TARGET_SHIFT1")
(match_test "optimize_function_for_size_p (cfun)")))))
(const_string "0")
(cond [(eq_attr "alternative" "2")
(const_string "lea")
(and (and (match_test "TARGET_DOUBLE_WITH_ADD")
- (match_operand 0 "register_operand" ""))
- (match_operand 2 "const1_operand" ""))
+ (match_operand 0 "register_operand"))
+ (match_operand 2 "const1_operand"))
(const_string "alu")
]
(const_string "ishift")))
(if_then_else
(ior (eq_attr "type" "alu")
(and (eq_attr "type" "ishift")
- (and (match_operand 2 "const1_operand" "")
+ (and (match_operand 2 "const1_operand")
(ior (match_test "TARGET_SHIFT1")
(match_test "optimize_function_for_size_p (cfun)")))))
(const_string "0")
}
[(set (attr "type")
(cond [(and (and (match_test "TARGET_DOUBLE_WITH_ADD")
- (match_operand 0 "register_operand" ""))
- (match_operand 1 "const1_operand" ""))
+ (match_operand 0 "register_operand"))
+ (match_operand 1 "const1_operand"))
(const_string "alu")
]
(const_string "ishift1")))
(if_then_else
(ior (eq_attr "type" "alu")
(and (eq_attr "type" "ishift1")
- (and (match_operand 1 "const1_operand" "")
+ (and (match_operand 1 "const1_operand")
(ior (match_test "TARGET_SHIFT1")
(match_test "optimize_function_for_size_p (cfun)")))))
(const_string "0")
;; Convert ashift to the lea pattern to avoid flags dependency.
(define_split
- [(set (match_operand 0 "register_operand" "")
- (ashift (match_operand 1 "index_register_operand" "")
- (match_operand:QI 2 "const_int_operand" "")))
+ [(set (match_operand 0 "register_operand")
+ (ashift (match_operand 1 "index_register_operand")
+ (match_operand:QI 2 "const_int_operand")))
(clobber (reg:CC FLAGS_REG))]
"GET_MODE (operands[0]) == GET_MODE (operands[1])
&& reload_completed
;; Convert ashift to the lea pattern to avoid flags dependency.
(define_split
- [(set (match_operand:DI 0 "register_operand" "")
+ [(set (match_operand:DI 0 "register_operand")
(zero_extend:DI
- (ashift:SI (match_operand:SI 1 "index_register_operand" "")
- (match_operand:QI 2 "const_int_operand" ""))))
+ (ashift:SI (match_operand:SI 1 "index_register_operand")
+ (match_operand:QI 2 "const_int_operand"))))
(clobber (reg:CC FLAGS_REG))]
"TARGET_64BIT && reload_completed
&& true_regnum (operands[0]) != true_regnum (operands[1])"
}
[(set (attr "type")
(cond [(and (and (match_test "TARGET_DOUBLE_WITH_ADD")
- (match_operand 0 "register_operand" ""))
- (match_operand 2 "const1_operand" ""))
+ (match_operand 0 "register_operand"))
+ (match_operand 2 "const1_operand"))
(const_string "alu")
]
(const_string "ishift")))
(if_then_else
(ior (eq_attr "type" "alu")
(and (eq_attr "type" "ishift")
- (and (match_operand 2 "const1_operand" "")
+ (and (match_operand 2 "const1_operand")
(ior (match_test "TARGET_SHIFT1")
(match_test "optimize_function_for_size_p (cfun)")))))
(const_string "0")
}
[(set (attr "type")
(cond [(and (match_test "TARGET_DOUBLE_WITH_ADD")
- (match_operand 2 "const1_operand" ""))
+ (match_operand 2 "const1_operand"))
(const_string "alu")
]
(const_string "ishift")))
(if_then_else
(ior (eq_attr "type" "alu")
(and (eq_attr "type" "ishift")
- (and (match_operand 2 "const1_operand" "")
+ (and (match_operand 2 "const1_operand")
(ior (match_test "TARGET_SHIFT1")
(match_test "optimize_function_for_size_p (cfun)")))))
(const_string "0")
}
[(set (attr "type")
(cond [(and (and (match_test "TARGET_DOUBLE_WITH_ADD")
- (match_operand 0 "register_operand" ""))
- (match_operand 2 "const1_operand" ""))
+ (match_operand 0 "register_operand"))
+ (match_operand 2 "const1_operand"))
(const_string "alu")
]
(const_string "ishift")))
(if_then_else
(ior (eq_attr "type" "alu")
(and (eq_attr "type" "ishift")
- (and (match_operand 2 "const1_operand" "")
+ (and (match_operand 2 "const1_operand")
(ior (match_test "TARGET_SHIFT1")
(match_test "optimize_function_for_size_p (cfun)")))))
(const_string "0")
;; See comment above `ashl<mode>3' about how this works.
(define_expand "<shift_insn><mode>3"
- [(set (match_operand:SDWIM 0 "<shift_operand>" "")
- (any_shiftrt:SDWIM (match_operand:SDWIM 1 "<shift_operand>" "")
- (match_operand:QI 2 "nonmemory_operand" "")))]
+ [(set (match_operand:SDWIM 0 "<shift_operand>")
+ (any_shiftrt:SDWIM (match_operand:SDWIM 1 "<shift_operand>")
+ (match_operand:QI 2 "nonmemory_operand")))]
""
"ix86_expand_binary_operator (<CODE>, <MODE>mode, operands); DONE;")
(define_peephole2
[(match_scratch:DWIH 3 "r")
- (parallel [(set (match_operand:<DWI> 0 "register_operand" "")
+ (parallel [(set (match_operand:<DWI> 0 "register_operand")
(any_shiftrt:<DWI>
- (match_operand:<DWI> 1 "register_operand" "")
- (match_operand:QI 2 "nonmemory_operand" "")))
+ (match_operand:<DWI> 1 "register_operand")
+ (match_operand:QI 2 "nonmemory_operand")))
(clobber (reg:CC FLAGS_REG))])
(match_dup 3)]
"TARGET_CMOVE"
(define_insn "ashrdi3_cvt"
[(set (match_operand:DI 0 "nonimmediate_operand" "=*d,rm")
(ashiftrt:DI (match_operand:DI 1 "nonimmediate_operand" "*a,0")
- (match_operand:QI 2 "const_int_operand" "")))
+ (match_operand:QI 2 "const_int_operand")))
(clobber (reg:CC FLAGS_REG))]
"TARGET_64BIT && INTVAL (operands[2]) == 63
&& (TARGET_USE_CLTD || optimize_function_for_size_p (cfun))
(define_insn "ashrsi3_cvt"
[(set (match_operand:SI 0 "nonimmediate_operand" "=*d,rm")
(ashiftrt:SI (match_operand:SI 1 "nonimmediate_operand" "*a,0")
- (match_operand:QI 2 "const_int_operand" "")))
+ (match_operand:QI 2 "const_int_operand")))
(clobber (reg:CC FLAGS_REG))]
"INTVAL (operands[2]) == 31
&& (TARGET_USE_CLTD || optimize_function_for_size_p (cfun))
[(set (match_operand:DI 0 "register_operand" "=*d,r")
(zero_extend:DI
(ashiftrt:SI (match_operand:SI 1 "register_operand" "*a,0")
- (match_operand:QI 2 "const_int_operand" ""))))
+ (match_operand:QI 2 "const_int_operand"))))
(clobber (reg:CC FLAGS_REG))]
"TARGET_64BIT && INTVAL (operands[2]) == 31
&& (TARGET_USE_CLTD || optimize_function_for_size_p (cfun))
(set_attr "mode" "SI")])
(define_expand "x86_shift<mode>_adj_3"
- [(use (match_operand:SWI48 0 "register_operand" ""))
- (use (match_operand:SWI48 1 "register_operand" ""))
- (use (match_operand:QI 2 "register_operand" ""))]
+ [(use (match_operand:SWI48 0 "register_operand"))
+ (use (match_operand:SWI48 1 "register_operand"))
+ (use (match_operand:QI 2 "register_operand"))]
""
{
rtx label = gen_label_rtx ();
(set_attr "type" "ishift,ishiftx")
(set (attr "length_immediate")
(if_then_else
- (and (match_operand 2 "const1_operand" "")
+ (and (match_operand 2 "const1_operand")
(ior (match_test "TARGET_SHIFT1")
(match_test "optimize_function_for_size_p (cfun)")))
(const_string "0")
;; Convert shift to the shiftx pattern to avoid flags dependency.
(define_split
- [(set (match_operand:SWI48 0 "register_operand" "")
- (any_shiftrt:SWI48 (match_operand:SWI48 1 "nonimmediate_operand" "")
- (match_operand:QI 2 "register_operand" "")))
+ [(set (match_operand:SWI48 0 "register_operand")
+ (any_shiftrt:SWI48 (match_operand:SWI48 1 "nonimmediate_operand")
+ (match_operand:QI 2 "register_operand")))
(clobber (reg:CC FLAGS_REG))]
"TARGET_BMI2 && reload_completed"
[(set (match_dup 0)
(set_attr "type" "ishift,ishiftx")
(set (attr "length_immediate")
(if_then_else
- (and (match_operand 2 "const1_operand" "")
+ (and (match_operand 2 "const1_operand")
(ior (match_test "TARGET_SHIFT1")
(match_test "optimize_function_for_size_p (cfun)")))
(const_string "0")
;; Convert shift to the shiftx pattern to avoid flags dependency.
(define_split
- [(set (match_operand:DI 0 "register_operand" "")
+ [(set (match_operand:DI 0 "register_operand")
(zero_extend:DI
- (any_shiftrt:SI (match_operand:SI 1 "nonimmediate_operand" "")
- (match_operand:QI 2 "register_operand" ""))))
+ (any_shiftrt:SI (match_operand:SI 1 "nonimmediate_operand")
+ (match_operand:QI 2 "register_operand"))))
(clobber (reg:CC FLAGS_REG))]
"TARGET_64BIT && TARGET_BMI2 && reload_completed"
[(set (match_dup 0)
[(set_attr "type" "ishift")
(set (attr "length_immediate")
(if_then_else
- (and (match_operand 2 "const1_operand" "")
+ (and (match_operand 2 "const1_operand")
(ior (match_test "TARGET_SHIFT1")
(match_test "optimize_function_for_size_p (cfun)")))
(const_string "0")
[(set_attr "type" "ishift1")
(set (attr "length_immediate")
(if_then_else
- (and (match_operand 1 "const1_operand" "")
+ (and (match_operand 1 "const1_operand")
(ior (match_test "TARGET_SHIFT1")
(match_test "optimize_function_for_size_p (cfun)")))
(const_string "0")
[(set_attr "type" "ishift")
(set (attr "length_immediate")
(if_then_else
- (and (match_operand 2 "const1_operand" "")
+ (and (match_operand 2 "const1_operand")
(ior (match_test "TARGET_SHIFT1")
(match_test "optimize_function_for_size_p (cfun)")))
(const_string "0")
[(set_attr "type" "ishift")
(set (attr "length_immediate")
(if_then_else
- (and (match_operand 2 "const1_operand" "")
+ (and (match_operand 2 "const1_operand")
(ior (match_test "TARGET_SHIFT1")
(match_test "optimize_function_for_size_p (cfun)")))
(const_string "0")
[(set_attr "type" "ishift")
(set (attr "length_immediate")
(if_then_else
- (and (match_operand 2 "const1_operand" "")
+ (and (match_operand 2 "const1_operand")
(ior (match_test "TARGET_SHIFT1")
(match_test "optimize_function_for_size_p (cfun)")))
(const_string "0")
;; Rotate instructions
(define_expand "<rotate_insn>ti3"
- [(set (match_operand:TI 0 "register_operand" "")
- (any_rotate:TI (match_operand:TI 1 "register_operand" "")
- (match_operand:QI 2 "nonmemory_operand" "")))]
+ [(set (match_operand:TI 0 "register_operand")
+ (any_rotate:TI (match_operand:TI 1 "register_operand")
+ (match_operand:QI 2 "nonmemory_operand")))]
"TARGET_64BIT"
{
if (const_1_to_63_operand (operands[2], VOIDmode))
})
(define_expand "<rotate_insn>di3"
- [(set (match_operand:DI 0 "shiftdi_operand" "")
- (any_rotate:DI (match_operand:DI 1 "shiftdi_operand" "")
- (match_operand:QI 2 "nonmemory_operand" "")))]
+ [(set (match_operand:DI 0 "shiftdi_operand")
+ (any_rotate:DI (match_operand:DI 1 "shiftdi_operand")
+ (match_operand:QI 2 "nonmemory_operand")))]
""
{
if (TARGET_64BIT)
})
(define_expand "<rotate_insn><mode>3"
- [(set (match_operand:SWIM124 0 "nonimmediate_operand" "")
- (any_rotate:SWIM124 (match_operand:SWIM124 1 "nonimmediate_operand" "")
- (match_operand:QI 2 "nonmemory_operand" "")))]
+ [(set (match_operand:SWIM124 0 "nonimmediate_operand")
+ (any_rotate:SWIM124 (match_operand:SWIM124 1 "nonimmediate_operand")
+ (match_operand:QI 2 "nonmemory_operand")))]
""
"ix86_expand_binary_operator (<CODE>, <MODE>mode, operands); DONE;")
(set (attr "length_immediate")
(if_then_else
(and (eq_attr "type" "rotate")
- (and (match_operand 2 "const1_operand" "")
+ (and (match_operand 2 "const1_operand")
(ior (match_test "TARGET_SHIFT1")
(match_test "optimize_function_for_size_p (cfun)"))))
(const_string "0")
;; Convert rotate to the rotatex pattern to avoid flags dependency.
(define_split
- [(set (match_operand:SWI48 0 "register_operand" "")
- (rotate:SWI48 (match_operand:SWI48 1 "nonimmediate_operand" "")
- (match_operand:QI 2 "immediate_operand" "")))
+ [(set (match_operand:SWI48 0 "register_operand")
+ (rotate:SWI48 (match_operand:SWI48 1 "nonimmediate_operand")
+ (match_operand:QI 2 "immediate_operand")))
(clobber (reg:CC FLAGS_REG))]
"TARGET_BMI2 && reload_completed"
[(set (match_dup 0)
})
(define_split
- [(set (match_operand:SWI48 0 "register_operand" "")
- (rotatert:SWI48 (match_operand:SWI48 1 "nonimmediate_operand" "")
- (match_operand:QI 2 "immediate_operand" "")))
+ [(set (match_operand:SWI48 0 "register_operand")
+ (rotatert:SWI48 (match_operand:SWI48 1 "nonimmediate_operand")
+ (match_operand:QI 2 "immediate_operand")))
(clobber (reg:CC FLAGS_REG))]
"TARGET_BMI2 && reload_completed"
[(set (match_dup 0)
(set (attr "length_immediate")
(if_then_else
(and (eq_attr "type" "rotate")
- (and (match_operand 2 "const1_operand" "")
+ (and (match_operand 2 "const1_operand")
(ior (match_test "TARGET_SHIFT1")
(match_test "optimize_function_for_size_p (cfun)"))))
(const_string "0")
;; Convert rotate to the rotatex pattern to avoid flags dependency.
(define_split
- [(set (match_operand:DI 0 "register_operand" "")
+ [(set (match_operand:DI 0 "register_operand")
(zero_extend:DI
- (rotate:SI (match_operand:SI 1 "nonimmediate_operand" "")
- (match_operand:QI 2 "immediate_operand" ""))))
+ (rotate:SI (match_operand:SI 1 "nonimmediate_operand")
+ (match_operand:QI 2 "immediate_operand"))))
(clobber (reg:CC FLAGS_REG))]
"TARGET_64BIT && TARGET_BMI2 && reload_completed"
[(set (match_dup 0)
})
(define_split
- [(set (match_operand:DI 0 "register_operand" "")
+ [(set (match_operand:DI 0 "register_operand")
(zero_extend:DI
- (rotatert:SI (match_operand:SI 1 "nonimmediate_operand" "")
- (match_operand:QI 2 "immediate_operand" ""))))
+ (rotatert:SI (match_operand:SI 1 "nonimmediate_operand")
+ (match_operand:QI 2 "immediate_operand"))))
(clobber (reg:CC FLAGS_REG))]
"TARGET_64BIT && TARGET_BMI2 && reload_completed"
[(set (match_dup 0)
[(set_attr "type" "rotate")
(set (attr "length_immediate")
(if_then_else
- (and (match_operand 2 "const1_operand" "")
+ (and (match_operand 2 "const1_operand")
(ior (match_test "TARGET_SHIFT1")
(match_test "optimize_function_for_size_p (cfun)")))
(const_string "0")
[(set_attr "type" "rotate1")
(set (attr "length_immediate")
(if_then_else
- (and (match_operand 1 "const1_operand" "")
+ (and (match_operand 1 "const1_operand")
(ior (match_test "TARGET_SHIFT1")
(match_test "optimize_function_for_size_p (cfun)")))
(const_string "0")
(set_attr "mode" "QI")])
(define_split
- [(set (match_operand:HI 0 "register_operand" "")
+ [(set (match_operand:HI 0 "register_operand")
(any_rotate:HI (match_dup 0) (const_int 8)))
(clobber (reg:CC FLAGS_REG))]
"reload_completed
;; Bit set / bit test instructions
(define_expand "extv"
- [(set (match_operand:SI 0 "register_operand" "")
- (sign_extract:SI (match_operand:SI 1 "register_operand" "")
- (match_operand:SI 2 "const8_operand" "")
- (match_operand:SI 3 "const8_operand" "")))]
+ [(set (match_operand:SI 0 "register_operand")
+ (sign_extract:SI (match_operand:SI 1 "register_operand")
+ (match_operand:SI 2 "const8_operand")
+ (match_operand:SI 3 "const8_operand")))]
""
{
/* Handle extractions from %ah et al. */
})
(define_expand "extzv"
- [(set (match_operand:SI 0 "register_operand" "")
- (zero_extract:SI (match_operand 1 "ext_register_operand" "")
- (match_operand:SI 2 "const8_operand" "")
- (match_operand:SI 3 "const8_operand" "")))]
+ [(set (match_operand:SI 0 "register_operand")
+ (zero_extract:SI (match_operand 1 "ext_register_operand")
+ (match_operand:SI 2 "const8_operand")
+ (match_operand:SI 3 "const8_operand")))]
""
{
/* Handle extractions from %ah et al. */
})
(define_expand "insv"
- [(set (zero_extract (match_operand 0 "register_operand" "")
- (match_operand 1 "const_int_operand" "")
- (match_operand 2 "const_int_operand" ""))
- (match_operand 3 "register_operand" ""))]
+ [(set (zero_extract (match_operand 0 "register_operand")
+ (match_operand 1 "const_int_operand")
+ (match_operand 2 "const_int_operand"))
+ (match_operand 3 "register_operand"))]
""
{
rtx (*gen_mov_insv_1) (rtx, rtx);
(define_insn "*btsq"
[(set (zero_extract:DI (match_operand:DI 0 "register_operand" "+r")
(const_int 1)
- (match_operand:DI 1 "const_0_to_63_operand" ""))
+ (match_operand:DI 1 "const_0_to_63_operand"))
(const_int 1))
(clobber (reg:CC FLAGS_REG))]
"TARGET_64BIT && (TARGET_USE_BT || reload_completed)"
(define_insn "*btrq"
[(set (zero_extract:DI (match_operand:DI 0 "register_operand" "+r")
(const_int 1)
- (match_operand:DI 1 "const_0_to_63_operand" ""))
+ (match_operand:DI 1 "const_0_to_63_operand"))
(const_int 0))
(clobber (reg:CC FLAGS_REG))]
"TARGET_64BIT && (TARGET_USE_BT || reload_completed)"
(define_insn "*btcq"
[(set (zero_extract:DI (match_operand:DI 0 "register_operand" "+r")
(const_int 1)
- (match_operand:DI 1 "const_0_to_63_operand" ""))
+ (match_operand:DI 1 "const_0_to_63_operand"))
(not:DI (zero_extract:DI (match_dup 0) (const_int 1) (match_dup 1))))
(clobber (reg:CC FLAGS_REG))]
"TARGET_64BIT && (TARGET_USE_BT || reload_completed)"
(define_peephole2
[(match_scratch:DI 2 "r")
(parallel [(set (zero_extract:DI
- (match_operand:DI 0 "register_operand" "")
+ (match_operand:DI 0 "register_operand")
(const_int 1)
- (match_operand:DI 1 "const_0_to_63_operand" ""))
+ (match_operand:DI 1 "const_0_to_63_operand"))
(const_int 1))
(clobber (reg:CC FLAGS_REG))])]
"TARGET_64BIT && !TARGET_USE_BT"
(define_peephole2
[(match_scratch:DI 2 "r")
(parallel [(set (zero_extract:DI
- (match_operand:DI 0 "register_operand" "")
+ (match_operand:DI 0 "register_operand")
(const_int 1)
- (match_operand:DI 1 "const_0_to_63_operand" ""))
+ (match_operand:DI 1 "const_0_to_63_operand"))
(const_int 0))
(clobber (reg:CC FLAGS_REG))])]
"TARGET_64BIT && !TARGET_USE_BT"
(define_peephole2
[(match_scratch:DI 2 "r")
(parallel [(set (zero_extract:DI
- (match_operand:DI 0 "register_operand" "")
+ (match_operand:DI 0 "register_operand")
(const_int 1)
- (match_operand:DI 1 "const_0_to_63_operand" ""))
+ (match_operand:DI 1 "const_0_to_63_operand"))
(not:DI (zero_extract:DI
(match_dup 0) (const_int 1) (match_dup 1))))
(clobber (reg:CC FLAGS_REG))])]
;; sete %al
(define_split
- [(set (match_operand:QI 0 "nonimmediate_operand" "")
+ [(set (match_operand:QI 0 "nonimmediate_operand")
(ne:QI (match_operator 1 "ix86_comparison_operator"
[(reg FLAGS_REG) (const_int 0)])
(const_int 0)))]
"PUT_MODE (operands[1], QImode);")
(define_split
- [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" ""))
+ [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand"))
(ne:QI (match_operator 1 "ix86_comparison_operator"
[(reg FLAGS_REG) (const_int 0)])
(const_int 0)))]
"PUT_MODE (operands[1], QImode);")
(define_split
- [(set (match_operand:QI 0 "nonimmediate_operand" "")
+ [(set (match_operand:QI 0 "nonimmediate_operand")
(eq:QI (match_operator 1 "ix86_comparison_operator"
[(reg FLAGS_REG) (const_int 0)])
(const_int 0)))]
})
(define_split
- [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" ""))
+ [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand"))
(eq:QI (match_operator 1 "ix86_comparison_operator"
[(reg FLAGS_REG) (const_int 0)])
(const_int 0)))]
[(set (pc)
(if_then_else (match_operator 1 "ix86_comparison_operator"
[(reg FLAGS_REG) (const_int 0)])
- (label_ref (match_operand 0 "" ""))
+ (label_ref (match_operand 0))
(pc)))]
""
"%+j%C1\t%l0"
(if_then_else (match_operator 1 "ix86_comparison_operator"
[(reg FLAGS_REG) (const_int 0)])
(pc)
- (label_ref (match_operand 0 "" ""))))]
+ (label_ref (match_operand 0))))]
""
"%+j%c1\t%l0"
[(set_attr "type" "ibr")
(if_then_else (ne (match_operator 0 "ix86_comparison_operator"
[(reg FLAGS_REG) (const_int 0)])
(const_int 0))
- (label_ref (match_operand 1 "" ""))
+ (label_ref (match_operand 1))
(pc)))]
""
[(set (pc)
(if_then_else (eq (match_operator 0 "ix86_comparison_operator"
[(reg FLAGS_REG) (const_int 0)])
(const_int 0))
- (label_ref (match_operand 1 "" ""))
+ (label_ref (match_operand 1))
(pc)))]
""
[(set (pc)
(zero_extend:SI
(match_operand:QI 2 "register_operand" "r")))
(const_int 0)])
- (label_ref (match_operand 3 "" ""))
+ (label_ref (match_operand 3))
(pc)))
(clobber (reg:CC FLAGS_REG))]
"TARGET_USE_BT || optimize_function_for_size_p (cfun)"
(and:SI
(match_operand:SI 2 "register_operand" "r")
(match_operand:SI 3 "const_int_operand" "n")))])
- (label_ref (match_operand 4 "" ""))
+ (label_ref (match_operand 4))
(pc)))
(clobber (reg:CC FLAGS_REG))]
"(TARGET_USE_BT || optimize_function_for_size_p (cfun))
(match_operand:QI 2 "register_operand" "r"))
(const_int 1))
(const_int 0)])
- (label_ref (match_operand 3 "" ""))
+ (label_ref (match_operand 3))
(pc)))
(clobber (reg:CC FLAGS_REG))]
"TARGET_USE_BT || optimize_function_for_size_p (cfun)"
(match_operand:SI 3 "const_int_operand" "n")) 0))
(const_int 1))
(const_int 0)])
- (label_ref (match_operand 4 "" ""))
+ (label_ref (match_operand 4))
(pc)))
(clobber (reg:CC FLAGS_REG))]
"(TARGET_USE_BT || optimize_function_for_size_p (cfun))
(if_then_else (match_operator 0 "ix86_fp_comparison_operator"
[(match_operand 1 "register_operand" "f")
(match_operand 2 "nonimmediate_operand" "fm")])
- (label_ref (match_operand 3 "" ""))
+ (label_ref (match_operand 3))
(pc)))
(clobber (reg:CCFP FPSR_REG))
(clobber (reg:CCFP FLAGS_REG))
[(match_operand 1 "register_operand" "f")
(match_operand 2 "nonimmediate_operand" "fm")])
(pc)
- (label_ref (match_operand 3 "" ""))))
+ (label_ref (match_operand 3))))
(clobber (reg:CCFP FPSR_REG))
(clobber (reg:CCFP FLAGS_REG))
(clobber (match_scratch:HI 4 "=a"))]
(if_then_else (match_operator 0 "ix86_fp_comparison_operator"
[(match_operand 1 "register_operand" "f")
(match_operand 2 "register_operand" "f")])
- (label_ref (match_operand 3 "" ""))
+ (label_ref (match_operand 3))
(pc)))
(clobber (reg:CCFP FPSR_REG))
(clobber (reg:CCFP FLAGS_REG))
[(match_operand 1 "register_operand" "f")
(match_operand 2 "register_operand" "f")])
(pc)
- (label_ref (match_operand 3 "" ""))))
+ (label_ref (match_operand 3))))
(clobber (reg:CCFP FPSR_REG))
(clobber (reg:CCFP FLAGS_REG))
(clobber (match_scratch:HI 4 "=a"))]
[(set (pc)
(if_then_else (match_operator 0 "ix86_fp_comparison_operator"
[(match_operand 1 "register_operand" "f")
- (match_operand 2 "const0_operand" "")])
- (label_ref (match_operand 3 "" ""))
+ (match_operand 2 "const0_operand")])
+ (label_ref (match_operand 3))
(pc)))
(clobber (reg:CCFP FPSR_REG))
(clobber (reg:CCFP FLAGS_REG))
(define_split
[(set (pc)
(if_then_else (match_operator 0 "ix86_fp_comparison_operator"
- [(match_operand 1 "register_operand" "")
- (match_operand 2 "nonimmediate_operand" "")])
- (match_operand 3 "" "")
- (match_operand 4 "" "")))
+ [(match_operand 1 "register_operand")
+ (match_operand 2 "nonimmediate_operand")])
+ (match_operand 3)
+ (match_operand 4)))
(clobber (reg:CCFP FPSR_REG))
(clobber (reg:CCFP FLAGS_REG))]
"reload_completed"
(define_split
[(set (pc)
(if_then_else (match_operator 0 "ix86_fp_comparison_operator"
- [(match_operand 1 "register_operand" "")
- (match_operand 2 "general_operand" "")])
- (match_operand 3 "" "")
- (match_operand 4 "" "")))
+ [(match_operand 1 "register_operand")
+ (match_operand 2 "general_operand")])
+ (match_operand 3)
+ (match_operand 4)))
(clobber (reg:CCFP FPSR_REG))
(clobber (reg:CCFP FLAGS_REG))
(clobber (match_scratch:HI 5 "=a"))]
[(match_operator 1 "float_operator"
[(match_operand:SWI24 2 "nonimmediate_operand" "m,?r")])
(match_operand 3 "register_operand" "f,f")])
- (label_ref (match_operand 4 "" ""))
+ (label_ref (match_operand 4))
(pc)))
(clobber (reg:CCFP FPSR_REG))
(clobber (reg:CCFP FLAGS_REG))
(if_then_else
(match_operator 0 "ix86_swapped_fp_comparison_operator"
[(match_operator 1 "float_operator"
- [(match_operand:SWI24 2 "memory_operand" "")])
- (match_operand 3 "register_operand" "")])
- (match_operand 4 "" "")
- (match_operand 5 "" "")))
+ [(match_operand:SWI24 2 "memory_operand")])
+ (match_operand 3 "register_operand")])
+ (match_operand 4)
+ (match_operand 5)))
(clobber (reg:CCFP FPSR_REG))
(clobber (reg:CCFP FLAGS_REG))
(clobber (match_scratch:HI 6 "=a"))]
(if_then_else
(match_operator 0 "ix86_swapped_fp_comparison_operator"
[(match_operator 1 "float_operator"
- [(match_operand:SWI24 2 "register_operand" "")])
- (match_operand 3 "register_operand" "")])
- (match_operand 4 "" "")
- (match_operand 5 "" "")))
+ [(match_operand:SWI24 2 "register_operand")])
+ (match_operand 3 "register_operand")])
+ (match_operand 4)
+ (match_operand 5)))
(clobber (reg:CCFP FPSR_REG))
(clobber (reg:CCFP FLAGS_REG))
(clobber (match_scratch:HI 6 "=a"))]
(define_insn "jump"
[(set (pc)
- (label_ref (match_operand 0 "" "")))]
+ (label_ref (match_operand 0)))]
""
"jmp\t%l0"
[(set_attr "type" "ibr")
(set_attr "modrm" "0")])
(define_expand "indirect_jump"
- [(set (pc) (match_operand 0 "indirect_branch_operand" ""))]
+ [(set (pc) (match_operand 0 "indirect_branch_operand"))]
""
{
if (TARGET_X32)
(set_attr "length_immediate" "0")])
(define_expand "tablejump"
- [(parallel [(set (pc) (match_operand 0 "indirect_branch_operand" ""))
- (use (label_ref (match_operand 1 "" "")))])]
+ [(parallel [(set (pc) (match_operand 0 "indirect_branch_operand"))
+ (use (label_ref (match_operand 1)))])]
""
{
/* In PIC mode, the table entries are stored GOT (32-bit) or PC (64-bit)
(define_insn "*tablejump_1"
[(set (pc) (match_operand:W 0 "indirect_branch_operand" "rw"))
- (use (label_ref (match_operand 1 "" "")))]
+ (use (label_ref (match_operand 1)))]
""
"jmp\t%A0"
[(set_attr "type" "ibr")
;; Convert setcc + movzbl to xor + setcc if operands don't overlap.
(define_peephole2
- [(set (reg FLAGS_REG) (match_operand 0 "" ""))
- (set (match_operand:QI 1 "register_operand" "")
+ [(set (reg FLAGS_REG) (match_operand 0))
+ (set (match_operand:QI 1 "register_operand")
(match_operator:QI 2 "ix86_comparison_operator"
[(reg FLAGS_REG) (const_int 0)]))
- (set (match_operand 3 "q_regs_operand" "")
+ (set (match_operand 3 "q_regs_operand")
(zero_extend (match_dup 1)))]
"(peep2_reg_dead_p (3, operands[1])
|| operands_match_p (operands[1], operands[3]))
})
(define_peephole2
- [(parallel [(set (reg FLAGS_REG) (match_operand 0 "" ""))
- (match_operand 4 "" "")])
- (set (match_operand:QI 1 "register_operand" "")
+ [(parallel [(set (reg FLAGS_REG) (match_operand 0))
+ (match_operand 4)])
+ (set (match_operand:QI 1 "register_operand")
(match_operator:QI 2 "ix86_comparison_operator"
[(reg FLAGS_REG) (const_int 0)]))
- (set (match_operand 3 "q_regs_operand" "")
+ (set (match_operand 3 "q_regs_operand")
(zero_extend (match_dup 1)))]
"(peep2_reg_dead_p (3, operands[1])
|| operands_match_p (operands[1], operands[3]))
;; Similar, but match zero extend with andsi3.
(define_peephole2
- [(set (reg FLAGS_REG) (match_operand 0 "" ""))
- (set (match_operand:QI 1 "register_operand" "")
+ [(set (reg FLAGS_REG) (match_operand 0))
+ (set (match_operand:QI 1 "register_operand")
(match_operator:QI 2 "ix86_comparison_operator"
[(reg FLAGS_REG) (const_int 0)]))
- (parallel [(set (match_operand:SI 3 "q_regs_operand" "")
+ (parallel [(set (match_operand:SI 3 "q_regs_operand")
(and:SI (match_dup 3) (const_int 255)))
(clobber (reg:CC FLAGS_REG))])]
"REGNO (operands[1]) == REGNO (operands[3])
})
(define_peephole2
- [(parallel [(set (reg FLAGS_REG) (match_operand 0 "" ""))
- (match_operand 4 "" "")])
- (set (match_operand:QI 1 "register_operand" "")
+ [(parallel [(set (reg FLAGS_REG) (match_operand 0))
+ (match_operand 4)])
+ (set (match_operand:QI 1 "register_operand")
(match_operator:QI 2 "ix86_comparison_operator"
[(reg FLAGS_REG) (const_int 0)]))
- (parallel [(set (match_operand 3 "q_regs_operand" "")
+ (parallel [(set (match_operand 3 "q_regs_operand")
(zero_extend (match_dup 1)))
(clobber (reg:CC FLAGS_REG))])]
"(peep2_reg_dead_p (3, operands[1])
;; Call subroutine returning no value.
(define_expand "call"
- [(call (match_operand:QI 0 "" "")
- (match_operand 1 "" ""))
- (use (match_operand 2 "" ""))]
+ [(call (match_operand:QI 0)
+ (match_operand 1))
+ (use (match_operand 2))]
""
{
ix86_expand_call (NULL, operands[0], operands[1],
})
(define_expand "sibcall"
- [(call (match_operand:QI 0 "" "")
- (match_operand 1 "" ""))
- (use (match_operand 2 "" ""))]
+ [(call (match_operand:QI 0)
+ (match_operand 1))
+ (use (match_operand 2))]
""
{
ix86_expand_call (NULL, operands[0], operands[1],
(define_insn_and_split "*call_vzeroupper"
[(call (mem:QI (match_operand:W 0 "call_insn_operand" "<c>zw"))
- (match_operand 1 "" ""))
- (unspec [(match_operand 2 "const_int_operand" "")]
+ (match_operand 1))
+ (unspec [(match_operand 2 "const_int_operand")]
UNSPEC_CALL_NEEDS_VZEROUPPER)]
"TARGET_VZEROUPPER && !SIBLING_CALL_P (insn)"
"#"
(define_insn "*call"
[(call (mem:QI (match_operand:W 0 "call_insn_operand" "<c>zw"))
- (match_operand 1 "" ""))]
+ (match_operand 1))]
"!SIBLING_CALL_P (insn)"
"* return ix86_output_call_insn (insn, operands[0]);"
[(set_attr "type" "call")])
(define_insn_and_split "*call_rex64_ms_sysv_vzeroupper"
[(call (mem:QI (match_operand:DI 0 "call_insn_operand" "rzw"))
- (match_operand 1 "" ""))
+ (match_operand 1))
(unspec [(const_int 0)] UNSPEC_MS_TO_SYSV_CALL)
(clobber (reg:TI XMM6_REG))
(clobber (reg:TI XMM7_REG))
(clobber (reg:TI XMM15_REG))
(clobber (reg:DI SI_REG))
(clobber (reg:DI DI_REG))
- (unspec [(match_operand 2 "const_int_operand" "")]
+ (unspec [(match_operand 2 "const_int_operand")]
UNSPEC_CALL_NEEDS_VZEROUPPER)]
"TARGET_VZEROUPPER && TARGET_64BIT && !SIBLING_CALL_P (insn)"
"#"
(define_insn "*call_rex64_ms_sysv"
[(call (mem:QI (match_operand:DI 0 "call_insn_operand" "rzw"))
- (match_operand 1 "" ""))
+ (match_operand 1))
(unspec [(const_int 0)] UNSPEC_MS_TO_SYSV_CALL)
(clobber (reg:TI XMM6_REG))
(clobber (reg:TI XMM7_REG))
(define_insn_and_split "*sibcall_vzeroupper"
[(call (mem:QI (match_operand:W 0 "sibcall_insn_operand" "Uz"))
- (match_operand 1 "" ""))
- (unspec [(match_operand 2 "const_int_operand" "")]
+ (match_operand 1))
+ (unspec [(match_operand 2 "const_int_operand")]
UNSPEC_CALL_NEEDS_VZEROUPPER)]
"TARGET_VZEROUPPER && SIBLING_CALL_P (insn)"
"#"
(define_insn "*sibcall"
[(call (mem:QI (match_operand:W 0 "sibcall_insn_operand" "Uz"))
- (match_operand 1 "" ""))]
+ (match_operand 1))]
"SIBLING_CALL_P (insn)"
"* return ix86_output_call_insn (insn, operands[0]);"
[(set_attr "type" "call")])
(define_expand "call_pop"
- [(parallel [(call (match_operand:QI 0 "" "")
- (match_operand:SI 1 "" ""))
+ [(parallel [(call (match_operand:QI 0)
+ (match_operand:SI 1))
(set (reg:SI SP_REG)
(plus:SI (reg:SI SP_REG)
- (match_operand:SI 3 "" "")))])]
+ (match_operand:SI 3)))])]
"!TARGET_64BIT"
{
ix86_expand_call (NULL, operands[0], operands[1],
(define_insn_and_split "*call_pop_vzeroupper"
[(call (mem:QI (match_operand:SI 0 "call_insn_operand" "lzm"))
- (match_operand 1 "" ""))
+ (match_operand 1))
(set (reg:SI SP_REG)
(plus:SI (reg:SI SP_REG)
(match_operand:SI 2 "immediate_operand" "i")))
- (unspec [(match_operand 3 "const_int_operand" "")]
+ (unspec [(match_operand 3 "const_int_operand")]
UNSPEC_CALL_NEEDS_VZEROUPPER)]
"TARGET_VZEROUPPER && !TARGET_64BIT && !SIBLING_CALL_P (insn)"
"#"
(define_insn "*call_pop"
[(call (mem:QI (match_operand:SI 0 "call_insn_operand" "lzm"))
- (match_operand 1 "" ""))
+ (match_operand 1))
(set (reg:SI SP_REG)
(plus:SI (reg:SI SP_REG)
(match_operand:SI 2 "immediate_operand" "i")))]
(define_insn_and_split "*sibcall_pop_vzeroupper"
[(call (mem:QI (match_operand:SI 0 "sibcall_insn_operand" "Uz"))
- (match_operand 1 "" ""))
+ (match_operand 1))
(set (reg:SI SP_REG)
(plus:SI (reg:SI SP_REG)
(match_operand:SI 2 "immediate_operand" "i")))
- (unspec [(match_operand 3 "const_int_operand" "")]
+ (unspec [(match_operand 3 "const_int_operand")]
UNSPEC_CALL_NEEDS_VZEROUPPER)]
"TARGET_VZEROUPPER && !TARGET_64BIT && SIBLING_CALL_P (insn)"
"#"
(define_insn "*sibcall_pop"
[(call (mem:QI (match_operand:SI 0 "sibcall_insn_operand" "Uz"))
- (match_operand 1 "" ""))
+ (match_operand 1))
(set (reg:SI SP_REG)
(plus:SI (reg:SI SP_REG)
(match_operand:SI 2 "immediate_operand" "i")))]
;; Call subroutine, returning value in operand 0
(define_expand "call_value"
- [(set (match_operand 0 "" "")
- (call (match_operand:QI 1 "" "")
- (match_operand 2 "" "")))
- (use (match_operand 3 "" ""))]
+ [(set (match_operand 0)
+ (call (match_operand:QI 1)
+ (match_operand 2)))
+ (use (match_operand 3))]
""
{
ix86_expand_call (operands[0], operands[1], operands[2],
})
(define_expand "sibcall_value"
- [(set (match_operand 0 "" "")
- (call (match_operand:QI 1 "" "")
- (match_operand 2 "" "")))
- (use (match_operand 3 "" ""))]
+ [(set (match_operand 0)
+ (call (match_operand:QI 1)
+ (match_operand 2)))
+ (use (match_operand 3))]
""
{
ix86_expand_call (operands[0], operands[1], operands[2],
})
(define_insn_and_split "*call_value_vzeroupper"
- [(set (match_operand 0 "" "")
+ [(set (match_operand 0)
(call (mem:QI (match_operand:W 1 "call_insn_operand" "<c>zw"))
- (match_operand 2 "" "")))
- (unspec [(match_operand 3 "const_int_operand" "")]
+ (match_operand 2)))
+ (unspec [(match_operand 3 "const_int_operand")]
UNSPEC_CALL_NEEDS_VZEROUPPER)]
"TARGET_VZEROUPPER && !SIBLING_CALL_P (insn)"
"#"
[(set_attr "type" "callv")])
(define_insn "*call_value"
- [(set (match_operand 0 "" "")
+ [(set (match_operand 0)
(call (mem:QI (match_operand:W 1 "call_insn_operand" "<c>zw"))
- (match_operand 2 "" "")))]
+ (match_operand 2)))]
"!SIBLING_CALL_P (insn)"
"* return ix86_output_call_insn (insn, operands[1]);"
[(set_attr "type" "callv")])
(define_insn_and_split "*sibcall_value_vzeroupper"
- [(set (match_operand 0 "" "")
+ [(set (match_operand 0)
(call (mem:QI (match_operand:W 1 "sibcall_insn_operand" "Uz"))
- (match_operand 2 "" "")))
- (unspec [(match_operand 3 "const_int_operand" "")]
+ (match_operand 2)))
+ (unspec [(match_operand 3 "const_int_operand")]
UNSPEC_CALL_NEEDS_VZEROUPPER)]
"TARGET_VZEROUPPER && SIBLING_CALL_P (insn)"
"#"
[(set_attr "type" "callv")])
(define_insn "*sibcall_value"
- [(set (match_operand 0 "" "")
+ [(set (match_operand 0)
(call (mem:QI (match_operand:W 1 "sibcall_insn_operand" "Uz"))
- (match_operand 2 "" "")))]
+ (match_operand 2)))]
"SIBLING_CALL_P (insn)"
"* return ix86_output_call_insn (insn, operands[1]);"
[(set_attr "type" "callv")])
(define_insn_and_split "*call_value_rex64_ms_sysv_vzeroupper"
- [(set (match_operand 0 "" "")
+ [(set (match_operand 0)
(call (mem:QI (match_operand:DI 1 "call_insn_operand" "rzw"))
- (match_operand 2 "" "")))
+ (match_operand 2)))
(unspec [(const_int 0)] UNSPEC_MS_TO_SYSV_CALL)
(clobber (reg:TI XMM6_REG))
(clobber (reg:TI XMM7_REG))
(clobber (reg:TI XMM15_REG))
(clobber (reg:DI SI_REG))
(clobber (reg:DI DI_REG))
- (unspec [(match_operand 3 "const_int_operand" "")]
+ (unspec [(match_operand 3 "const_int_operand")]
UNSPEC_CALL_NEEDS_VZEROUPPER)]
"TARGET_VZEROUPPER && TARGET_64BIT && !SIBLING_CALL_P (insn)"
"#"
[(set_attr "type" "callv")])
(define_insn "*call_value_rex64_ms_sysv"
- [(set (match_operand 0 "" "")
+ [(set (match_operand 0)
(call (mem:QI (match_operand:DI 1 "call_insn_operand" "rzw"))
- (match_operand 2 "" "")))
+ (match_operand 2)))
(unspec [(const_int 0)] UNSPEC_MS_TO_SYSV_CALL)
(clobber (reg:TI XMM6_REG))
(clobber (reg:TI XMM7_REG))
[(set_attr "type" "callv")])
(define_expand "call_value_pop"
- [(parallel [(set (match_operand 0 "" "")
- (call (match_operand:QI 1 "" "")
- (match_operand:SI 2 "" "")))
+ [(parallel [(set (match_operand 0)
+ (call (match_operand:QI 1)
+ (match_operand:SI 2)))
(set (reg:SI SP_REG)
(plus:SI (reg:SI SP_REG)
- (match_operand:SI 4 "" "")))])]
+ (match_operand:SI 4)))])]
"!TARGET_64BIT"
{
ix86_expand_call (operands[0], operands[1], operands[2],
})
(define_insn_and_split "*call_value_pop_vzeroupper"
- [(set (match_operand 0 "" "")
+ [(set (match_operand 0)
(call (mem:QI (match_operand:SI 1 "call_insn_operand" "lzm"))
- (match_operand 2 "" "")))
+ (match_operand 2)))
(set (reg:SI SP_REG)
(plus:SI (reg:SI SP_REG)
(match_operand:SI 3 "immediate_operand" "i")))
- (unspec [(match_operand 4 "const_int_operand" "")]
+ (unspec [(match_operand 4 "const_int_operand")]
UNSPEC_CALL_NEEDS_VZEROUPPER)]
"TARGET_VZEROUPPER && !TARGET_64BIT && !SIBLING_CALL_P (insn)"
"#"
[(set_attr "type" "callv")])
(define_insn "*call_value_pop"
- [(set (match_operand 0 "" "")
+ [(set (match_operand 0)
(call (mem:QI (match_operand:SI 1 "call_insn_operand" "lzm"))
- (match_operand 2 "" "")))
+ (match_operand 2)))
(set (reg:SI SP_REG)
(plus:SI (reg:SI SP_REG)
(match_operand:SI 3 "immediate_operand" "i")))]
[(set_attr "type" "callv")])
(define_insn_and_split "*sibcall_value_pop_vzeroupper"
- [(set (match_operand 0 "" "")
+ [(set (match_operand 0)
(call (mem:QI (match_operand:SI 1 "sibcall_insn_operand" "Uz"))
- (match_operand 2 "" "")))
+ (match_operand 2)))
(set (reg:SI SP_REG)
(plus:SI (reg:SI SP_REG)
(match_operand:SI 3 "immediate_operand" "i")))
- (unspec [(match_operand 4 "const_int_operand" "")]
+ (unspec [(match_operand 4 "const_int_operand")]
UNSPEC_CALL_NEEDS_VZEROUPPER)]
"TARGET_VZEROUPPER && !TARGET_64BIT && SIBLING_CALL_P (insn)"
"#"
[(set_attr "type" "callv")])
(define_insn "*sibcall_value_pop"
- [(set (match_operand 0 "" "")
+ [(set (match_operand 0)
(call (mem:QI (match_operand:SI 1 "sibcall_insn_operand" "Uz"))
- (match_operand 2 "" "")))
+ (match_operand 2)))
(set (reg:SI SP_REG)
(plus:SI (reg:SI SP_REG)
(match_operand:SI 3 "immediate_operand" "i")))]
;; Call subroutine returning any type.
(define_expand "untyped_call"
- [(parallel [(call (match_operand 0 "" "")
+ [(parallel [(call (match_operand 0)
(const_int 0))
- (match_operand 1 "" "")
- (match_operand 2 "" "")])]
+ (match_operand 1)
+ (match_operand 2)])]
""
{
int i;
})
(define_insn "*memory_blockage"
- [(set (match_operand:BLK 0 "" "")
+ [(set (match_operand:BLK 0)
(unspec:BLK [(match_dup 0)] UNSPEC_MEMORY_BLOCKAGE))]
""
""
;; As USE insns aren't meaningful after reload, this is used instead
;; to prevent deleting instructions setting registers for PIC code
(define_insn "prologue_use"
- [(unspec_volatile [(match_operand 0 "" "")] UNSPECV_PROLOGUE_USE)]
+ [(unspec_volatile [(match_operand 0)] UNSPECV_PROLOGUE_USE)]
""
""
[(set_attr "length" "0")])
(define_insn "simple_return_pop_internal"
[(simple_return)
- (use (match_operand:SI 0 "const_int_operand" ""))]
+ (use (match_operand:SI 0 "const_int_operand"))]
"reload_completed"
"ret\t%0"
[(set_attr "length" "3")
;; Generate nops. Operand 0 is the number of nops, up to 8.
(define_insn "nops"
- [(unspec_volatile [(match_operand 0 "const_int_operand" "")]
+ [(unspec_volatile [(match_operand 0 "const_int_operand")]
UNSPECV_NOPS)]
"reload_completed"
{
;; block on K8.
(define_insn "pad"
- [(unspec_volatile [(match_operand 0 "" "")] UNSPECV_ALIGN)]
+ [(unspec_volatile [(match_operand 0)] UNSPECV_ALIGN)]
""
{
#ifdef ASM_OUTPUT_MAX_SKIP_PAD
(define_insn "set_got_labelled"
[(set (match_operand:SI 0 "register_operand" "=r")
- (unspec:SI [(label_ref (match_operand 1 "" ""))]
+ (unspec:SI [(label_ref (match_operand 1))]
UNSPEC_SET_GOT))
(clobber (reg:CC FLAGS_REG))]
"!TARGET_64BIT"
(define_insn "set_rip_rex64"
[(set (match_operand:DI 0 "register_operand" "=r")
- (unspec:DI [(label_ref (match_operand 1 "" ""))] UNSPEC_SET_RIP))]
+ (unspec:DI [(label_ref (match_operand 1))] UNSPEC_SET_RIP))]
"TARGET_64BIT"
"lea{q}\t{%l1(%%rip), %0|%0, %l1[rip]}"
[(set_attr "type" "lea")
(define_insn "set_got_offset_rex64"
[(set (match_operand:DI 0 "register_operand" "=r")
(unspec:DI
- [(label_ref (match_operand 1 "" ""))]
+ [(label_ref (match_operand 1))]
UNSPEC_SET_GOT_OFFSET))]
"TARGET_LP64"
"movabs{q}\t{$_GLOBAL_OFFSET_TABLE_-%l1, %0|%0, OFFSET FLAT:_GLOBAL_OFFSET_TABLE_-%l1}"
"ix86_expand_epilogue (0); DONE;")
(define_expand "eh_return"
- [(use (match_operand 0 "register_operand" ""))]
+ [(use (match_operand 0 "register_operand"))]
""
{
rtx tmp, sa = EH_RETURN_STACKADJ_RTX, ra = operands[0];
;; In order to support the call/return predictor, we use a return
;; instruction which the middle-end doesn't see.
(define_insn "split_stack_return"
- [(unspec_volatile [(match_operand:SI 0 "const_int_operand" "")]
+ [(unspec_volatile [(match_operand:SI 0 "const_int_operand")]
UNSPECV_SPLIT_STACK_RETURN)]
""
{
[(set_attr "atom_unit" "jeu")
(set_attr "modrm" "0")
(set (attr "length")
- (if_then_else (match_operand:SI 0 "const0_operand" "")
+ (if_then_else (match_operand:SI 0 "const0_operand")
(const_int 1)
(const_int 3)))
(set (attr "length_immediate")
- (if_then_else (match_operand:SI 0 "const0_operand" "")
+ (if_then_else (match_operand:SI 0 "const0_operand")
(const_int 0)
(const_int 2)))])
(define_expand "split_stack_space_check"
[(set (pc) (if_then_else
(ltu (minus (reg SP_REG)
- (match_operand 0 "register_operand" ""))
+ (match_operand 0 "register_operand"))
(unspec [(const_int 0)] UNSPEC_STACK_CHECK))
- (label_ref (match_operand 1 "" ""))
+ (label_ref (match_operand 1))
(pc)))]
""
{
[(set (match_dup 2) (const_int -1))
(parallel [(set (reg:CCZ FLAGS_REG)
(compare:CCZ
- (match_operand:SWI48 1 "nonimmediate_operand" "")
+ (match_operand:SWI48 1 "nonimmediate_operand")
(const_int 0)))
- (set (match_operand:SWI48 0 "register_operand" "")
+ (set (match_operand:SWI48 0 "register_operand")
(ctz:SWI48 (match_dup 1)))])
(set (match_dup 0) (if_then_else:SWI48
(eq (reg:CCZ FLAGS_REG) (const_int 0))
(define_expand "clz<mode>2"
[(parallel
- [(set (match_operand:SWI248 0 "register_operand" "")
+ [(set (match_operand:SWI248 0 "register_operand")
(minus:SWI248
(match_dup 2)
- (clz:SWI248 (match_operand:SWI248 1 "nonimmediate_operand" ""))))
+ (clz:SWI248 (match_operand:SWI248 1 "nonimmediate_operand"))))
(clobber (reg:CC FLAGS_REG))])
(parallel
[(set (match_dup 0) (xor:SWI248 (match_dup 0) (match_dup 2)))
(set_attr "mode" "SI")])
(define_expand "bswap<mode>2"
- [(set (match_operand:SWI48 0 "register_operand" "")
- (bswap:SWI48 (match_operand:SWI48 1 "register_operand" "")))]
+ [(set (match_operand:SWI48 0 "register_operand")
+ (bswap:SWI48 (match_operand:SWI48 1 "register_operand")))]
""
{
if (<MODE>mode == SImode && !(TARGET_BSWAP || TARGET_MOVBE))
(set_attr "mode" "HI")])
(define_expand "paritydi2"
- [(set (match_operand:DI 0 "register_operand" "")
- (parity:DI (match_operand:DI 1 "register_operand" "")))]
+ [(set (match_operand:DI 0 "register_operand")
+ (parity:DI (match_operand:DI 1 "register_operand")))]
"! TARGET_POPCNT"
{
rtx scratch = gen_reg_rtx (QImode);
})
(define_expand "paritysi2"
- [(set (match_operand:SI 0 "register_operand" "")
- (parity:SI (match_operand:SI 1 "register_operand" "")))]
+ [(set (match_operand:SI 0 "register_operand")
+ (parity:SI (match_operand:SI 1 "register_operand")))]
"! TARGET_POPCNT"
{
rtx scratch = gen_reg_rtx (QImode);
[(set (match_operand:SI 0 "register_operand" "=a")
(unspec:SI
[(match_operand:SI 1 "register_operand" "b")
- (match_operand 2 "tls_symbolic_operand" "")
+ (match_operand 2 "tls_symbolic_operand")
(match_operand 3 "constant_call_address_operand" "z")]
UNSPEC_TLS_GD))
(clobber (match_scratch:SI 4 "=d"))
(define_expand "tls_global_dynamic_32"
[(parallel
- [(set (match_operand:SI 0 "register_operand" "")
- (unspec:SI [(match_operand:SI 2 "register_operand" "")
- (match_operand 1 "tls_symbolic_operand" "")
- (match_operand 3 "constant_call_address_operand" "")]
+ [(set (match_operand:SI 0 "register_operand")
+ (unspec:SI [(match_operand:SI 2 "register_operand")
+ (match_operand 1 "tls_symbolic_operand")
+ (match_operand 3 "constant_call_address_operand")]
UNSPEC_TLS_GD))
- (clobber (match_scratch:SI 4 ""))
- (clobber (match_scratch:SI 5 ""))
+ (clobber (match_scratch:SI 4))
+ (clobber (match_scratch:SI 5))
(clobber (reg:CC FLAGS_REG))])])
(define_insn "*tls_global_dynamic_64_<mode>"
[(set (match_operand:P 0 "register_operand" "=a")
(call:P
(mem:QI (match_operand 2 "constant_call_address_operand" "z"))
- (match_operand 3 "" "")))
- (unspec:P [(match_operand 1 "tls_symbolic_operand" "")]
+ (match_operand 3)))
+ (unspec:P [(match_operand 1 "tls_symbolic_operand")]
UNSPEC_TLS_GD)]
"TARGET_64BIT"
{
(define_expand "tls_global_dynamic_64_<mode>"
[(parallel
- [(set (match_operand:P 0 "register_operand" "")
+ [(set (match_operand:P 0 "register_operand")
(call:P
- (mem:QI (match_operand 2 "constant_call_address_operand" ""))
+ (mem:QI (match_operand 2 "constant_call_address_operand"))
(const_int 0)))
- (unspec:P [(match_operand 1 "tls_symbolic_operand" "")]
+ (unspec:P [(match_operand 1 "tls_symbolic_operand")]
UNSPEC_TLS_GD)])]
"TARGET_64BIT")
(define_expand "tls_local_dynamic_base_32"
[(parallel
- [(set (match_operand:SI 0 "register_operand" "")
+ [(set (match_operand:SI 0 "register_operand")
(unspec:SI
- [(match_operand:SI 1 "register_operand" "")
- (match_operand 2 "constant_call_address_operand" "")]
+ [(match_operand:SI 1 "register_operand")
+ (match_operand 2 "constant_call_address_operand")]
UNSPEC_TLS_LD_BASE))
- (clobber (match_scratch:SI 3 ""))
- (clobber (match_scratch:SI 4 ""))
+ (clobber (match_scratch:SI 3))
+ (clobber (match_scratch:SI 4))
(clobber (reg:CC FLAGS_REG))])])
(define_insn "*tls_local_dynamic_base_64_<mode>"
[(set (match_operand:P 0 "register_operand" "=a")
(call:P
(mem:QI (match_operand 1 "constant_call_address_operand" "z"))
- (match_operand 2 "" "")))
+ (match_operand 2)))
(unspec:P [(const_int 0)] UNSPEC_TLS_LD_BASE)]
"TARGET_64BIT"
{
(define_expand "tls_local_dynamic_base_64_<mode>"
[(parallel
- [(set (match_operand:P 0 "register_operand" "")
+ [(set (match_operand:P 0 "register_operand")
(call:P
- (mem:QI (match_operand 1 "constant_call_address_operand" ""))
+ (mem:QI (match_operand 1 "constant_call_address_operand"))
(const_int 0)))
(unspec:P [(const_int 0)] UNSPEC_TLS_LD_BASE)])]
"TARGET_64BIT")
(match_operand 2 "constant_call_address_operand" "z")]
UNSPEC_TLS_LD_BASE)
(const:SI (unspec:SI
- [(match_operand 3 "tls_symbolic_operand" "")]
+ [(match_operand 3 "tls_symbolic_operand")]
UNSPEC_DTPOFF))))
(clobber (match_scratch:SI 4 "=d"))
(clobber (match_scratch:SI 5 "=c"))
(define_insn "tls_initial_exec_64_sun"
[(set (match_operand:DI 0 "register_operand" "=a")
(unspec:DI
- [(match_operand 1 "tls_symbolic_operand" "")]
+ [(match_operand 1 "tls_symbolic_operand")]
UNSPEC_TLS_IE_SUN))
(clobber (reg:CC FLAGS_REG))]
"TARGET_64BIT && TARGET_SUN_TLS"
(define_insn "tls_initial_exec_x32"
[(set (match_operand:SI 0 "register_operand" "=r")
(unspec:SI
- [(match_operand 1 "tls_symbolic_operand" "")]
+ [(match_operand 1 "tls_symbolic_operand")]
UNSPEC_TLS_IE_X32))
(clobber (reg:CC FLAGS_REG))]
"TARGET_X32"
(define_expand "tls_dynamic_gnu2_32"
[(set (match_dup 3)
- (plus:SI (match_operand:SI 2 "register_operand" "")
+ (plus:SI (match_operand:SI 2 "register_operand")
(const:SI
- (unspec:SI [(match_operand 1 "tls_symbolic_operand" "")]
+ (unspec:SI [(match_operand 1 "tls_symbolic_operand")]
UNSPEC_TLSDESC))))
(parallel
- [(set (match_operand:SI 0 "register_operand" "")
+ [(set (match_operand:SI 0 "register_operand")
(unspec:SI [(match_dup 1) (match_dup 3)
(match_dup 2) (reg:SI SP_REG)]
UNSPEC_TLSDESC))
[(set (match_operand:SI 0 "register_operand" "=r")
(plus:SI (match_operand:SI 1 "register_operand" "b")
(const:SI
- (unspec:SI [(match_operand 2 "tls_symbolic_operand" "")]
+ (unspec:SI [(match_operand 2 "tls_symbolic_operand")]
UNSPEC_TLSDESC))))]
"!TARGET_64BIT && TARGET_GNU2_TLS"
"lea{l}\t{%E2@TLSDESC(%1), %0|%0, %E2@TLSDESC[%1]}"
(define_insn "*tls_dynamic_gnu2_call_32"
[(set (match_operand:SI 0 "register_operand" "=a")
- (unspec:SI [(match_operand 1 "tls_symbolic_operand" "")
+ (unspec:SI [(match_operand 1 "tls_symbolic_operand")
(match_operand:SI 2 "register_operand" "0")
;; we have to make sure %ebx still points to the GOT
(match_operand:SI 3 "register_operand" "b")
(define_insn_and_split "*tls_dynamic_gnu2_combine_32"
[(set (match_operand:SI 0 "register_operand" "=&a")
(plus:SI
- (unspec:SI [(match_operand 3 "tls_modbase_operand" "")
- (match_operand:SI 4 "" "")
+ (unspec:SI [(match_operand 3 "tls_modbase_operand")
+ (match_operand:SI 4)
(match_operand:SI 2 "register_operand" "b")
(reg:SI SP_REG)]
UNSPEC_TLSDESC)
(const:SI (unspec:SI
- [(match_operand 1 "tls_symbolic_operand" "")]
+ [(match_operand 1 "tls_symbolic_operand")]
UNSPEC_DTPOFF))))
(clobber (reg:CC FLAGS_REG))]
"!TARGET_64BIT && TARGET_GNU2_TLS"
(define_expand "tls_dynamic_gnu2_64"
[(set (match_dup 2)
- (unspec:DI [(match_operand 1 "tls_symbolic_operand" "")]
+ (unspec:DI [(match_operand 1 "tls_symbolic_operand")]
UNSPEC_TLSDESC))
(parallel
- [(set (match_operand:DI 0 "register_operand" "")
+ [(set (match_operand:DI 0 "register_operand")
(unspec:DI [(match_dup 1) (match_dup 2) (reg:DI SP_REG)]
UNSPEC_TLSDESC))
(clobber (reg:CC FLAGS_REG))])]
(define_insn "*tls_dynamic_gnu2_lea_64"
[(set (match_operand:DI 0 "register_operand" "=r")
- (unspec:DI [(match_operand 1 "tls_symbolic_operand" "")]
+ (unspec:DI [(match_operand 1 "tls_symbolic_operand")]
UNSPEC_TLSDESC))]
"TARGET_64BIT && TARGET_GNU2_TLS"
"lea{q}\t{%E1@TLSDESC(%%rip), %0|%0, %E1@TLSDESC[rip]}"
(define_insn "*tls_dynamic_gnu2_call_64"
[(set (match_operand:DI 0 "register_operand" "=a")
- (unspec:DI [(match_operand 1 "tls_symbolic_operand" "")
+ (unspec:DI [(match_operand 1 "tls_symbolic_operand")
(match_operand:DI 2 "register_operand" "0")
(reg:DI SP_REG)]
UNSPEC_TLSDESC))
(define_insn_and_split "*tls_dynamic_gnu2_combine_64"
[(set (match_operand:DI 0 "register_operand" "=&a")
(plus:DI
- (unspec:DI [(match_operand 2 "tls_modbase_operand" "")
- (match_operand:DI 3 "" "")
+ (unspec:DI [(match_operand 2 "tls_modbase_operand")
+ (match_operand:DI 3)
(reg:DI SP_REG)]
UNSPEC_TLSDESC)
(const:DI (unspec:DI
- [(match_operand 1 "tls_symbolic_operand" "")]
+ [(match_operand 1 "tls_symbolic_operand")]
UNSPEC_DTPOFF))))
(clobber (reg:CC FLAGS_REG))]
"TARGET_64BIT && TARGET_GNU2_TLS"
"* return output_387_binary_op (insn, operands);"
[(set (attr "type")
(if_then_else (eq_attr "alternative" "1,2")
- (if_then_else (match_operand:MODEF 3 "mult_operator" "")
+ (if_then_else (match_operand:MODEF 3 "mult_operator")
(const_string "ssemul")
(const_string "sseadd"))
- (if_then_else (match_operand:MODEF 3 "mult_operator" "")
+ (if_then_else (match_operand:MODEF 3 "mult_operator")
(const_string "fmul")
(const_string "fop"))))
(set_attr "isa" "*,noavx,avx")
&& !(MEM_P (operands[1]) && MEM_P (operands[2]))"
"* return output_387_binary_op (insn, operands);"
[(set (attr "type")
- (if_then_else (match_operand:MODEF 3 "mult_operator" "")
+ (if_then_else (match_operand:MODEF 3 "mult_operator")
(const_string "ssemul")
(const_string "sseadd")))
(set_attr "isa" "noavx,avx")
&& !(MEM_P (operands[1]) && MEM_P (operands[2]))"
"* return output_387_binary_op (insn, operands);"
[(set (attr "type")
- (if_then_else (match_operand:MODEF 3 "mult_operator" "")
+ (if_then_else (match_operand:MODEF 3 "mult_operator")
(const_string "fmul")
(const_string "fop")))
(set_attr "mode" "<MODE>")])
"* return output_387_binary_op (insn, operands);"
[(set (attr "type")
(cond [(and (eq_attr "alternative" "2,3")
- (match_operand:MODEF 3 "mult_operator" ""))
+ (match_operand:MODEF 3 "mult_operator"))
(const_string "ssemul")
(and (eq_attr "alternative" "2,3")
- (match_operand:MODEF 3 "div_operator" ""))
+ (match_operand:MODEF 3 "div_operator"))
(const_string "ssediv")
(eq_attr "alternative" "2,3")
(const_string "sseadd")
- (match_operand:MODEF 3 "mult_operator" "")
+ (match_operand:MODEF 3 "mult_operator")
(const_string "fmul")
- (match_operand:MODEF 3 "div_operator" "")
+ (match_operand:MODEF 3 "div_operator")
(const_string "fdiv")
]
(const_string "fop")))
&& !COMMUTATIVE_ARITH_P (operands[3])"
"* return output_387_binary_op (insn, operands);"
[(set (attr "type")
- (cond [(match_operand:MODEF 3 "mult_operator" "")
+ (cond [(match_operand:MODEF 3 "mult_operator")
(const_string "ssemul")
- (match_operand:MODEF 3 "div_operator" "")
+ (match_operand:MODEF 3 "div_operator")
(const_string "ssediv")
]
(const_string "sseadd")))
&& !(MEM_P (operands[1]) && MEM_P (operands[2]))"
"* return output_387_binary_op (insn, operands);"
[(set (attr "type")
- (cond [(match_operand:MODEF 3 "mult_operator" "")
+ (cond [(match_operand:MODEF 3 "mult_operator")
(const_string "fmul")
- (match_operand:MODEF 3 "div_operator" "")
+ (match_operand:MODEF 3 "div_operator")
(const_string "fdiv")
]
(const_string "fop")))
&& (TARGET_USE_<SWI24:MODE>MODE_FIOP || optimize_function_for_size_p (cfun))"
"* return which_alternative ? \"#\" : output_387_binary_op (insn, operands);"
[(set (attr "type")
- (cond [(match_operand:MODEF 3 "mult_operator" "")
+ (cond [(match_operand:MODEF 3 "mult_operator")
(const_string "fmul")
- (match_operand:MODEF 3 "div_operator" "")
+ (match_operand:MODEF 3 "div_operator")
(const_string "fdiv")
]
(const_string "fop")))
&& (TARGET_USE_<SWI24:MODE>MODE_FIOP || optimize_function_for_size_p (cfun))"
"* return which_alternative ? \"#\" : output_387_binary_op (insn, operands);"
[(set (attr "type")
- (cond [(match_operand:MODEF 3 "mult_operator" "")
+ (cond [(match_operand:MODEF 3 "mult_operator")
(const_string "fmul")
- (match_operand:MODEF 3 "div_operator" "")
+ (match_operand:MODEF 3 "div_operator")
(const_string "fdiv")
]
(const_string "fop")))
&& !(MEM_P (operands[1]) && MEM_P (operands[2]))"
"* return output_387_binary_op (insn, operands);"
[(set (attr "type")
- (cond [(match_operand:DF 3 "mult_operator" "")
+ (cond [(match_operand:DF 3 "mult_operator")
(const_string "fmul")
- (match_operand:DF 3 "div_operator" "")
+ (match_operand:DF 3 "div_operator")
(const_string "fdiv")
]
(const_string "fop")))
&& !(TARGET_SSE2 && TARGET_SSE_MATH)"
"* return output_387_binary_op (insn, operands);"
[(set (attr "type")
- (cond [(match_operand:DF 3 "mult_operator" "")
+ (cond [(match_operand:DF 3 "mult_operator")
(const_string "fmul")
- (match_operand:DF 3 "div_operator" "")
+ (match_operand:DF 3 "div_operator")
(const_string "fdiv")
]
(const_string "fop")))
&& !(TARGET_SSE2 && TARGET_SSE_MATH)"
"* return output_387_binary_op (insn, operands);"
[(set (attr "type")
- (cond [(match_operand:DF 3 "mult_operator" "")
+ (cond [(match_operand:DF 3 "mult_operator")
(const_string "fmul")
- (match_operand:DF 3 "div_operator" "")
+ (match_operand:DF 3 "div_operator")
(const_string "fdiv")
]
(const_string "fop")))
&& COMMUTATIVE_ARITH_P (operands[3])"
"* return output_387_binary_op (insn, operands);"
[(set (attr "type")
- (if_then_else (match_operand:XF 3 "mult_operator" "")
+ (if_then_else (match_operand:XF 3 "mult_operator")
(const_string "fmul")
(const_string "fop")))
(set_attr "mode" "XF")])
&& !COMMUTATIVE_ARITH_P (operands[3])"
"* return output_387_binary_op (insn, operands);"
[(set (attr "type")
- (cond [(match_operand:XF 3 "mult_operator" "")
+ (cond [(match_operand:XF 3 "mult_operator")
(const_string "fmul")
- (match_operand:XF 3 "div_operator" "")
+ (match_operand:XF 3 "div_operator")
(const_string "fdiv")
]
(const_string "fop")))
"TARGET_80387 && (TARGET_USE_<MODE>MODE_FIOP || optimize_function_for_size_p (cfun))"
"* return which_alternative ? \"#\" : output_387_binary_op (insn, operands);"
[(set (attr "type")
- (cond [(match_operand:XF 3 "mult_operator" "")
+ (cond [(match_operand:XF 3 "mult_operator")
(const_string "fmul")
- (match_operand:XF 3 "div_operator" "")
+ (match_operand:XF 3 "div_operator")
(const_string "fdiv")
]
(const_string "fop")))
"TARGET_80387 && (TARGET_USE_<MODE>MODE_FIOP || optimize_function_for_size_p (cfun))"
"* return which_alternative ? \"#\" : output_387_binary_op (insn, operands);"
[(set (attr "type")
- (cond [(match_operand:XF 3 "mult_operator" "")
+ (cond [(match_operand:XF 3 "mult_operator")
(const_string "fmul")
- (match_operand:XF 3 "div_operator" "")
+ (match_operand:XF 3 "div_operator")
(const_string "fdiv")
]
(const_string "fop")))
"TARGET_80387"
"* return output_387_binary_op (insn, operands);"
[(set (attr "type")
- (cond [(match_operand:XF 3 "mult_operator" "")
+ (cond [(match_operand:XF 3 "mult_operator")
(const_string "fmul")
- (match_operand:XF 3 "div_operator" "")
+ (match_operand:XF 3 "div_operator")
(const_string "fdiv")
]
(const_string "fop")))
"TARGET_80387"
"* return output_387_binary_op (insn, operands);"
[(set (attr "type")
- (cond [(match_operand:XF 3 "mult_operator" "")
+ (cond [(match_operand:XF 3 "mult_operator")
(const_string "fmul")
- (match_operand:XF 3 "div_operator" "")
+ (match_operand:XF 3 "div_operator")
(const_string "fdiv")
]
(const_string "fop")))
"TARGET_80387"
"* return output_387_binary_op (insn, operands);"
[(set (attr "type")
- (cond [(match_operand:XF 3 "mult_operator" "")
+ (cond [(match_operand:XF 3 "mult_operator")
(const_string "fmul")
- (match_operand:XF 3 "div_operator" "")
+ (match_operand:XF 3 "div_operator")
(const_string "fdiv")
]
(const_string "fop")))
(set_attr "mode" "<MODE>")])
(define_split
- [(set (match_operand 0 "register_operand" "")
+ [(set (match_operand 0 "register_operand")
(match_operator 3 "binary_fp_operator"
- [(float (match_operand:SWI24 1 "register_operand" ""))
- (match_operand 2 "register_operand" "")]))]
+ [(float (match_operand:SWI24 1 "register_operand"))
+ (match_operand 2 "register_operand")]))]
"reload_completed
&& X87_FLOAT_MODE_P (GET_MODE (operands[0]))
&& X87_ENABLE_FLOAT (GET_MODE (operands[0]), GET_MODE (operands[1]))"
})
(define_split
- [(set (match_operand 0 "register_operand" "")
+ [(set (match_operand 0 "register_operand")
(match_operator 3 "binary_fp_operator"
- [(match_operand 1 "register_operand" "")
- (float (match_operand:SWI24 2 "register_operand" ""))]))]
+ [(match_operand 1 "register_operand")
+ (float (match_operand:SWI24 2 "register_operand"))]))]
"reload_completed
&& X87_FLOAT_MODE_P (GET_MODE (operands[0]))
&& X87_ENABLE_FLOAT (GET_MODE (operands[0]), GET_MODE (operands[2]))"
(set_attr "mode" "SF")])
(define_expand "rsqrtsf2"
- [(set (match_operand:SF 0 "register_operand" "")
- (unspec:SF [(match_operand:SF 1 "nonimmediate_operand" "")]
+ [(set (match_operand:SF 0 "register_operand")
+ (unspec:SF [(match_operand:SF 1 "nonimmediate_operand")]
UNSPEC_RSQRT))]
"TARGET_SSE_MATH"
{
(set_attr "bdver1_decode" "*")])
(define_expand "sqrt<mode>2"
- [(set (match_operand:MODEF 0 "register_operand" "")
+ [(set (match_operand:MODEF 0 "register_operand")
(sqrt:MODEF
- (match_operand:MODEF 1 "nonimmediate_operand" "")))]
+ (match_operand:MODEF 1 "nonimmediate_operand")))]
"(TARGET_USE_FANCY_MATH_387 && X87_ENABLE_ARITH (<MODE>mode))
|| (SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH)"
{
(set_attr "mode" "XF")])
(define_expand "fmodxf3"
- [(use (match_operand:XF 0 "register_operand" ""))
- (use (match_operand:XF 1 "general_operand" ""))
- (use (match_operand:XF 2 "general_operand" ""))]
+ [(use (match_operand:XF 0 "register_operand"))
+ (use (match_operand:XF 1 "general_operand"))
+ (use (match_operand:XF 2 "general_operand"))]
"TARGET_USE_FANCY_MATH_387"
{
rtx label = gen_label_rtx ();
})
(define_expand "fmod<mode>3"
- [(use (match_operand:MODEF 0 "register_operand" ""))
- (use (match_operand:MODEF 1 "general_operand" ""))
- (use (match_operand:MODEF 2 "general_operand" ""))]
+ [(use (match_operand:MODEF 0 "register_operand"))
+ (use (match_operand:MODEF 1 "general_operand"))
+ (use (match_operand:MODEF 2 "general_operand"))]
"TARGET_USE_FANCY_MATH_387"
{
rtx (*gen_truncxf) (rtx, rtx);
(set_attr "mode" "XF")])
(define_expand "remainderxf3"
- [(use (match_operand:XF 0 "register_operand" ""))
- (use (match_operand:XF 1 "general_operand" ""))
- (use (match_operand:XF 2 "general_operand" ""))]
+ [(use (match_operand:XF 0 "register_operand"))
+ (use (match_operand:XF 1 "general_operand"))
+ (use (match_operand:XF 2 "general_operand"))]
"TARGET_USE_FANCY_MATH_387"
{
rtx label = gen_label_rtx ();
})
(define_expand "remainder<mode>3"
- [(use (match_operand:MODEF 0 "register_operand" ""))
- (use (match_operand:MODEF 1 "general_operand" ""))
- (use (match_operand:MODEF 2 "general_operand" ""))]
+ [(use (match_operand:MODEF 0 "register_operand"))
+ (use (match_operand:MODEF 1 "general_operand"))
+ (use (match_operand:MODEF 2 "general_operand"))]
"TARGET_USE_FANCY_MATH_387"
{
rtx (*gen_truncxf) (rtx, rtx);
(set_attr "mode" "XF")])
(define_split
- [(set (match_operand:XF 0 "register_operand" "")
- (unspec:XF [(match_operand:XF 2 "register_operand" "")]
+ [(set (match_operand:XF 0 "register_operand")
+ (unspec:XF [(match_operand:XF 2 "register_operand")]
UNSPEC_SINCOS_COS))
- (set (match_operand:XF 1 "register_operand" "")
+ (set (match_operand:XF 1 "register_operand")
(unspec:XF [(match_dup 2)] UNSPEC_SINCOS_SIN))]
"find_regno_note (insn, REG_UNUSED, REGNO (operands[0]))
&& can_create_pseudo_p ()"
[(set (match_dup 1) (unspec:XF [(match_dup 2)] UNSPEC_SIN))])
(define_split
- [(set (match_operand:XF 0 "register_operand" "")
- (unspec:XF [(match_operand:XF 2 "register_operand" "")]
+ [(set (match_operand:XF 0 "register_operand")
+ (unspec:XF [(match_operand:XF 2 "register_operand")]
UNSPEC_SINCOS_COS))
- (set (match_operand:XF 1 "register_operand" "")
+ (set (match_operand:XF 1 "register_operand")
(unspec:XF [(match_dup 2)] UNSPEC_SINCOS_SIN))]
"find_regno_note (insn, REG_UNUSED, REGNO (operands[1]))
&& can_create_pseudo_p ()"
(set_attr "mode" "XF")])
(define_split
- [(set (match_operand:XF 0 "register_operand" "")
+ [(set (match_operand:XF 0 "register_operand")
(unspec:XF [(float_extend:XF
- (match_operand:MODEF 2 "register_operand" ""))]
+ (match_operand:MODEF 2 "register_operand"))]
UNSPEC_SINCOS_COS))
- (set (match_operand:XF 1 "register_operand" "")
+ (set (match_operand:XF 1 "register_operand")
(unspec:XF [(float_extend:XF (match_dup 2))] UNSPEC_SINCOS_SIN))]
"find_regno_note (insn, REG_UNUSED, REGNO (operands[0]))
&& can_create_pseudo_p ()"
(unspec:XF [(float_extend:XF (match_dup 2))] UNSPEC_SIN))])
(define_split
- [(set (match_operand:XF 0 "register_operand" "")
+ [(set (match_operand:XF 0 "register_operand")
(unspec:XF [(float_extend:XF
- (match_operand:MODEF 2 "register_operand" ""))]
+ (match_operand:MODEF 2 "register_operand"))]
UNSPEC_SINCOS_COS))
- (set (match_operand:XF 1 "register_operand" "")
+ (set (match_operand:XF 1 "register_operand")
(unspec:XF [(float_extend:XF (match_dup 2))] UNSPEC_SINCOS_SIN))]
"find_regno_note (insn, REG_UNUSED, REGNO (operands[1]))
&& can_create_pseudo_p ()"
(unspec:XF [(float_extend:XF (match_dup 2))] UNSPEC_COS))])
(define_expand "sincos<mode>3"
- [(use (match_operand:MODEF 0 "register_operand" ""))
- (use (match_operand:MODEF 1 "register_operand" ""))
- (use (match_operand:MODEF 2 "register_operand" ""))]
+ [(use (match_operand:MODEF 0 "register_operand"))
+ (use (match_operand:MODEF 1 "register_operand"))
+ (use (match_operand:MODEF 2 "register_operand"))]
"TARGET_USE_FANCY_MATH_387
&& (!(SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH)
|| TARGET_MIX_SSE_I387)
(set_attr "mode" "XF")])
(define_expand "tanxf2"
- [(use (match_operand:XF 0 "register_operand" ""))
- (use (match_operand:XF 1 "register_operand" ""))]
+ [(use (match_operand:XF 0 "register_operand"))
+ (use (match_operand:XF 1 "register_operand"))]
"TARGET_USE_FANCY_MATH_387
&& flag_unsafe_math_optimizations"
{
})
(define_expand "tan<mode>2"
- [(use (match_operand:MODEF 0 "register_operand" ""))
- (use (match_operand:MODEF 1 "register_operand" ""))]
+ [(use (match_operand:MODEF 0 "register_operand"))
+ (use (match_operand:MODEF 1 "register_operand"))]
"TARGET_USE_FANCY_MATH_387
&& (!(SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH)
|| TARGET_MIX_SSE_I387)
(set_attr "mode" "XF")])
(define_expand "atan2xf3"
- [(parallel [(set (match_operand:XF 0 "register_operand" "")
- (unspec:XF [(match_operand:XF 2 "register_operand" "")
- (match_operand:XF 1 "register_operand" "")]
+ [(parallel [(set (match_operand:XF 0 "register_operand")
+ (unspec:XF [(match_operand:XF 2 "register_operand")
+ (match_operand:XF 1 "register_operand")]
UNSPEC_FPATAN))
- (clobber (match_scratch:XF 3 ""))])]
+ (clobber (match_scratch:XF 3))])]
"TARGET_USE_FANCY_MATH_387
&& flag_unsafe_math_optimizations")
(define_expand "atan2<mode>3"
- [(use (match_operand:MODEF 0 "register_operand" ""))
- (use (match_operand:MODEF 1 "register_operand" ""))
- (use (match_operand:MODEF 2 "register_operand" ""))]
+ [(use (match_operand:MODEF 0 "register_operand"))
+ (use (match_operand:MODEF 1 "register_operand"))
+ (use (match_operand:MODEF 2 "register_operand"))]
"TARGET_USE_FANCY_MATH_387
&& (!(SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH)
|| TARGET_MIX_SSE_I387)
})
(define_expand "atanxf2"
- [(parallel [(set (match_operand:XF 0 "register_operand" "")
+ [(parallel [(set (match_operand:XF 0 "register_operand")
(unspec:XF [(match_dup 2)
- (match_operand:XF 1 "register_operand" "")]
+ (match_operand:XF 1 "register_operand")]
UNSPEC_FPATAN))
- (clobber (match_scratch:XF 3 ""))])]
+ (clobber (match_scratch:XF 3))])]
"TARGET_USE_FANCY_MATH_387
&& flag_unsafe_math_optimizations"
{
})
(define_expand "atan<mode>2"
- [(use (match_operand:MODEF 0 "register_operand" ""))
- (use (match_operand:MODEF 1 "register_operand" ""))]
+ [(use (match_operand:MODEF 0 "register_operand"))
+ (use (match_operand:MODEF 1 "register_operand"))]
"TARGET_USE_FANCY_MATH_387
&& (!(SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH)
|| TARGET_MIX_SSE_I387)
(define_expand "asinxf2"
[(set (match_dup 2)
- (mult:XF (match_operand:XF 1 "register_operand" "")
+ (mult:XF (match_operand:XF 1 "register_operand")
(match_dup 1)))
(set (match_dup 4) (minus:XF (match_dup 3) (match_dup 2)))
(set (match_dup 5) (sqrt:XF (match_dup 4)))
- (parallel [(set (match_operand:XF 0 "register_operand" "")
+ (parallel [(set (match_operand:XF 0 "register_operand")
(unspec:XF [(match_dup 5) (match_dup 1)]
UNSPEC_FPATAN))
- (clobber (match_scratch:XF 6 ""))])]
+ (clobber (match_scratch:XF 6))])]
"TARGET_USE_FANCY_MATH_387
&& flag_unsafe_math_optimizations"
{
})
(define_expand "asin<mode>2"
- [(use (match_operand:MODEF 0 "register_operand" ""))
- (use (match_operand:MODEF 1 "general_operand" ""))]
+ [(use (match_operand:MODEF 0 "register_operand"))
+ (use (match_operand:MODEF 1 "general_operand"))]
"TARGET_USE_FANCY_MATH_387
&& (!(SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH)
|| TARGET_MIX_SSE_I387)
(define_expand "acosxf2"
[(set (match_dup 2)
- (mult:XF (match_operand:XF 1 "register_operand" "")
+ (mult:XF (match_operand:XF 1 "register_operand")
(match_dup 1)))
(set (match_dup 4) (minus:XF (match_dup 3) (match_dup 2)))
(set (match_dup 5) (sqrt:XF (match_dup 4)))
- (parallel [(set (match_operand:XF 0 "register_operand" "")
+ (parallel [(set (match_operand:XF 0 "register_operand")
(unspec:XF [(match_dup 1) (match_dup 5)]
UNSPEC_FPATAN))
- (clobber (match_scratch:XF 6 ""))])]
+ (clobber (match_scratch:XF 6))])]
"TARGET_USE_FANCY_MATH_387
&& flag_unsafe_math_optimizations"
{
})
(define_expand "acos<mode>2"
- [(use (match_operand:MODEF 0 "register_operand" ""))
- (use (match_operand:MODEF 1 "general_operand" ""))]
+ [(use (match_operand:MODEF 0 "register_operand"))
+ (use (match_operand:MODEF 1 "general_operand"))]
"TARGET_USE_FANCY_MATH_387
&& (!(SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH)
|| TARGET_MIX_SSE_I387)
(set_attr "mode" "XF")])
(define_expand "logxf2"
- [(parallel [(set (match_operand:XF 0 "register_operand" "")
- (unspec:XF [(match_operand:XF 1 "register_operand" "")
+ [(parallel [(set (match_operand:XF 0 "register_operand")
+ (unspec:XF [(match_operand:XF 1 "register_operand")
(match_dup 2)] UNSPEC_FYL2X))
- (clobber (match_scratch:XF 3 ""))])]
+ (clobber (match_scratch:XF 3))])]
"TARGET_USE_FANCY_MATH_387
&& flag_unsafe_math_optimizations"
{
})
(define_expand "log<mode>2"
- [(use (match_operand:MODEF 0 "register_operand" ""))
- (use (match_operand:MODEF 1 "register_operand" ""))]
+ [(use (match_operand:MODEF 0 "register_operand"))
+ (use (match_operand:MODEF 1 "register_operand"))]
"TARGET_USE_FANCY_MATH_387
&& (!(SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH)
|| TARGET_MIX_SSE_I387)
})
(define_expand "log10xf2"
- [(parallel [(set (match_operand:XF 0 "register_operand" "")
- (unspec:XF [(match_operand:XF 1 "register_operand" "")
+ [(parallel [(set (match_operand:XF 0 "register_operand")
+ (unspec:XF [(match_operand:XF 1 "register_operand")
(match_dup 2)] UNSPEC_FYL2X))
- (clobber (match_scratch:XF 3 ""))])]
+ (clobber (match_scratch:XF 3))])]
"TARGET_USE_FANCY_MATH_387
&& flag_unsafe_math_optimizations"
{
})
(define_expand "log10<mode>2"
- [(use (match_operand:MODEF 0 "register_operand" ""))
- (use (match_operand:MODEF 1 "register_operand" ""))]
+ [(use (match_operand:MODEF 0 "register_operand"))
+ (use (match_operand:MODEF 1 "register_operand"))]
"TARGET_USE_FANCY_MATH_387
&& (!(SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH)
|| TARGET_MIX_SSE_I387)
})
(define_expand "log2xf2"
- [(parallel [(set (match_operand:XF 0 "register_operand" "")
- (unspec:XF [(match_operand:XF 1 "register_operand" "")
+ [(parallel [(set (match_operand:XF 0 "register_operand")
+ (unspec:XF [(match_operand:XF 1 "register_operand")
(match_dup 2)] UNSPEC_FYL2X))
- (clobber (match_scratch:XF 3 ""))])]
+ (clobber (match_scratch:XF 3))])]
"TARGET_USE_FANCY_MATH_387
&& flag_unsafe_math_optimizations"
{
})
(define_expand "log2<mode>2"
- [(use (match_operand:MODEF 0 "register_operand" ""))
- (use (match_operand:MODEF 1 "register_operand" ""))]
+ [(use (match_operand:MODEF 0 "register_operand"))
+ (use (match_operand:MODEF 1 "register_operand"))]
"TARGET_USE_FANCY_MATH_387
&& (!(SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH)
|| TARGET_MIX_SSE_I387)
(set_attr "mode" "XF")])
(define_expand "log1pxf2"
- [(use (match_operand:XF 0 "register_operand" ""))
- (use (match_operand:XF 1 "register_operand" ""))]
+ [(use (match_operand:XF 0 "register_operand"))
+ (use (match_operand:XF 1 "register_operand"))]
"TARGET_USE_FANCY_MATH_387
&& flag_unsafe_math_optimizations"
{
})
(define_expand "log1p<mode>2"
- [(use (match_operand:MODEF 0 "register_operand" ""))
- (use (match_operand:MODEF 1 "register_operand" ""))]
+ [(use (match_operand:MODEF 0 "register_operand"))
+ (use (match_operand:MODEF 1 "register_operand"))]
"TARGET_USE_FANCY_MATH_387
&& (!(SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH)
|| TARGET_MIX_SSE_I387)
(define_expand "logbxf2"
[(parallel [(set (match_dup 2)
- (unspec:XF [(match_operand:XF 1 "register_operand" "")]
+ (unspec:XF [(match_operand:XF 1 "register_operand")]
UNSPEC_XTRACT_FRACT))
- (set (match_operand:XF 0 "register_operand" "")
+ (set (match_operand:XF 0 "register_operand")
(unspec:XF [(match_dup 1)] UNSPEC_XTRACT_EXP))])]
"TARGET_USE_FANCY_MATH_387
&& flag_unsafe_math_optimizations"
"operands[2] = gen_reg_rtx (XFmode);")
(define_expand "logb<mode>2"
- [(use (match_operand:MODEF 0 "register_operand" ""))
- (use (match_operand:MODEF 1 "register_operand" ""))]
+ [(use (match_operand:MODEF 0 "register_operand"))
+ (use (match_operand:MODEF 1 "register_operand"))]
"TARGET_USE_FANCY_MATH_387
&& (!(SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH)
|| TARGET_MIX_SSE_I387)
})
(define_expand "ilogbxf2"
- [(use (match_operand:SI 0 "register_operand" ""))
- (use (match_operand:XF 1 "register_operand" ""))]
+ [(use (match_operand:SI 0 "register_operand"))
+ (use (match_operand:XF 1 "register_operand"))]
"TARGET_USE_FANCY_MATH_387
&& flag_unsafe_math_optimizations"
{
})
(define_expand "ilogb<mode>2"
- [(use (match_operand:SI 0 "register_operand" ""))
- (use (match_operand:MODEF 1 "register_operand" ""))]
+ [(use (match_operand:SI 0 "register_operand"))
+ (use (match_operand:MODEF 1 "register_operand"))]
"TARGET_USE_FANCY_MATH_387
&& (!(SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH)
|| TARGET_MIX_SSE_I387)
(set_attr "mode" "XF")])
(define_expand "expNcorexf3"
- [(set (match_dup 3) (mult:XF (match_operand:XF 1 "register_operand" "")
- (match_operand:XF 2 "register_operand" "")))
+ [(set (match_dup 3) (mult:XF (match_operand:XF 1 "register_operand")
+ (match_operand:XF 2 "register_operand")))
(set (match_dup 4) (unspec:XF [(match_dup 3)] UNSPEC_FRNDINT))
(set (match_dup 5) (minus:XF (match_dup 3) (match_dup 4)))
(set (match_dup 6) (unspec:XF [(match_dup 5)] UNSPEC_F2XM1))
(set (match_dup 8) (plus:XF (match_dup 6) (match_dup 7)))
- (parallel [(set (match_operand:XF 0 "register_operand" "")
+ (parallel [(set (match_operand:XF 0 "register_operand")
(unspec:XF [(match_dup 8) (match_dup 4)]
UNSPEC_FSCALE_FRACT))
(set (match_dup 9)
})
(define_expand "expxf2"
- [(use (match_operand:XF 0 "register_operand" ""))
- (use (match_operand:XF 1 "register_operand" ""))]
+ [(use (match_operand:XF 0 "register_operand"))
+ (use (match_operand:XF 1 "register_operand"))]
"TARGET_USE_FANCY_MATH_387
&& flag_unsafe_math_optimizations"
{
})
(define_expand "exp<mode>2"
- [(use (match_operand:MODEF 0 "register_operand" ""))
- (use (match_operand:MODEF 1 "general_operand" ""))]
+ [(use (match_operand:MODEF 0 "register_operand"))
+ (use (match_operand:MODEF 1 "general_operand"))]
"TARGET_USE_FANCY_MATH_387
&& (!(SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH)
|| TARGET_MIX_SSE_I387)
})
(define_expand "exp10xf2"
- [(use (match_operand:XF 0 "register_operand" ""))
- (use (match_operand:XF 1 "register_operand" ""))]
+ [(use (match_operand:XF 0 "register_operand"))
+ (use (match_operand:XF 1 "register_operand"))]
"TARGET_USE_FANCY_MATH_387
&& flag_unsafe_math_optimizations"
{
})
(define_expand "exp10<mode>2"
- [(use (match_operand:MODEF 0 "register_operand" ""))
- (use (match_operand:MODEF 1 "general_operand" ""))]
+ [(use (match_operand:MODEF 0 "register_operand"))
+ (use (match_operand:MODEF 1 "general_operand"))]
"TARGET_USE_FANCY_MATH_387
&& (!(SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH)
|| TARGET_MIX_SSE_I387)
})
(define_expand "exp2xf2"
- [(use (match_operand:XF 0 "register_operand" ""))
- (use (match_operand:XF 1 "register_operand" ""))]
+ [(use (match_operand:XF 0 "register_operand"))
+ (use (match_operand:XF 1 "register_operand"))]
"TARGET_USE_FANCY_MATH_387
&& flag_unsafe_math_optimizations"
{
})
(define_expand "exp2<mode>2"
- [(use (match_operand:MODEF 0 "register_operand" ""))
- (use (match_operand:MODEF 1 "general_operand" ""))]
+ [(use (match_operand:MODEF 0 "register_operand"))
+ (use (match_operand:MODEF 1 "general_operand"))]
"TARGET_USE_FANCY_MATH_387
&& (!(SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH)
|| TARGET_MIX_SSE_I387)
})
(define_expand "expm1xf2"
- [(set (match_dup 3) (mult:XF (match_operand:XF 1 "register_operand" "")
+ [(set (match_dup 3) (mult:XF (match_operand:XF 1 "register_operand")
(match_dup 2)))
(set (match_dup 4) (unspec:XF [(match_dup 3)] UNSPEC_FRNDINT))
(set (match_dup 5) (minus:XF (match_dup 3) (match_dup 4)))
UNSPEC_FSCALE_EXP))])
(set (match_dup 12) (minus:XF (match_dup 10)
(float_extend:XF (match_dup 13))))
- (set (match_operand:XF 0 "register_operand" "")
+ (set (match_operand:XF 0 "register_operand")
(plus:XF (match_dup 12) (match_dup 7)))]
"TARGET_USE_FANCY_MATH_387
&& flag_unsafe_math_optimizations"
})
(define_expand "expm1<mode>2"
- [(use (match_operand:MODEF 0 "register_operand" ""))
- (use (match_operand:MODEF 1 "general_operand" ""))]
+ [(use (match_operand:MODEF 0 "register_operand"))
+ (use (match_operand:MODEF 1 "general_operand"))]
"TARGET_USE_FANCY_MATH_387
&& (!(SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH)
|| TARGET_MIX_SSE_I387)
(define_expand "ldexpxf3"
[(set (match_dup 3)
- (float:XF (match_operand:SI 2 "register_operand" "")))
- (parallel [(set (match_operand:XF 0 " register_operand" "")
- (unspec:XF [(match_operand:XF 1 "register_operand" "")
+ (float:XF (match_operand:SI 2 "register_operand")))
+ (parallel [(set (match_operand:XF 0 " register_operand")
+ (unspec:XF [(match_operand:XF 1 "register_operand")
(match_dup 3)]
UNSPEC_FSCALE_FRACT))
(set (match_dup 4)
})
(define_expand "ldexp<mode>3"
- [(use (match_operand:MODEF 0 "register_operand" ""))
- (use (match_operand:MODEF 1 "general_operand" ""))
- (use (match_operand:SI 2 "register_operand" ""))]
+ [(use (match_operand:MODEF 0 "register_operand"))
+ (use (match_operand:MODEF 1 "general_operand"))
+ (use (match_operand:SI 2 "register_operand"))]
"TARGET_USE_FANCY_MATH_387
&& (!(SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH)
|| TARGET_MIX_SSE_I387)
})
(define_expand "scalbxf3"
- [(parallel [(set (match_operand:XF 0 " register_operand" "")
- (unspec:XF [(match_operand:XF 1 "register_operand" "")
- (match_operand:XF 2 "register_operand" "")]
+ [(parallel [(set (match_operand:XF 0 " register_operand")
+ (unspec:XF [(match_operand:XF 1 "register_operand")
+ (match_operand:XF 2 "register_operand")]
UNSPEC_FSCALE_FRACT))
(set (match_dup 3)
(unspec:XF [(match_dup 1) (match_dup 2)]
})
(define_expand "scalb<mode>3"
- [(use (match_operand:MODEF 0 "register_operand" ""))
- (use (match_operand:MODEF 1 "general_operand" ""))
- (use (match_operand:MODEF 2 "general_operand" ""))]
+ [(use (match_operand:MODEF 0 "register_operand"))
+ (use (match_operand:MODEF 1 "general_operand"))
+ (use (match_operand:MODEF 2 "general_operand"))]
"TARGET_USE_FANCY_MATH_387
&& (!(SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH)
|| TARGET_MIX_SSE_I387)
})
(define_expand "significandxf2"
- [(parallel [(set (match_operand:XF 0 "register_operand" "")
- (unspec:XF [(match_operand:XF 1 "register_operand" "")]
+ [(parallel [(set (match_operand:XF 0 "register_operand")
+ (unspec:XF [(match_operand:XF 1 "register_operand")]
UNSPEC_XTRACT_FRACT))
(set (match_dup 2)
(unspec:XF [(match_dup 1)] UNSPEC_XTRACT_EXP))])]
"operands[2] = gen_reg_rtx (XFmode);")
(define_expand "significand<mode>2"
- [(use (match_operand:MODEF 0 "register_operand" ""))
- (use (match_operand:MODEF 1 "register_operand" ""))]
+ [(use (match_operand:MODEF 0 "register_operand"))
+ (use (match_operand:MODEF 1 "register_operand"))]
"TARGET_USE_FANCY_MATH_387
&& (!(SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH)
|| TARGET_MIX_SSE_I387)
(set_attr "mode" "XF")])
(define_expand "rint<mode>2"
- [(use (match_operand:MODEF 0 "register_operand" ""))
- (use (match_operand:MODEF 1 "register_operand" ""))]
+ [(use (match_operand:MODEF 0 "register_operand"))
+ (use (match_operand:MODEF 1 "register_operand"))]
"(TARGET_USE_FANCY_MATH_387
&& (!(SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH)
|| TARGET_MIX_SSE_I387)
})
(define_expand "round<mode>2"
- [(match_operand:X87MODEF 0 "register_operand" "")
- (match_operand:X87MODEF 1 "nonimmediate_operand" "")]
+ [(match_operand:X87MODEF 0 "register_operand")
+ (match_operand:X87MODEF 1 "nonimmediate_operand")]
"(TARGET_USE_FANCY_MATH_387
&& (!(SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH)
|| TARGET_MIX_SSE_I387)
})
(define_insn_and_split "*fistdi2_1"
- [(set (match_operand:DI 0 "nonimmediate_operand" "")
- (unspec:DI [(match_operand:XF 1 "register_operand" "")]
+ [(set (match_operand:DI 0 "nonimmediate_operand")
+ (unspec:DI [(match_operand:XF 1 "register_operand")]
UNSPEC_FIST))]
"TARGET_USE_FANCY_MATH_387
&& can_create_pseudo_p ()"
(set_attr "mode" "DI")])
(define_split
- [(set (match_operand:DI 0 "register_operand" "")
- (unspec:DI [(match_operand:XF 1 "register_operand" "")]
+ [(set (match_operand:DI 0 "register_operand")
+ (unspec:DI [(match_operand:XF 1 "register_operand")]
UNSPEC_FIST))
- (clobber (match_operand:DI 2 "memory_operand" ""))
- (clobber (match_scratch 3 ""))]
+ (clobber (match_operand:DI 2 "memory_operand"))
+ (clobber (match_scratch 3))]
"reload_completed"
[(parallel [(set (match_dup 2) (unspec:DI [(match_dup 1)] UNSPEC_FIST))
(clobber (match_dup 3))])
(set (match_dup 0) (match_dup 2))])
(define_split
- [(set (match_operand:DI 0 "memory_operand" "")
- (unspec:DI [(match_operand:XF 1 "register_operand" "")]
+ [(set (match_operand:DI 0 "memory_operand")
+ (unspec:DI [(match_operand:XF 1 "register_operand")]
UNSPEC_FIST))
- (clobber (match_operand:DI 2 "memory_operand" ""))
- (clobber (match_scratch 3 ""))]
+ (clobber (match_operand:DI 2 "memory_operand"))
+ (clobber (match_scratch 3))]
"reload_completed"
[(parallel [(set (match_dup 0) (unspec:DI [(match_dup 1)] UNSPEC_FIST))
(clobber (match_dup 3))])])
(define_insn_and_split "*fist<mode>2_1"
- [(set (match_operand:SWI24 0 "register_operand" "")
- (unspec:SWI24 [(match_operand:XF 1 "register_operand" "")]
+ [(set (match_operand:SWI24 0 "register_operand")
+ (unspec:SWI24 [(match_operand:XF 1 "register_operand")]
UNSPEC_FIST))]
"TARGET_USE_FANCY_MATH_387
&& can_create_pseudo_p ()"
(set_attr "mode" "<MODE>")])
(define_split
- [(set (match_operand:SWI24 0 "register_operand" "")
- (unspec:SWI24 [(match_operand:XF 1 "register_operand" "")]
+ [(set (match_operand:SWI24 0 "register_operand")
+ (unspec:SWI24 [(match_operand:XF 1 "register_operand")]
UNSPEC_FIST))
- (clobber (match_operand:SWI24 2 "memory_operand" ""))]
+ (clobber (match_operand:SWI24 2 "memory_operand"))]
"reload_completed"
[(set (match_dup 2) (unspec:SWI24 [(match_dup 1)] UNSPEC_FIST))
(set (match_dup 0) (match_dup 2))])
(define_split
- [(set (match_operand:SWI24 0 "memory_operand" "")
- (unspec:SWI24 [(match_operand:XF 1 "register_operand" "")]
+ [(set (match_operand:SWI24 0 "memory_operand")
+ (unspec:SWI24 [(match_operand:XF 1 "register_operand")]
UNSPEC_FIST))
- (clobber (match_operand:SWI24 2 "memory_operand" ""))]
+ (clobber (match_operand:SWI24 2 "memory_operand"))]
"reload_completed"
[(set (match_dup 0) (unspec:SWI24 [(match_dup 1)] UNSPEC_FIST))])
(define_expand "lrintxf<mode>2"
- [(set (match_operand:SWI248x 0 "nonimmediate_operand" "")
- (unspec:SWI248x [(match_operand:XF 1 "register_operand" "")]
+ [(set (match_operand:SWI248x 0 "nonimmediate_operand")
+ (unspec:SWI248x [(match_operand:XF 1 "register_operand")]
UNSPEC_FIST))]
"TARGET_USE_FANCY_MATH_387")
(define_expand "lrint<MODEF:mode><SWI48x:mode>2"
- [(set (match_operand:SWI48x 0 "nonimmediate_operand" "")
- (unspec:SWI48x [(match_operand:MODEF 1 "register_operand" "")]
+ [(set (match_operand:SWI48x 0 "nonimmediate_operand")
+ (unspec:SWI48x [(match_operand:MODEF 1 "register_operand")]
UNSPEC_FIX_NOTRUNC))]
"SSE_FLOAT_MODE_P (<MODEF:MODE>mode) && TARGET_SSE_MATH
&& ((<SWI48x:MODE>mode != DImode) || TARGET_64BIT)")
(define_expand "lround<X87MODEF:mode><SWI248x:mode>2"
- [(match_operand:SWI248x 0 "nonimmediate_operand" "")
- (match_operand:X87MODEF 1 "register_operand" "")]
+ [(match_operand:SWI248x 0 "nonimmediate_operand")
+ (match_operand:X87MODEF 1 "register_operand")]
"(TARGET_USE_FANCY_MATH_387
&& (!(SSE_FLOAT_MODE_P (<X87MODEF:MODE>mode) && TARGET_SSE_MATH)
|| TARGET_MIX_SSE_I387)
;; Rounding mode control word calculation could clobber FLAGS_REG.
(define_insn_and_split "frndintxf2_floor"
- [(set (match_operand:XF 0 "register_operand" "")
- (unspec:XF [(match_operand:XF 1 "register_operand" "")]
+ [(set (match_operand:XF 0 "register_operand")
+ (unspec:XF [(match_operand:XF 1 "register_operand")]
UNSPEC_FRNDINT_FLOOR))
(clobber (reg:CC FLAGS_REG))]
"TARGET_USE_FANCY_MATH_387
(set_attr "mode" "XF")])
(define_expand "floorxf2"
- [(use (match_operand:XF 0 "register_operand" ""))
- (use (match_operand:XF 1 "register_operand" ""))]
+ [(use (match_operand:XF 0 "register_operand"))
+ (use (match_operand:XF 1 "register_operand"))]
"TARGET_USE_FANCY_MATH_387
&& flag_unsafe_math_optimizations"
{
})
(define_expand "floor<mode>2"
- [(use (match_operand:MODEF 0 "register_operand" ""))
- (use (match_operand:MODEF 1 "register_operand" ""))]
+ [(use (match_operand:MODEF 0 "register_operand"))
+ (use (match_operand:MODEF 1 "register_operand"))]
"(TARGET_USE_FANCY_MATH_387
&& (!(SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH)
|| TARGET_MIX_SSE_I387)
})
(define_insn_and_split "*fist<mode>2_floor_1"
- [(set (match_operand:SWI248x 0 "nonimmediate_operand" "")
- (unspec:SWI248x [(match_operand:XF 1 "register_operand" "")]
+ [(set (match_operand:SWI248x 0 "nonimmediate_operand")
+ (unspec:SWI248x [(match_operand:XF 1 "register_operand")]
UNSPEC_FIST_FLOOR))
(clobber (reg:CC FLAGS_REG))]
"TARGET_USE_FANCY_MATH_387
(set_attr "mode" "DI")])
(define_split
- [(set (match_operand:DI 0 "register_operand" "")
- (unspec:DI [(match_operand:XF 1 "register_operand" "")]
+ [(set (match_operand:DI 0 "register_operand")
+ (unspec:DI [(match_operand:XF 1 "register_operand")]
UNSPEC_FIST_FLOOR))
- (use (match_operand:HI 2 "memory_operand" ""))
- (use (match_operand:HI 3 "memory_operand" ""))
- (clobber (match_operand:DI 4 "memory_operand" ""))
- (clobber (match_scratch 5 ""))]
+ (use (match_operand:HI 2 "memory_operand"))
+ (use (match_operand:HI 3 "memory_operand"))
+ (clobber (match_operand:DI 4 "memory_operand"))
+ (clobber (match_scratch 5))]
"reload_completed"
[(parallel [(set (match_dup 4)
(unspec:DI [(match_dup 1)] UNSPEC_FIST_FLOOR))
(set (match_dup 0) (match_dup 4))])
(define_split
- [(set (match_operand:DI 0 "memory_operand" "")
- (unspec:DI [(match_operand:XF 1 "register_operand" "")]
+ [(set (match_operand:DI 0 "memory_operand")
+ (unspec:DI [(match_operand:XF 1 "register_operand")]
UNSPEC_FIST_FLOOR))
- (use (match_operand:HI 2 "memory_operand" ""))
- (use (match_operand:HI 3 "memory_operand" ""))
- (clobber (match_operand:DI 4 "memory_operand" ""))
- (clobber (match_scratch 5 ""))]
+ (use (match_operand:HI 2 "memory_operand"))
+ (use (match_operand:HI 3 "memory_operand"))
+ (clobber (match_operand:DI 4 "memory_operand"))
+ (clobber (match_scratch 5))]
"reload_completed"
[(parallel [(set (match_dup 0)
(unspec:DI [(match_dup 1)] UNSPEC_FIST_FLOOR))
(set_attr "mode" "<MODE>")])
(define_split
- [(set (match_operand:SWI24 0 "register_operand" "")
- (unspec:SWI24 [(match_operand:XF 1 "register_operand" "")]
+ [(set (match_operand:SWI24 0 "register_operand")
+ (unspec:SWI24 [(match_operand:XF 1 "register_operand")]
UNSPEC_FIST_FLOOR))
- (use (match_operand:HI 2 "memory_operand" ""))
- (use (match_operand:HI 3 "memory_operand" ""))
- (clobber (match_operand:SWI24 4 "memory_operand" ""))]
+ (use (match_operand:HI 2 "memory_operand"))
+ (use (match_operand:HI 3 "memory_operand"))
+ (clobber (match_operand:SWI24 4 "memory_operand"))]
"reload_completed"
[(parallel [(set (match_dup 4)
(unspec:SWI24 [(match_dup 1)] UNSPEC_FIST_FLOOR))
(set (match_dup 0) (match_dup 4))])
(define_split
- [(set (match_operand:SWI24 0 "memory_operand" "")
- (unspec:SWI24 [(match_operand:XF 1 "register_operand" "")]
+ [(set (match_operand:SWI24 0 "memory_operand")
+ (unspec:SWI24 [(match_operand:XF 1 "register_operand")]
UNSPEC_FIST_FLOOR))
- (use (match_operand:HI 2 "memory_operand" ""))
- (use (match_operand:HI 3 "memory_operand" ""))
- (clobber (match_operand:SWI24 4 "memory_operand" ""))]
+ (use (match_operand:HI 2 "memory_operand"))
+ (use (match_operand:HI 3 "memory_operand"))
+ (clobber (match_operand:SWI24 4 "memory_operand"))]
"reload_completed"
[(parallel [(set (match_dup 0)
(unspec:SWI24 [(match_dup 1)] UNSPEC_FIST_FLOOR))
(use (match_dup 3))])])
(define_expand "lfloorxf<mode>2"
- [(parallel [(set (match_operand:SWI248x 0 "nonimmediate_operand" "")
- (unspec:SWI248x [(match_operand:XF 1 "register_operand" "")]
+ [(parallel [(set (match_operand:SWI248x 0 "nonimmediate_operand")
+ (unspec:SWI248x [(match_operand:XF 1 "register_operand")]
UNSPEC_FIST_FLOOR))
(clobber (reg:CC FLAGS_REG))])]
"TARGET_USE_FANCY_MATH_387
&& flag_unsafe_math_optimizations")
(define_expand "lfloor<MODEF:mode><SWI48:mode>2"
- [(match_operand:SWI48 0 "nonimmediate_operand" "")
- (match_operand:MODEF 1 "register_operand" "")]
+ [(match_operand:SWI48 0 "nonimmediate_operand")
+ (match_operand:MODEF 1 "register_operand")]
"SSE_FLOAT_MODE_P (<MODEF:MODE>mode) && TARGET_SSE_MATH
&& !flag_trapping_math"
{
;; Rounding mode control word calculation could clobber FLAGS_REG.
(define_insn_and_split "frndintxf2_ceil"
- [(set (match_operand:XF 0 "register_operand" "")
- (unspec:XF [(match_operand:XF 1 "register_operand" "")]
+ [(set (match_operand:XF 0 "register_operand")
+ (unspec:XF [(match_operand:XF 1 "register_operand")]
UNSPEC_FRNDINT_CEIL))
(clobber (reg:CC FLAGS_REG))]
"TARGET_USE_FANCY_MATH_387
(set_attr "mode" "XF")])
(define_expand "ceilxf2"
- [(use (match_operand:XF 0 "register_operand" ""))
- (use (match_operand:XF 1 "register_operand" ""))]
+ [(use (match_operand:XF 0 "register_operand"))
+ (use (match_operand:XF 1 "register_operand"))]
"TARGET_USE_FANCY_MATH_387
&& flag_unsafe_math_optimizations"
{
})
(define_expand "ceil<mode>2"
- [(use (match_operand:MODEF 0 "register_operand" ""))
- (use (match_operand:MODEF 1 "register_operand" ""))]
+ [(use (match_operand:MODEF 0 "register_operand"))
+ (use (match_operand:MODEF 1 "register_operand"))]
"(TARGET_USE_FANCY_MATH_387
&& (!(SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH)
|| TARGET_MIX_SSE_I387)
})
(define_insn_and_split "*fist<mode>2_ceil_1"
- [(set (match_operand:SWI248x 0 "nonimmediate_operand" "")
- (unspec:SWI248x [(match_operand:XF 1 "register_operand" "")]
+ [(set (match_operand:SWI248x 0 "nonimmediate_operand")
+ (unspec:SWI248x [(match_operand:XF 1 "register_operand")]
UNSPEC_FIST_CEIL))
(clobber (reg:CC FLAGS_REG))]
"TARGET_USE_FANCY_MATH_387
(set_attr "mode" "DI")])
(define_split
- [(set (match_operand:DI 0 "register_operand" "")
- (unspec:DI [(match_operand:XF 1 "register_operand" "")]
+ [(set (match_operand:DI 0 "register_operand")
+ (unspec:DI [(match_operand:XF 1 "register_operand")]
UNSPEC_FIST_CEIL))
- (use (match_operand:HI 2 "memory_operand" ""))
- (use (match_operand:HI 3 "memory_operand" ""))
- (clobber (match_operand:DI 4 "memory_operand" ""))
- (clobber (match_scratch 5 ""))]
+ (use (match_operand:HI 2 "memory_operand"))
+ (use (match_operand:HI 3 "memory_operand"))
+ (clobber (match_operand:DI 4 "memory_operand"))
+ (clobber (match_scratch 5))]
"reload_completed"
[(parallel [(set (match_dup 4)
(unspec:DI [(match_dup 1)] UNSPEC_FIST_CEIL))
(set (match_dup 0) (match_dup 4))])
(define_split
- [(set (match_operand:DI 0 "memory_operand" "")
- (unspec:DI [(match_operand:XF 1 "register_operand" "")]
+ [(set (match_operand:DI 0 "memory_operand")
+ (unspec:DI [(match_operand:XF 1 "register_operand")]
UNSPEC_FIST_CEIL))
- (use (match_operand:HI 2 "memory_operand" ""))
- (use (match_operand:HI 3 "memory_operand" ""))
- (clobber (match_operand:DI 4 "memory_operand" ""))
- (clobber (match_scratch 5 ""))]
+ (use (match_operand:HI 2 "memory_operand"))
+ (use (match_operand:HI 3 "memory_operand"))
+ (clobber (match_operand:DI 4 "memory_operand"))
+ (clobber (match_scratch 5))]
"reload_completed"
[(parallel [(set (match_dup 0)
(unspec:DI [(match_dup 1)] UNSPEC_FIST_CEIL))
(set_attr "mode" "<MODE>")])
(define_split
- [(set (match_operand:SWI24 0 "register_operand" "")
- (unspec:SWI24 [(match_operand:XF 1 "register_operand" "")]
+ [(set (match_operand:SWI24 0 "register_operand")
+ (unspec:SWI24 [(match_operand:XF 1 "register_operand")]
UNSPEC_FIST_CEIL))
- (use (match_operand:HI 2 "memory_operand" ""))
- (use (match_operand:HI 3 "memory_operand" ""))
- (clobber (match_operand:SWI24 4 "memory_operand" ""))]
+ (use (match_operand:HI 2 "memory_operand"))
+ (use (match_operand:HI 3 "memory_operand"))
+ (clobber (match_operand:SWI24 4 "memory_operand"))]
"reload_completed"
[(parallel [(set (match_dup 4)
(unspec:SWI24 [(match_dup 1)] UNSPEC_FIST_CEIL))
(set (match_dup 0) (match_dup 4))])
(define_split
- [(set (match_operand:SWI24 0 "memory_operand" "")
- (unspec:SWI24 [(match_operand:XF 1 "register_operand" "")]
+ [(set (match_operand:SWI24 0 "memory_operand")
+ (unspec:SWI24 [(match_operand:XF 1 "register_operand")]
UNSPEC_FIST_CEIL))
- (use (match_operand:HI 2 "memory_operand" ""))
- (use (match_operand:HI 3 "memory_operand" ""))
- (clobber (match_operand:SWI24 4 "memory_operand" ""))]
+ (use (match_operand:HI 2 "memory_operand"))
+ (use (match_operand:HI 3 "memory_operand"))
+ (clobber (match_operand:SWI24 4 "memory_operand"))]
"reload_completed"
[(parallel [(set (match_dup 0)
(unspec:SWI24 [(match_dup 1)] UNSPEC_FIST_CEIL))
(use (match_dup 3))])])
(define_expand "lceilxf<mode>2"
- [(parallel [(set (match_operand:SWI248x 0 "nonimmediate_operand" "")
- (unspec:SWI248x [(match_operand:XF 1 "register_operand" "")]
+ [(parallel [(set (match_operand:SWI248x 0 "nonimmediate_operand")
+ (unspec:SWI248x [(match_operand:XF 1 "register_operand")]
UNSPEC_FIST_CEIL))
(clobber (reg:CC FLAGS_REG))])]
"TARGET_USE_FANCY_MATH_387
&& flag_unsafe_math_optimizations")
(define_expand "lceil<MODEF:mode><SWI48:mode>2"
- [(match_operand:SWI48 0 "nonimmediate_operand" "")
- (match_operand:MODEF 1 "register_operand" "")]
+ [(match_operand:SWI48 0 "nonimmediate_operand")
+ (match_operand:MODEF 1 "register_operand")]
"SSE_FLOAT_MODE_P (<MODEF:MODE>mode) && TARGET_SSE_MATH
&& !flag_trapping_math"
{
;; Rounding mode control word calculation could clobber FLAGS_REG.
(define_insn_and_split "frndintxf2_trunc"
- [(set (match_operand:XF 0 "register_operand" "")
- (unspec:XF [(match_operand:XF 1 "register_operand" "")]
+ [(set (match_operand:XF 0 "register_operand")
+ (unspec:XF [(match_operand:XF 1 "register_operand")]
UNSPEC_FRNDINT_TRUNC))
(clobber (reg:CC FLAGS_REG))]
"TARGET_USE_FANCY_MATH_387
(set_attr "mode" "XF")])
(define_expand "btruncxf2"
- [(use (match_operand:XF 0 "register_operand" ""))
- (use (match_operand:XF 1 "register_operand" ""))]
+ [(use (match_operand:XF 0 "register_operand"))
+ (use (match_operand:XF 1 "register_operand"))]
"TARGET_USE_FANCY_MATH_387
&& flag_unsafe_math_optimizations"
{
})
(define_expand "btrunc<mode>2"
- [(use (match_operand:MODEF 0 "register_operand" ""))
- (use (match_operand:MODEF 1 "register_operand" ""))]
+ [(use (match_operand:MODEF 0 "register_operand"))
+ (use (match_operand:MODEF 1 "register_operand"))]
"(TARGET_USE_FANCY_MATH_387
&& (!(SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH)
|| TARGET_MIX_SSE_I387)
;; Rounding mode control word calculation could clobber FLAGS_REG.
(define_insn_and_split "frndintxf2_mask_pm"
- [(set (match_operand:XF 0 "register_operand" "")
- (unspec:XF [(match_operand:XF 1 "register_operand" "")]
+ [(set (match_operand:XF 0 "register_operand")
+ (unspec:XF [(match_operand:XF 1 "register_operand")]
UNSPEC_FRNDINT_MASK_PM))
(clobber (reg:CC FLAGS_REG))]
"TARGET_USE_FANCY_MATH_387
(set_attr "mode" "XF")])
(define_expand "nearbyintxf2"
- [(use (match_operand:XF 0 "register_operand" ""))
- (use (match_operand:XF 1 "register_operand" ""))]
+ [(use (match_operand:XF 0 "register_operand"))
+ (use (match_operand:XF 1 "register_operand"))]
"TARGET_USE_FANCY_MATH_387
&& flag_unsafe_math_optimizations"
{
})
(define_expand "nearbyint<mode>2"
- [(use (match_operand:MODEF 0 "register_operand" ""))
- (use (match_operand:MODEF 1 "register_operand" ""))]
+ [(use (match_operand:MODEF 0 "register_operand"))
+ (use (match_operand:MODEF 1 "register_operand"))]
"TARGET_USE_FANCY_MATH_387
&& (!(SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH)
|| TARGET_MIX_SSE_I387)
(set_attr "mode" "<MODE>")])
(define_insn_and_split "fxam<mode>2_i387_with_temp"
- [(set (match_operand:HI 0 "register_operand" "")
+ [(set (match_operand:HI 0 "register_operand")
(unspec:HI
- [(match_operand:MODEF 1 "memory_operand" "")]
+ [(match_operand:MODEF 1 "memory_operand")]
UNSPEC_FXAM_MEM))]
"TARGET_USE_FANCY_MATH_387
&& can_create_pseudo_p ()"
(set_attr "mode" "<MODE>")])
(define_expand "isinfxf2"
- [(use (match_operand:SI 0 "register_operand" ""))
- (use (match_operand:XF 1 "register_operand" ""))]
+ [(use (match_operand:SI 0 "register_operand"))
+ (use (match_operand:XF 1 "register_operand"))]
"TARGET_USE_FANCY_MATH_387
&& TARGET_C99_FUNCTIONS"
{
})
(define_expand "isinf<mode>2"
- [(use (match_operand:SI 0 "register_operand" ""))
- (use (match_operand:MODEF 1 "nonimmediate_operand" ""))]
+ [(use (match_operand:SI 0 "register_operand"))
+ (use (match_operand:MODEF 1 "nonimmediate_operand"))]
"TARGET_USE_FANCY_MATH_387
&& TARGET_C99_FUNCTIONS
&& !(SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH)"
})
(define_expand "signbitxf2"
- [(use (match_operand:SI 0 "register_operand" ""))
- (use (match_operand:XF 1 "register_operand" ""))]
+ [(use (match_operand:SI 0 "register_operand"))
+ (use (match_operand:XF 1 "register_operand"))]
"TARGET_USE_FANCY_MATH_387"
{
rtx scratch = gen_reg_rtx (HImode);
;; Use movmskpd in SSE mode to avoid store forwarding stall
;; for 32bit targets and movq+shrq sequence for 64bit targets.
(define_expand "signbitdf2"
- [(use (match_operand:SI 0 "register_operand" ""))
- (use (match_operand:DF 1 "register_operand" ""))]
+ [(use (match_operand:SI 0 "register_operand"))
+ (use (match_operand:DF 1 "register_operand"))]
"TARGET_USE_FANCY_MATH_387
|| (SSE_FLOAT_MODE_P (DFmode) && TARGET_SSE_MATH)"
{
})
(define_expand "signbitsf2"
- [(use (match_operand:SI 0 "register_operand" ""))
- (use (match_operand:SF 1 "register_operand" ""))]
+ [(use (match_operand:SI 0 "register_operand"))
+ (use (match_operand:SF 1 "register_operand"))]
"TARGET_USE_FANCY_MATH_387
&& !(SSE_FLOAT_MODE_P (SFmode) && TARGET_SSE_MATH)"
{
(set_attr "modrm" "0")])
(define_expand "movmem<mode>"
- [(use (match_operand:BLK 0 "memory_operand" ""))
- (use (match_operand:BLK 1 "memory_operand" ""))
- (use (match_operand:SWI48 2 "nonmemory_operand" ""))
- (use (match_operand:SWI48 3 "const_int_operand" ""))
- (use (match_operand:SI 4 "const_int_operand" ""))
- (use (match_operand:SI 5 "const_int_operand" ""))]
+ [(use (match_operand:BLK 0 "memory_operand"))
+ (use (match_operand:BLK 1 "memory_operand"))
+ (use (match_operand:SWI48 2 "nonmemory_operand"))
+ (use (match_operand:SWI48 3 "const_int_operand"))
+ (use (match_operand:SI 4 "const_int_operand"))
+ (use (match_operand:SI 5 "const_int_operand"))]
""
{
if (ix86_expand_movmem (operands[0], operands[1], operands[2], operands[3],
;; Handle this case here to simplify previous expander.
(define_expand "strmov"
- [(set (match_dup 4) (match_operand 3 "memory_operand" ""))
- (set (match_operand 1 "memory_operand" "") (match_dup 4))
- (parallel [(set (match_operand 0 "register_operand" "") (match_dup 5))
+ [(set (match_dup 4) (match_operand 3 "memory_operand"))
+ (set (match_operand 1 "memory_operand") (match_dup 4))
+ (parallel [(set (match_operand 0 "register_operand") (match_dup 5))
(clobber (reg:CC FLAGS_REG))])
- (parallel [(set (match_operand 2 "register_operand" "") (match_dup 6))
+ (parallel [(set (match_operand 2 "register_operand") (match_dup 6))
(clobber (reg:CC FLAGS_REG))])]
""
{
})
(define_expand "strmov_singleop"
- [(parallel [(set (match_operand 1 "memory_operand" "")
- (match_operand 3 "memory_operand" ""))
- (set (match_operand 0 "register_operand" "")
- (match_operand 4 "" ""))
- (set (match_operand 2 "register_operand" "")
- (match_operand 5 "" ""))])]
+ [(parallel [(set (match_operand 1 "memory_operand")
+ (match_operand 3 "memory_operand"))
+ (set (match_operand 0 "register_operand")
+ (match_operand 4))
+ (set (match_operand 2 "register_operand")
+ (match_operand 5))])]
""
"ix86_current_function_needs_cld = 1;")
(set_attr "mode" "QI")])
(define_expand "rep_mov"
- [(parallel [(set (match_operand 4 "register_operand" "") (const_int 0))
- (set (match_operand 0 "register_operand" "")
- (match_operand 5 "" ""))
- (set (match_operand 2 "register_operand" "")
- (match_operand 6 "" ""))
- (set (match_operand 1 "memory_operand" "")
- (match_operand 3 "memory_operand" ""))
+ [(parallel [(set (match_operand 4 "register_operand") (const_int 0))
+ (set (match_operand 0 "register_operand")
+ (match_operand 5))
+ (set (match_operand 2 "register_operand")
+ (match_operand 6))
+ (set (match_operand 1 "memory_operand")
+ (match_operand 3 "memory_operand"))
(use (match_dup 4))])]
""
"ix86_current_function_needs_cld = 1;")
(set_attr "mode" "QI")])
(define_expand "setmem<mode>"
- [(use (match_operand:BLK 0 "memory_operand" ""))
- (use (match_operand:SWI48 1 "nonmemory_operand" ""))
- (use (match_operand:QI 2 "nonmemory_operand" ""))
- (use (match_operand 3 "const_int_operand" ""))
- (use (match_operand:SI 4 "const_int_operand" ""))
- (use (match_operand:SI 5 "const_int_operand" ""))]
+ [(use (match_operand:BLK 0 "memory_operand"))
+ (use (match_operand:SWI48 1 "nonmemory_operand"))
+ (use (match_operand:QI 2 "nonmemory_operand"))
+ (use (match_operand 3 "const_int_operand"))
+ (use (match_operand:SI 4 "const_int_operand"))
+ (use (match_operand:SI 5 "const_int_operand"))]
""
{
if (ix86_expand_setmem (operands[0], operands[1],
;; Handle this case here to simplify previous expander.
(define_expand "strset"
- [(set (match_operand 1 "memory_operand" "")
- (match_operand 2 "register_operand" ""))
- (parallel [(set (match_operand 0 "register_operand" "")
+ [(set (match_operand 1 "memory_operand")
+ (match_operand 2 "register_operand"))
+ (parallel [(set (match_operand 0 "register_operand")
(match_dup 3))
(clobber (reg:CC FLAGS_REG))])]
""
})
(define_expand "strset_singleop"
- [(parallel [(set (match_operand 1 "memory_operand" "")
- (match_operand 2 "register_operand" ""))
- (set (match_operand 0 "register_operand" "")
- (match_operand 3 "" ""))])]
+ [(parallel [(set (match_operand 1 "memory_operand")
+ (match_operand 2 "register_operand"))
+ (set (match_operand 0 "register_operand")
+ (match_operand 3))])]
""
"ix86_current_function_needs_cld = 1;")
(set_attr "mode" "QI")])
(define_expand "rep_stos"
- [(parallel [(set (match_operand 1 "register_operand" "") (const_int 0))
- (set (match_operand 0 "register_operand" "")
- (match_operand 4 "" ""))
- (set (match_operand 2 "memory_operand" "") (const_int 0))
- (use (match_operand 3 "register_operand" ""))
+ [(parallel [(set (match_operand 1 "register_operand") (const_int 0))
+ (set (match_operand 0 "register_operand")
+ (match_operand 4))
+ (set (match_operand 2 "memory_operand") (const_int 0))
+ (use (match_operand 3 "register_operand"))
(use (match_dup 1))])]
""
"ix86_current_function_needs_cld = 1;")
(set_attr "mode" "QI")])
(define_expand "cmpstrnsi"
- [(set (match_operand:SI 0 "register_operand" "")
- (compare:SI (match_operand:BLK 1 "general_operand" "")
- (match_operand:BLK 2 "general_operand" "")))
- (use (match_operand 3 "general_operand" ""))
- (use (match_operand 4 "immediate_operand" ""))]
+ [(set (match_operand:SI 0 "register_operand")
+ (compare:SI (match_operand:BLK 1 "general_operand")
+ (match_operand:BLK 2 "general_operand")))
+ (use (match_operand 3 "general_operand"))
+ (use (match_operand 4 "immediate_operand"))]
""
{
rtx addr1, addr2, out, outlow, count, countreg, align;
(gtu:QI (reg:CC FLAGS_REG) (const_int 0)))
(set (match_dup 2)
(ltu:QI (reg:CC FLAGS_REG) (const_int 0)))
- (parallel [(set (match_operand:QI 0 "register_operand" "")
+ (parallel [(set (match_operand:QI 0 "register_operand")
(minus:QI (match_dup 1)
(match_dup 2)))
(clobber (reg:CC FLAGS_REG))])]
(define_expand "cmpstrnqi_nz_1"
[(parallel [(set (reg:CC FLAGS_REG)
- (compare:CC (match_operand 4 "memory_operand" "")
- (match_operand 5 "memory_operand" "")))
- (use (match_operand 2 "register_operand" ""))
- (use (match_operand:SI 3 "immediate_operand" ""))
- (clobber (match_operand 0 "register_operand" ""))
- (clobber (match_operand 1 "register_operand" ""))
+ (compare:CC (match_operand 4 "memory_operand")
+ (match_operand 5 "memory_operand")))
+ (use (match_operand 2 "register_operand"))
+ (use (match_operand:SI 3 "immediate_operand"))
+ (clobber (match_operand 0 "register_operand"))
+ (clobber (match_operand 1 "register_operand"))
(clobber (match_dup 2))])]
""
"ix86_current_function_needs_cld = 1;")
(define_expand "cmpstrnqi_1"
[(parallel [(set (reg:CC FLAGS_REG)
- (if_then_else:CC (ne (match_operand 2 "register_operand" "")
+ (if_then_else:CC (ne (match_operand 2 "register_operand")
(const_int 0))
- (compare:CC (match_operand 4 "memory_operand" "")
- (match_operand 5 "memory_operand" ""))
+ (compare:CC (match_operand 4 "memory_operand")
+ (match_operand 5 "memory_operand"))
(const_int 0)))
- (use (match_operand:SI 3 "immediate_operand" ""))
+ (use (match_operand:SI 3 "immediate_operand"))
(use (reg:CC FLAGS_REG))
- (clobber (match_operand 0 "register_operand" ""))
- (clobber (match_operand 1 "register_operand" ""))
+ (clobber (match_operand 0 "register_operand"))
+ (clobber (match_operand 1 "register_operand"))
(clobber (match_dup 2))])]
""
"ix86_current_function_needs_cld = 1;")
(set_attr "prefix_rep" "1")])
(define_expand "strlen<mode>"
- [(set (match_operand:P 0 "register_operand" "")
- (unspec:P [(match_operand:BLK 1 "general_operand" "")
- (match_operand:QI 2 "immediate_operand" "")
- (match_operand 3 "immediate_operand" "")]
+ [(set (match_operand:P 0 "register_operand")
+ (unspec:P [(match_operand:BLK 1 "general_operand")
+ (match_operand:QI 2 "immediate_operand")
+ (match_operand 3 "immediate_operand")]
UNSPEC_SCAS))]
""
{
})
(define_expand "strlenqi_1"
- [(parallel [(set (match_operand 0 "register_operand" "")
- (match_operand 2 "" ""))
- (clobber (match_operand 1 "register_operand" ""))
+ [(parallel [(set (match_operand 0 "register_operand")
+ (match_operand 2))
+ (clobber (match_operand 1 "register_operand"))
(clobber (reg:CC FLAGS_REG))])]
""
"ix86_current_function_needs_cld = 1;")
(define_peephole2
[(parallel[
(set (reg:CC FLAGS_REG)
- (compare:CC (mem:BLK (match_operand 4 "register_operand" ""))
- (mem:BLK (match_operand 5 "register_operand" ""))))
- (use (match_operand 6 "register_operand" ""))
- (use (match_operand:SI 3 "immediate_operand" ""))
- (clobber (match_operand 0 "register_operand" ""))
- (clobber (match_operand 1 "register_operand" ""))
- (clobber (match_operand 2 "register_operand" ""))])
- (set (match_operand:QI 7 "register_operand" "")
+ (compare:CC (mem:BLK (match_operand 4 "register_operand"))
+ (mem:BLK (match_operand 5 "register_operand"))))
+ (use (match_operand 6 "register_operand"))
+ (use (match_operand:SI 3 "immediate_operand"))
+ (clobber (match_operand 0 "register_operand"))
+ (clobber (match_operand 1 "register_operand"))
+ (clobber (match_operand 2 "register_operand"))])
+ (set (match_operand:QI 7 "register_operand")
(gtu:QI (reg:CC FLAGS_REG) (const_int 0)))
- (set (match_operand:QI 8 "register_operand" "")
+ (set (match_operand:QI 8 "register_operand")
(ltu:QI (reg:CC FLAGS_REG) (const_int 0)))
(set (reg FLAGS_REG)
(compare (match_dup 7) (match_dup 8)))
(define_peephole2
[(parallel[
(set (reg:CC FLAGS_REG)
- (if_then_else:CC (ne (match_operand 6 "register_operand" "")
+ (if_then_else:CC (ne (match_operand 6 "register_operand")
(const_int 0))
- (compare:CC (mem:BLK (match_operand 4 "register_operand" ""))
- (mem:BLK (match_operand 5 "register_operand" "")))
+ (compare:CC (mem:BLK (match_operand 4 "register_operand"))
+ (mem:BLK (match_operand 5 "register_operand")))
(const_int 0)))
- (use (match_operand:SI 3 "immediate_operand" ""))
+ (use (match_operand:SI 3 "immediate_operand"))
(use (reg:CC FLAGS_REG))
- (clobber (match_operand 0 "register_operand" ""))
- (clobber (match_operand 1 "register_operand" ""))
- (clobber (match_operand 2 "register_operand" ""))])
- (set (match_operand:QI 7 "register_operand" "")
+ (clobber (match_operand 0 "register_operand"))
+ (clobber (match_operand 1 "register_operand"))
+ (clobber (match_operand 2 "register_operand"))])
+ (set (match_operand:QI 7 "register_operand")
(gtu:QI (reg:CC FLAGS_REG) (const_int 0)))
- (set (match_operand:QI 8 "register_operand" "")
+ (set (match_operand:QI 8 "register_operand")
(ltu:QI (reg:CC FLAGS_REG) (const_int 0)))
(set (reg FLAGS_REG)
(compare (match_dup 7) (match_dup 8)))
;; Conditional move instructions.
(define_expand "mov<mode>cc"
- [(set (match_operand:SWIM 0 "register_operand" "")
- (if_then_else:SWIM (match_operand 1 "ordered_comparison_operator" "")
- (match_operand:SWIM 2 "<general_operand>" "")
- (match_operand:SWIM 3 "<general_operand>" "")))]
+ [(set (match_operand:SWIM 0 "register_operand")
+ (if_then_else:SWIM (match_operand 1 "ordered_comparison_operator")
+ (match_operand:SWIM 2 "<general_operand>")
+ (match_operand:SWIM 3 "<general_operand>")))]
""
"if (ix86_expand_int_movcc (operands)) DONE; else FAIL;")
(define_expand "x86_mov<mode>cc_0_m1"
[(parallel
- [(set (match_operand:SWI48 0 "register_operand" "")
+ [(set (match_operand:SWI48 0 "register_operand")
(if_then_else:SWI48
(match_operator:SWI48 2 "ix86_carry_flag_operator"
- [(match_operand 1 "flags_reg_operand" "")
+ [(match_operand 1 "flags_reg_operand")
(const_int 0)])
(const_int -1)
(const_int 0)))
(define_insn_and_split "*movqicc_noc"
[(set (match_operand:QI 0 "register_operand" "=r,r")
(if_then_else:QI (match_operator 1 "ix86_comparison_operator"
- [(match_operand 4 "flags_reg_operand" "")
+ [(match_operand 4 "flags_reg_operand")
(const_int 0)])
(match_operand:QI 2 "register_operand" "r,0")
(match_operand:QI 3 "register_operand" "0,r")))]
(set_attr "mode" "SI")])
(define_expand "mov<mode>cc"
- [(set (match_operand:X87MODEF 0 "register_operand" "")
+ [(set (match_operand:X87MODEF 0 "register_operand")
(if_then_else:X87MODEF
- (match_operand 1 "ix86_fp_comparison_operator" "")
- (match_operand:X87MODEF 2 "register_operand" "")
- (match_operand:X87MODEF 3 "register_operand" "")))]
+ (match_operand 1 "ix86_fp_comparison_operator")
+ (match_operand:X87MODEF 2 "register_operand")
+ (match_operand:X87MODEF 3 "register_operand")))]
"(TARGET_80387 && TARGET_CMOVE)
|| (SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH)"
"if (ix86_expand_fp_movcc (operands)) DONE; else FAIL;")
(set_attr "mode" "DF,DF,DI,DI")])
(define_split
- [(set (match_operand:DF 0 "register_and_not_any_fp_reg_operand" "")
+ [(set (match_operand:DF 0 "register_and_not_any_fp_reg_operand")
(if_then_else:DF (match_operator 1 "fcmov_comparison_operator"
- [(match_operand 4 "flags_reg_operand" "")
+ [(match_operand 4 "flags_reg_operand")
(const_int 0)])
- (match_operand:DF 2 "nonimmediate_operand" "")
- (match_operand:DF 3 "nonimmediate_operand" "")))]
+ (match_operand:DF 2 "nonimmediate_operand")
+ (match_operand:DF 3 "nonimmediate_operand")))]
"!TARGET_64BIT && reload_completed"
[(set (match_dup 2)
(if_then_else:SI (match_op_dup 1 [(match_dup 4) (const_int 0)])
;;
;; Actually we only match the last two instructions for simplicity.
(define_peephole2
- [(set (match_operand 0 "fp_register_operand" "")
- (match_operand 1 "fp_register_operand" ""))
+ [(set (match_operand 0 "fp_register_operand")
+ (match_operand 1 "fp_register_operand"))
(set (match_dup 0)
(match_operator 2 "binary_fp_operator"
[(match_dup 0)
- (match_operand 3 "memory_operand" "")]))]
+ (match_operand 3 "memory_operand")]))]
"REGNO (operands[0]) != REGNO (operands[1])"
[(set (match_dup 0) (match_dup 3))
(set (match_dup 0) (match_dup 4))]
;; Conditional addition patterns
(define_expand "add<mode>cc"
- [(match_operand:SWI 0 "register_operand" "")
- (match_operand 1 "ordered_comparison_operator" "")
- (match_operand:SWI 2 "register_operand" "")
- (match_operand:SWI 3 "const_int_operand" "")]
+ [(match_operand:SWI 0 "register_operand")
+ (match_operand 1 "ordered_comparison_operator")
+ (match_operand:SWI 2 "register_operand")
+ (match_operand:SWI 3 "const_int_operand")]
""
"if (ix86_expand_int_addcc (operands)) DONE; else FAIL;")
\f
(cond [(and (eq_attr "alternative" "0")
(not (match_test "TARGET_OPT_AGU")))
(const_string "alu")
- (match_operand:<MODE> 2 "const0_operand" "")
+ (match_operand:<MODE> 2 "const0_operand")
(const_string "imov")
]
(const_string "lea")))
(cond [(eq_attr "type" "imov")
(const_string "0")
(and (eq_attr "type" "alu")
- (match_operand 2 "const128_operand" ""))
+ (match_operand 2 "const128_operand"))
(const_string "1")
]
(const_string "*")))
(set_attr "length" "5")])
(define_expand "allocate_stack"
- [(match_operand 0 "register_operand" "")
- (match_operand 1 "general_operand" "")]
+ [(match_operand 0 "register_operand")
+ (match_operand 1 "general_operand")]
"ix86_target_stack_probe ()"
{
rtx x;
;; Use IOR for stack probes, this is shorter.
(define_expand "probe_stack"
- [(match_operand 0 "memory_operand" "")]
+ [(match_operand 0 "memory_operand")]
""
{
rtx (*gen_ior3) (rtx, rtx, rtx);
[(set_attr "type" "multi")])
(define_expand "builtin_setjmp_receiver"
- [(label_ref (match_operand 0 "" ""))]
+ [(label_ref (match_operand 0))]
"!TARGET_64BIT && flag_pic"
{
#if TARGET_MACHO
;; Avoid redundant prefixes by splitting HImode arithmetic to SImode.
(define_split
- [(set (match_operand 0 "register_operand" "")
+ [(set (match_operand 0 "register_operand")
(match_operator 3 "promotable_binary_operator"
- [(match_operand 1 "register_operand" "")
- (match_operand 2 "aligned_operand" "")]))
+ [(match_operand 1 "register_operand")
+ (match_operand 2 "aligned_operand")]))
(clobber (reg:CC FLAGS_REG))]
"! TARGET_PARTIAL_REG_STALL && reload_completed
&& ((GET_MODE (operands[0]) == HImode
; instruction size is unchanged, except in the %eax case for
; which it is increased by one byte, hence the ! optimize_size.
(define_split
- [(set (match_operand 0 "flags_reg_operand" "")
+ [(set (match_operand 0 "flags_reg_operand")
(match_operator 2 "compare_operator"
- [(and (match_operand 3 "aligned_operand" "")
- (match_operand 4 "const_int_operand" ""))
+ [(and (match_operand 3 "aligned_operand")
+ (match_operand 4 "const_int_operand"))
(const_int 0)]))
- (set (match_operand 1 "register_operand" "")
+ (set (match_operand 1 "register_operand")
(and (match_dup 3) (match_dup 4)))]
"! TARGET_PARTIAL_REG_STALL && reload_completed
&& optimize_insn_for_speed_p ()
; the instruction size would at least double, which is not what we
; want even with ! optimize_size.
(define_split
- [(set (match_operand 0 "flags_reg_operand" "")
+ [(set (match_operand 0 "flags_reg_operand")
(match_operator 1 "compare_operator"
- [(and (match_operand:HI 2 "aligned_operand" "")
- (match_operand:HI 3 "const_int_operand" ""))
+ [(and (match_operand:HI 2 "aligned_operand")
+ (match_operand:HI 3 "const_int_operand"))
(const_int 0)]))]
"! TARGET_PARTIAL_REG_STALL && reload_completed
&& ! TARGET_FAST_PREFIX
})
(define_split
- [(set (match_operand 0 "register_operand" "")
- (neg (match_operand 1 "register_operand" "")))
+ [(set (match_operand 0 "register_operand")
+ (neg (match_operand 1 "register_operand")))
(clobber (reg:CC FLAGS_REG))]
"! TARGET_PARTIAL_REG_STALL && reload_completed
&& (GET_MODE (operands[0]) == HImode
})
(define_split
- [(set (match_operand 0 "register_operand" "")
- (not (match_operand 1 "register_operand" "")))]
+ [(set (match_operand 0 "register_operand")
+ (not (match_operand 1 "register_operand")))]
"! TARGET_PARTIAL_REG_STALL && reload_completed
&& (GET_MODE (operands[0]) == HImode
|| (GET_MODE (operands[0]) == QImode
})
(define_split
- [(set (match_operand 0 "register_operand" "")
+ [(set (match_operand 0 "register_operand")
(if_then_else (match_operator 1 "ordered_comparison_operator"
[(reg FLAGS_REG) (const_int 0)])
- (match_operand 2 "register_operand" "")
- (match_operand 3 "register_operand" "")))]
+ (match_operand 2 "register_operand")
+ (match_operand 3 "register_operand")))]
"! TARGET_PARTIAL_REG_STALL && TARGET_CMOVE
&& (GET_MODE (operands[0]) == HImode
|| (GET_MODE (operands[0]) == QImode
;; Don't push memory operands
(define_peephole2
- [(set (match_operand:SWI 0 "push_operand" "")
- (match_operand:SWI 1 "memory_operand" ""))
+ [(set (match_operand:SWI 0 "push_operand")
+ (match_operand:SWI 1 "memory_operand"))
(match_scratch:SWI 2 "<r>")]
"!(TARGET_PUSH_MEMORY || optimize_insn_for_size_p ())
&& !RTX_FRAME_RELATED_P (peep2_next_insn (0))"
;; We need to handle SFmode only, because DFmode and XFmode are split to
;; SImode pushes.
(define_peephole2
- [(set (match_operand:SF 0 "push_operand" "")
- (match_operand:SF 1 "memory_operand" ""))
+ [(set (match_operand:SF 0 "push_operand")
+ (match_operand:SF 1 "memory_operand"))
(match_scratch:SF 2 "r")]
"!(TARGET_PUSH_MEMORY || optimize_insn_for_size_p ())
&& !RTX_FRAME_RELATED_P (peep2_next_insn (0))"
;; gets too big.
(define_peephole2
[(match_scratch:SWI124 1 "<r>")
- (set (match_operand:SWI124 0 "memory_operand" "")
+ (set (match_operand:SWI124 0 "memory_operand")
(const_int 0))]
"optimize_insn_for_speed_p ()
&& !TARGET_USE_MOV0
(define_peephole2
[(match_scratch:SWI124 2 "<r>")
- (set (match_operand:SWI124 0 "memory_operand" "")
- (match_operand:SWI124 1 "immediate_operand" ""))]
+ (set (match_operand:SWI124 0 "memory_operand")
+ (match_operand:SWI124 1 "immediate_operand"))]
"optimize_insn_for_speed_p ()
&& TARGET_SPLIT_LONG_MOVES
&& get_attr_length (insn) >= ix86_cur_cost ()->large_insn"
;; Don't compare memory with zero, load and use a test instead.
(define_peephole2
- [(set (match_operand 0 "flags_reg_operand" "")
+ [(set (match_operand 0 "flags_reg_operand")
(match_operator 1 "compare_operator"
- [(match_operand:SI 2 "memory_operand" "")
+ [(match_operand:SI 2 "memory_operand")
(const_int 0)]))
(match_scratch:SI 3 "r")]
"optimize_insn_for_speed_p () && ix86_match_ccmode (insn, CCNOmode)"
;; lifetime information then.
(define_peephole2
- [(set (match_operand:SWI124 0 "nonimmediate_operand" "")
- (not:SWI124 (match_operand:SWI124 1 "nonimmediate_operand" "")))]
+ [(set (match_operand:SWI124 0 "nonimmediate_operand")
+ (not:SWI124 (match_operand:SWI124 1 "nonimmediate_operand")))]
"optimize_insn_for_speed_p ()
&& ((TARGET_NOT_UNPAIRABLE
&& (!MEM_P (operands[0])
;; versions if we're concerned about partial register stalls.
(define_peephole2
- [(set (match_operand 0 "flags_reg_operand" "")
+ [(set (match_operand 0 "flags_reg_operand")
(match_operator 1 "compare_operator"
- [(and:SI (match_operand:SI 2 "register_operand" "")
- (match_operand:SI 3 "immediate_operand" ""))
+ [(and:SI (match_operand:SI 2 "register_operand")
+ (match_operand:SI 3 "immediate_operand"))
(const_int 0)]))]
"ix86_match_ccmode (insn, CCNOmode)
&& (true_regnum (operands[2]) != AX_REG
;; on ! TARGET_PARTIAL_REG_STALL
(define_peephole2
- [(set (match_operand 0 "flags_reg_operand" "")
+ [(set (match_operand 0 "flags_reg_operand")
(match_operator 1 "compare_operator"
- [(and:QI (match_operand:QI 2 "register_operand" "")
- (match_operand:QI 3 "immediate_operand" ""))
+ [(and:QI (match_operand:QI 2 "register_operand")
+ (match_operand:QI 3 "immediate_operand"))
(const_int 0)]))]
"! TARGET_PARTIAL_REG_STALL
&& ix86_match_ccmode (insn, CCNOmode)
(and:QI (match_dup 2) (match_dup 3)))])])
(define_peephole2
- [(set (match_operand 0 "flags_reg_operand" "")
+ [(set (match_operand 0 "flags_reg_operand")
(match_operator 1 "compare_operator"
[(and:SI
(zero_extract:SI
- (match_operand 2 "ext_register_operand" "")
+ (match_operand 2 "ext_register_operand")
(const_int 8)
(const_int 8))
- (match_operand 3 "const_int_operand" ""))
+ (match_operand 3 "const_int_operand"))
(const_int 0)]))]
"! TARGET_PARTIAL_REG_STALL
&& ix86_match_ccmode (insn, CCNOmode)
;; Don't do logical operations with memory inputs.
(define_peephole2
[(match_scratch:SI 2 "r")
- (parallel [(set (match_operand:SI 0 "register_operand" "")
+ (parallel [(set (match_operand:SI 0 "register_operand")
(match_operator:SI 3 "arith_or_logical_operator"
[(match_dup 0)
- (match_operand:SI 1 "memory_operand" "")]))
+ (match_operand:SI 1 "memory_operand")]))
(clobber (reg:CC FLAGS_REG))])]
"!(TARGET_READ_MODIFY || optimize_insn_for_size_p ())"
[(set (match_dup 2) (match_dup 1))
(define_peephole2
[(match_scratch:SI 2 "r")
- (parallel [(set (match_operand:SI 0 "register_operand" "")
+ (parallel [(set (match_operand:SI 0 "register_operand")
(match_operator:SI 3 "arith_or_logical_operator"
- [(match_operand:SI 1 "memory_operand" "")
+ [(match_operand:SI 1 "memory_operand")
(match_dup 0)]))
(clobber (reg:CC FLAGS_REG))])]
"!(TARGET_READ_MODIFY || optimize_insn_for_size_p ())"
;; refers to the destination of the load!
(define_peephole2
- [(set (match_operand:SI 0 "register_operand" "")
- (match_operand:SI 1 "register_operand" ""))
+ [(set (match_operand:SI 0 "register_operand")
+ (match_operand:SI 1 "register_operand"))
(parallel [(set (match_dup 0)
(match_operator:SI 3 "commutative_operator"
[(match_dup 0)
- (match_operand:SI 2 "memory_operand" "")]))
+ (match_operand:SI 2 "memory_operand")]))
(clobber (reg:CC FLAGS_REG))])]
"REGNO (operands[0]) != REGNO (operands[1])
&& GENERAL_REGNO_P (REGNO (operands[0]))
"operands[4] = replace_rtx (operands[2], operands[0], operands[1]);")
(define_peephole2
- [(set (match_operand 0 "register_operand" "")
- (match_operand 1 "register_operand" ""))
+ [(set (match_operand 0 "register_operand")
+ (match_operand 1 "register_operand"))
(set (match_dup 0)
(match_operator 3 "commutative_operator"
[(match_dup 0)
- (match_operand 2 "memory_operand" "")]))]
+ (match_operand 2 "memory_operand")]))]
"REGNO (operands[0]) != REGNO (operands[1])
&& ((MMX_REG_P (operands[0]) && MMX_REG_P (operands[1]))
|| (SSE_REG_P (operands[0]) && SSE_REG_P (operands[1])))"
(define_peephole2
[(match_scratch:SI 2 "r")
- (parallel [(set (match_operand:SI 0 "memory_operand" "")
+ (parallel [(set (match_operand:SI 0 "memory_operand")
(match_operator:SI 3 "arith_or_logical_operator"
[(match_dup 0)
- (match_operand:SI 1 "nonmemory_operand" "")]))
+ (match_operand:SI 1 "nonmemory_operand")]))
(clobber (reg:CC FLAGS_REG))])]
"!(TARGET_READ_MODIFY_WRITE || optimize_insn_for_size_p ())
/* Do not split stack checking probes. */
(define_peephole2
[(match_scratch:SI 2 "r")
- (parallel [(set (match_operand:SI 0 "memory_operand" "")
+ (parallel [(set (match_operand:SI 0 "memory_operand")
(match_operator:SI 3 "arith_or_logical_operator"
- [(match_operand:SI 1 "nonmemory_operand" "")
+ [(match_operand:SI 1 "nonmemory_operand")
(match_dup 0)]))
(clobber (reg:CC FLAGS_REG))])]
"!(TARGET_READ_MODIFY_WRITE || optimize_insn_for_size_p ())
;; Attempt to use arith or logical operations with memory outputs with
;; setting of flags.
(define_peephole2
- [(set (match_operand:SWI 0 "register_operand" "")
- (match_operand:SWI 1 "memory_operand" ""))
+ [(set (match_operand:SWI 0 "register_operand")
+ (match_operand:SWI 1 "memory_operand"))
(parallel [(set (match_dup 0)
(match_operator:SWI 3 "plusminuslogic_operator"
[(match_dup 0)
- (match_operand:SWI 2 "<nonmemory_operand>" "")]))
+ (match_operand:SWI 2 "<nonmemory_operand>")]))
(clobber (reg:CC FLAGS_REG))])
(set (match_dup 1) (match_dup 0))
(set (reg FLAGS_REG) (compare (match_dup 0) (const_int 0)))]
})
(define_peephole2
- [(parallel [(set (match_operand:SWI 0 "register_operand" "")
+ [(parallel [(set (match_operand:SWI 0 "register_operand")
(match_operator:SWI 2 "plusminuslogic_operator"
[(match_dup 0)
- (match_operand:SWI 1 "memory_operand" "")]))
+ (match_operand:SWI 1 "memory_operand")]))
(clobber (reg:CC FLAGS_REG))])
(set (match_dup 1) (match_dup 0))
(set (reg FLAGS_REG) (compare (match_dup 0) (const_int 0)))]
})
(define_peephole2
- [(set (match_operand:SWI12 0 "register_operand" "")
- (match_operand:SWI12 1 "memory_operand" ""))
- (parallel [(set (match_operand:SI 4 "register_operand" "")
+ [(set (match_operand:SWI12 0 "register_operand")
+ (match_operand:SWI12 1 "memory_operand"))
+ (parallel [(set (match_operand:SI 4 "register_operand")
(match_operator:SI 3 "plusminuslogic_operator"
[(match_dup 4)
- (match_operand:SI 2 "nonmemory_operand" "")]))
+ (match_operand:SI 2 "nonmemory_operand")]))
(clobber (reg:CC FLAGS_REG))])
(set (match_dup 1) (match_dup 0))
(set (reg FLAGS_REG) (compare (match_dup 0) (const_int 0)))]
;; Attempt to always use XOR for zeroing registers.
(define_peephole2
- [(set (match_operand 0 "register_operand" "")
- (match_operand 1 "const0_operand" ""))]
+ [(set (match_operand 0 "register_operand")
+ (match_operand 1 "const0_operand"))]
"GET_MODE_SIZE (GET_MODE (operands[0])) <= UNITS_PER_WORD
&& (! TARGET_USE_MOV0 || optimize_insn_for_size_p ())
&& GENERAL_REG_P (operands[0])
"operands[0] = gen_lowpart (word_mode, operands[0]);")
(define_peephole2
- [(set (strict_low_part (match_operand 0 "register_operand" ""))
+ [(set (strict_low_part (match_operand 0 "register_operand"))
(const_int 0))]
"(GET_MODE (operands[0]) == QImode
|| GET_MODE (operands[0]) == HImode)
;; For HI, SI and DI modes, or $-1,reg is smaller than mov $-1,reg.
(define_peephole2
- [(set (match_operand:SWI248 0 "register_operand" "")
+ [(set (match_operand:SWI248 0 "register_operand")
(const_int -1))]
"(optimize_insn_for_size_p () || TARGET_MOVE_M1_VIA_OR)
&& peep2_regno_dead_p (0, FLAGS_REG)"
;; These can be created by move expanders.
(define_peephole2
- [(set (match_operand:SWI48 0 "register_operand" "")
+ [(set (match_operand:SWI48 0 "register_operand")
(plus:SWI48 (match_dup 0)
- (match_operand:SWI48 1 "<nonmemory_operand>" "")))]
+ (match_operand:SWI48 1 "<nonmemory_operand>")))]
"peep2_regno_dead_p (0, FLAGS_REG)"
[(parallel [(set (match_dup 0) (plus:SWI48 (match_dup 0) (match_dup 1)))
(clobber (reg:CC FLAGS_REG))])])
(define_peephole2
- [(set (match_operand:SI 0 "register_operand" "")
- (subreg:SI (plus:DI (match_operand:DI 1 "register_operand" "")
- (match_operand:DI 2 "nonmemory_operand" "")) 0))]
+ [(set (match_operand:SI 0 "register_operand")
+ (subreg:SI (plus:DI (match_operand:DI 1 "register_operand")
+ (match_operand:DI 2 "nonmemory_operand")) 0))]
"TARGET_64BIT
&& peep2_regno_dead_p (0, FLAGS_REG)
&& REGNO (operands[0]) == REGNO (operands[1])"
"operands[2] = gen_lowpart (SImode, operands[2]);")
(define_peephole2
- [(set (match_operand:SWI48 0 "register_operand" "")
+ [(set (match_operand:SWI48 0 "register_operand")
(mult:SWI48 (match_dup 0)
- (match_operand:SWI48 1 "const_int_operand" "")))]
+ (match_operand:SWI48 1 "const_int_operand")))]
"exact_log2 (INTVAL (operands[1])) >= 0
&& peep2_regno_dead_p (0, FLAGS_REG)"
[(parallel [(set (match_dup 0) (ashift:SWI48 (match_dup 0) (match_dup 2)))
"operands[2] = GEN_INT (exact_log2 (INTVAL (operands[1])));")
(define_peephole2
- [(set (match_operand:SI 0 "register_operand" "")
- (subreg:SI (mult:DI (match_operand:DI 1 "register_operand" "")
- (match_operand:DI 2 "const_int_operand" "")) 0))]
+ [(set (match_operand:SI 0 "register_operand")
+ (subreg:SI (mult:DI (match_operand:DI 1 "register_operand")
+ (match_operand:DI 2 "const_int_operand")) 0))]
"TARGET_64BIT
&& exact_log2 (INTVAL (operands[2])) >= 0
&& REGNO (operands[0]) == REGNO (operands[1])
[(match_scratch:W 1 "r")
(parallel [(set (reg:P SP_REG)
(plus:P (reg:P SP_REG)
- (match_operand:P 0 "const_int_operand" "")))
+ (match_operand:P 0 "const_int_operand")))
(clobber (reg:CC FLAGS_REG))
(clobber (mem:BLK (scratch)))])]
"(TARGET_SINGLE_PUSH || optimize_insn_for_size_p ())
[(match_scratch:W 1 "r")
(parallel [(set (reg:P SP_REG)
(plus:P (reg:P SP_REG)
- (match_operand:P 0 "const_int_operand" "")))
+ (match_operand:P 0 "const_int_operand")))
(clobber (reg:CC FLAGS_REG))
(clobber (mem:BLK (scratch)))])]
"(TARGET_DOUBLE_PUSH || optimize_insn_for_size_p ())
[(match_scratch:W 1 "r")
(parallel [(set (reg:P SP_REG)
(plus:P (reg:P SP_REG)
- (match_operand:P 0 "const_int_operand" "")))
+ (match_operand:P 0 "const_int_operand")))
(clobber (reg:CC FLAGS_REG))])]
"(TARGET_SINGLE_PUSH || optimize_insn_for_size_p ())
&& INTVAL (operands[0]) == -GET_MODE_SIZE (word_mode)"
[(match_scratch:W 1 "r")
(parallel [(set (reg:P SP_REG)
(plus:P (reg:P SP_REG)
- (match_operand:P 0 "const_int_operand" "")))
+ (match_operand:P 0 "const_int_operand")))
(clobber (reg:CC FLAGS_REG))])]
"(TARGET_DOUBLE_PUSH || optimize_insn_for_size_p ())
&& INTVAL (operands[0]) == -2*GET_MODE_SIZE (word_mode)"
[(match_scratch:W 1 "r")
(parallel [(set (reg:P SP_REG)
(plus:P (reg:P SP_REG)
- (match_operand:P 0 "const_int_operand" "")))
+ (match_operand:P 0 "const_int_operand")))
(clobber (reg:CC FLAGS_REG))
(clobber (mem:BLK (scratch)))])]
"(TARGET_SINGLE_POP || optimize_insn_for_size_p ())
(match_scratch:W 2 "r")
(parallel [(set (reg:P SP_REG)
(plus:P (reg:P SP_REG)
- (match_operand:P 0 "const_int_operand" "")))
+ (match_operand:P 0 "const_int_operand")))
(clobber (reg:CC FLAGS_REG))
(clobber (mem:BLK (scratch)))])]
"(TARGET_DOUBLE_POP || optimize_insn_for_size_p ())
[(match_scratch:W 1 "r")
(parallel [(set (reg:P SP_REG)
(plus:P (reg:P SP_REG)
- (match_operand:P 0 "const_int_operand" "")))
+ (match_operand:P 0 "const_int_operand")))
(clobber (reg:CC FLAGS_REG))
(clobber (mem:BLK (scratch)))])]
"optimize_insn_for_size_p ()
[(match_scratch:W 1 "r")
(parallel [(set (reg:P SP_REG)
(plus:P (reg:P SP_REG)
- (match_operand:P 0 "const_int_operand" "")))
+ (match_operand:P 0 "const_int_operand")))
(clobber (reg:CC FLAGS_REG))])]
"INTVAL (operands[0]) == GET_MODE_SIZE (word_mode)"
[(set (match_dup 1) (mem:W (post_inc:P (reg:P SP_REG))))])
(match_scratch:W 2 "r")
(parallel [(set (reg:P SP_REG)
(plus:P (reg:P SP_REG)
- (match_operand:P 0 "const_int_operand" "")))
+ (match_operand:P 0 "const_int_operand")))
(clobber (reg:CC FLAGS_REG))])]
"INTVAL (operands[0]) == 2*GET_MODE_SIZE (word_mode)"
[(set (match_dup 1) (mem:W (post_inc:P (reg:P SP_REG))))
[(match_scratch:W 1 "r")
(parallel [(set (reg:P SP_REG)
(plus:P (reg:P SP_REG)
- (match_operand:P 0 "const_int_operand" "")))
+ (match_operand:P 0 "const_int_operand")))
(clobber (reg:CC FLAGS_REG))])]
"optimize_insn_for_size_p ()
&& INTVAL (operands[0]) == 2*GET_MODE_SIZE (word_mode)"
;; Convert compares with 1 to shorter inc/dec operations when CF is not
;; required and register dies. Similarly for 128 to -128.
(define_peephole2
- [(set (match_operand 0 "flags_reg_operand" "")
+ [(set (match_operand 0 "flags_reg_operand")
(match_operator 1 "compare_operator"
- [(match_operand 2 "register_operand" "")
- (match_operand 3 "const_int_operand" "")]))]
+ [(match_operand 2 "register_operand")
+ (match_operand 3 "const_int_operand")]))]
"(((!TARGET_FUSE_CMP_AND_BRANCH || optimize_insn_for_size_p ())
&& incdec_operand (operands[3], GET_MODE (operands[3])))
|| (!TARGET_FUSE_CMP_AND_BRANCH
;; Convert imul by three, five and nine into lea
(define_peephole2
[(parallel
- [(set (match_operand:SWI48 0 "register_operand" "")
- (mult:SWI48 (match_operand:SWI48 1 "register_operand" "")
- (match_operand:SWI48 2 "const359_operand" "")))
+ [(set (match_operand:SWI48 0 "register_operand")
+ (mult:SWI48 (match_operand:SWI48 1 "register_operand")
+ (match_operand:SWI48 2 "const359_operand")))
(clobber (reg:CC FLAGS_REG))])]
"!TARGET_PARTIAL_REG_STALL
|| <MODE>mode == SImode
(define_peephole2
[(parallel
- [(set (match_operand:SWI48 0 "register_operand" "")
- (mult:SWI48 (match_operand:SWI48 1 "nonimmediate_operand" "")
- (match_operand:SWI48 2 "const359_operand" "")))
+ [(set (match_operand:SWI48 0 "register_operand")
+ (mult:SWI48 (match_operand:SWI48 1 "nonimmediate_operand")
+ (match_operand:SWI48 2 "const359_operand")))
(clobber (reg:CC FLAGS_REG))])]
"optimize_insn_for_speed_p ()
&& (!TARGET_PARTIAL_REG_STALL || <MODE>mode == SImode)"
;; imul $32bit_imm, reg, reg is direct decoded.
(define_peephole2
[(match_scratch:SWI48 3 "r")
- (parallel [(set (match_operand:SWI48 0 "register_operand" "")
- (mult:SWI48 (match_operand:SWI48 1 "memory_operand" "")
- (match_operand:SWI48 2 "immediate_operand" "")))
+ (parallel [(set (match_operand:SWI48 0 "register_operand")
+ (mult:SWI48 (match_operand:SWI48 1 "memory_operand")
+ (match_operand:SWI48 2 "immediate_operand")))
(clobber (reg:CC FLAGS_REG))])]
"TARGET_SLOW_IMUL_IMM32_MEM && optimize_insn_for_speed_p ()
&& !satisfies_constraint_K (operands[2])"
(define_peephole2
[(match_scratch:SI 3 "r")
- (parallel [(set (match_operand:DI 0 "register_operand" "")
+ (parallel [(set (match_operand:DI 0 "register_operand")
(zero_extend:DI
- (mult:SI (match_operand:SI 1 "memory_operand" "")
- (match_operand:SI 2 "immediate_operand" ""))))
+ (mult:SI (match_operand:SI 1 "memory_operand")
+ (match_operand:SI 2 "immediate_operand"))))
(clobber (reg:CC FLAGS_REG))])]
"TARGET_64BIT
&& TARGET_SLOW_IMUL_IMM32_MEM && optimize_insn_for_speed_p ()
;; It would be better to force assembler to encode instruction using long
;; immediate, but there is apparently no way to do so.
(define_peephole2
- [(parallel [(set (match_operand:SWI248 0 "register_operand" "")
+ [(parallel [(set (match_operand:SWI248 0 "register_operand")
(mult:SWI248
- (match_operand:SWI248 1 "nonimmediate_operand" "")
- (match_operand:SWI248 2 "const_int_operand" "")))
+ (match_operand:SWI248 1 "nonimmediate_operand")
+ (match_operand:SWI248 2 "const_int_operand")))
(clobber (reg:CC FLAGS_REG))])
(match_scratch:SWI248 3 "r")]
"TARGET_SLOW_IMUL_IMM8 && optimize_insn_for_speed_p ()
(define_peephole2
[(match_scratch:W 5 "r")
- (parallel [(set (match_operand 0 "register_operand" "")
- (ashift (match_operand 1 "register_operand" "")
- (match_operand 2 "const_int_operand" "")))
+ (parallel [(set (match_operand 0 "register_operand")
+ (ashift (match_operand 1 "register_operand")
+ (match_operand 2 "const_int_operand")))
(clobber (reg:CC FLAGS_REG))])
- (parallel [(set (match_operand 3 "register_operand" "")
+ (parallel [(set (match_operand 3 "register_operand")
(plus (match_dup 0)
- (match_operand 4 "x86_64_general_operand" "")))
+ (match_operand 4 "x86_64_general_operand")))
(clobber (reg:CC FLAGS_REG))])]
"IN_RANGE (INTVAL (operands[2]), 1, 3)
/* Validate MODE for lea. */
[(set_attr "length" "2")])
(define_expand "prefetch"
- [(prefetch (match_operand 0 "address_operand" "")
- (match_operand:SI 1 "const_int_operand" "")
- (match_operand:SI 2 "const_int_operand" ""))]
+ [(prefetch (match_operand 0 "address_operand")
+ (match_operand:SI 1 "const_int_operand")
+ (match_operand:SI 2 "const_int_operand"))]
"TARGET_PREFETCH_SSE || TARGET_3DNOW"
{
int rw = INTVAL (operands[1]);
(define_insn "*prefetch_sse_<mode>"
[(prefetch (match_operand:P 0 "address_operand" "p")
(const_int 0)
- (match_operand:SI 1 "const_int_operand" ""))]
+ (match_operand:SI 1 "const_int_operand"))]
"TARGET_PREFETCH_SSE"
{
static const char * const patterns[4] = {
(set_attr "memory" "none")])
(define_expand "stack_protect_set"
- [(match_operand 0 "memory_operand" "")
- (match_operand 1 "memory_operand" "")]
+ [(match_operand 0 "memory_operand")
+ (match_operand 1 "memory_operand")]
""
{
rtx (*insn)(rtx, rtx);
[(set_attr "type" "multi")])
(define_expand "stack_protect_test"
- [(match_operand 0 "memory_operand" "")
- (match_operand 1 "memory_operand" "")
- (match_operand 2 "" "")]
+ [(match_operand 0 "memory_operand")
+ (match_operand 1 "memory_operand")
+ (match_operand 2)]
""
{
rtx flags = gen_rtx_REG (CCZmode, FLAGS_REG);
})
(define_insn "stack_protect_test_<mode>"
- [(set (match_operand:CCZ 0 "flags_reg_operand" "")
+ [(set (match_operand:CCZ 0 "flags_reg_operand")
(unspec:CCZ [(match_operand:PTR 1 "memory_operand" "m")
(match_operand:PTR 2 "memory_operand" "m")]
UNSPEC_SP_TEST))
[(set_attr "type" "multi")])
(define_insn "stack_tls_protect_test_<mode>"
- [(set (match_operand:CCZ 0 "flags_reg_operand" "")
+ [(set (match_operand:CCZ 0 "flags_reg_operand")
(unspec:CCZ [(match_operand:PTR 1 "memory_operand" "m")
(match_operand:PTR 2 "const_int_operand" "i")]
UNSPEC_SP_TLS_TEST))
(set_attr "prefix_rep" "1")
(set_attr "prefix_extra" "1")
(set (attr "prefix_data16")
- (if_then_else (match_operand:HI 2 "" "")
+ (if_then_else (match_operand:HI 2)
(const_string "1")
(const_string "*")))
(set (attr "prefix_rex")
- (if_then_else (match_operand:QI 2 "ext_QIreg_operand" "")
+ (if_then_else (match_operand:QI 2 "ext_QIreg_operand")
(const_string "1")
(const_string "*")))
(set_attr "mode" "SI")])
(set_attr "mode" "DI")])
(define_expand "rdpmc"
- [(match_operand:DI 0 "register_operand" "")
- (match_operand:SI 1 "register_operand" "")]
+ [(match_operand:DI 0 "register_operand")
+ (match_operand:SI 1 "register_operand")]
""
{
rtx reg = gen_reg_rtx (DImode);
(set_attr "length" "2")])
(define_expand "rdtsc"
- [(set (match_operand:DI 0 "register_operand" "")
+ [(set (match_operand:DI 0 "register_operand")
(unspec_volatile:DI [(const_int 0)] UNSPECV_RDTSC))]
""
{
(set_attr "length" "2")])
(define_expand "rdtscp"
- [(match_operand:DI 0 "register_operand" "")
- (match_operand:SI 1 "memory_operand" "")]
+ [(match_operand:DI 0 "register_operand")
+ (match_operand:SI 1 "memory_operand")]
""
{
rtx di = gen_rtx_UNSPEC_VOLATILE (DImode,
;; Use "rep; nop", instead of "pause", to support older assemblers.
;; They have the same encoding.
(define_insn "*pause"
- [(set (match_operand:BLK 0 "" "")
+ [(set (match_operand:BLK 0)
(unspec:BLK [(match_dup 0)] UNSPEC_PAUSE))]
""
"rep; nop"
(set_attr "memory" "unknown")])
(define_expand "xbegin"
- [(set (match_operand:SI 0 "register_operand" "")
+ [(set (match_operand:SI 0 "register_operand")
(unspec_volatile:SI [(match_dup 1)] UNSPECV_XBEGIN))]
"TARGET_RTM"
{
[(set (pc)
(if_then_else (ne (unspec [(const_int 0)] UNSPEC_XBEGIN_ABORT)
(const_int 0))
- (label_ref (match_operand 2 "" ""))
+ (label_ref (match_operand 2))
(pc)))
(set (match_operand:SI 0 "register_operand" "=a")
(unspec_volatile:SI [(match_operand:SI 1 "register_operand" "0")]
(set_attr "length" "3")])
(define_expand "xtest"
- [(set (match_operand:QI 0 "register_operand" "")
+ [(set (match_operand:QI 0 "register_operand")
(unspec_volatile:QI [(const_int 0)] UNSPECV_XTEST))]
"TARGET_RTM"
{
;; This is essential for maintaining stable calling conventions.
(define_expand "mov<mode>"
- [(set (match_operand:V16 0 "nonimmediate_operand" "")
- (match_operand:V16 1 "nonimmediate_operand" ""))]
+ [(set (match_operand:V16 0 "nonimmediate_operand")
+ (match_operand:V16 1 "nonimmediate_operand"))]
"TARGET_SSE"
{
ix86_expand_vector_move (<MODE>mode, operands);
})
(define_split
- [(set (match_operand:V4SF 0 "register_operand" "")
- (match_operand:V4SF 1 "zero_extended_scalar_load_operand" ""))]
+ [(set (match_operand:V4SF 0 "register_operand")
+ (match_operand:V4SF 1 "zero_extended_scalar_load_operand"))]
"TARGET_SSE && reload_completed"
[(set (match_dup 0)
(vec_merge:V4SF
})
(define_split
- [(set (match_operand:V2DF 0 "register_operand" "")
- (match_operand:V2DF 1 "zero_extended_scalar_load_operand" ""))]
+ [(set (match_operand:V2DF 0 "register_operand")
+ (match_operand:V2DF 1 "zero_extended_scalar_load_operand"))]
"TARGET_SSE2 && reload_completed"
[(set (match_dup 0) (vec_concat:V2DF (match_dup 1) (match_dup 2)))]
{
})
(define_expand "push<mode>1"
- [(match_operand:V16 0 "register_operand" "")]
+ [(match_operand:V16 0 "register_operand")]
"TARGET_SSE"
{
ix86_expand_push (<MODE>mode, operands[0]);
})
(define_expand "movmisalign<mode>"
- [(set (match_operand:V16 0 "nonimmediate_operand" "")
- (match_operand:V16 1 "nonimmediate_operand" ""))]
+ [(set (match_operand:V16 0 "nonimmediate_operand")
+ (match_operand:V16 1 "nonimmediate_operand"))]
"TARGET_SSE"
{
ix86_expand_vector_move_misalign (<MODE>mode, operands);
})
(define_expand "<sse>_movu<ssemodesuffix><avxsizesuffix>"
- [(set (match_operand:VF 0 "nonimmediate_operand" "")
+ [(set (match_operand:VF 0 "nonimmediate_operand")
(unspec:VF
- [(match_operand:VF 1 "nonimmediate_operand" "")]
+ [(match_operand:VF 1 "nonimmediate_operand")]
UNSPEC_MOVU))]
"TARGET_SSE"
{
(set_attr "mode" "<MODE>")])
(define_expand "<sse2>_movdqu<avxsizesuffix>"
- [(set (match_operand:VI1 0 "nonimmediate_operand" "")
- (unspec:VI1 [(match_operand:VI1 1 "nonimmediate_operand" "")]
+ [(set (match_operand:VI1 0 "nonimmediate_operand")
+ (unspec:VI1 [(match_operand:VI1 1 "nonimmediate_operand")]
UNSPEC_MOVU))]
"TARGET_SSE2"
{
(V4DF "TARGET_AVX") (V2DF "TARGET_SSE2")])
(define_expand "storent<mode>"
- [(set (match_operand:STORENT_MODE 0 "memory_operand" "")
+ [(set (match_operand:STORENT_MODE 0 "memory_operand")
(unspec:STORENT_MODE
- [(match_operand:STORENT_MODE 1 "register_operand" "")]
+ [(match_operand:STORENT_MODE 1 "register_operand")]
UNSPEC_MOVNT))]
"TARGET_SSE")
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
(define_expand "<code><mode>2"
- [(set (match_operand:VF 0 "register_operand" "")
+ [(set (match_operand:VF 0 "register_operand")
(absneg:VF
- (match_operand:VF 1 "register_operand" "")))]
+ (match_operand:VF 1 "register_operand")))]
"TARGET_SSE"
"ix86_expand_fp_absneg_operator (<CODE>, <MODE>mode, operands); DONE;")
[(set_attr "isa" "noavx,noavx,avx,avx")])
(define_expand "<plusminus_insn><mode>3"
- [(set (match_operand:VF 0 "register_operand" "")
+ [(set (match_operand:VF 0 "register_operand")
(plusminus:VF
- (match_operand:VF 1 "nonimmediate_operand" "")
- (match_operand:VF 2 "nonimmediate_operand" "")))]
+ (match_operand:VF 1 "nonimmediate_operand")
+ (match_operand:VF 2 "nonimmediate_operand")))]
"TARGET_SSE"
"ix86_fixup_binary_operands_no_copy (<CODE>, <MODE>mode, operands);")
(set_attr "mode" "<ssescalarmode>")])
(define_expand "mul<mode>3"
- [(set (match_operand:VF 0 "register_operand" "")
+ [(set (match_operand:VF 0 "register_operand")
(mult:VF
- (match_operand:VF 1 "nonimmediate_operand" "")
- (match_operand:VF 2 "nonimmediate_operand" "")))]
+ (match_operand:VF 1 "nonimmediate_operand")
+ (match_operand:VF 2 "nonimmediate_operand")))]
"TARGET_SSE"
"ix86_fixup_binary_operands_no_copy (MULT, <MODE>mode, operands);")
(set_attr "mode" "<ssescalarmode>")])
(define_expand "div<mode>3"
- [(set (match_operand:VF2 0 "register_operand" "")
- (div:VF2 (match_operand:VF2 1 "register_operand" "")
- (match_operand:VF2 2 "nonimmediate_operand" "")))]
+ [(set (match_operand:VF2 0 "register_operand")
+ (div:VF2 (match_operand:VF2 1 "register_operand")
+ (match_operand:VF2 2 "nonimmediate_operand")))]
"TARGET_SSE2"
"ix86_fixup_binary_operands_no_copy (DIV, <MODE>mode, operands);")
(define_expand "div<mode>3"
- [(set (match_operand:VF1 0 "register_operand" "")
- (div:VF1 (match_operand:VF1 1 "register_operand" "")
- (match_operand:VF1 2 "nonimmediate_operand" "")))]
+ [(set (match_operand:VF1 0 "register_operand")
+ (div:VF1 (match_operand:VF1 1 "register_operand")
+ (match_operand:VF1 2 "nonimmediate_operand")))]
"TARGET_SSE"
{
ix86_fixup_binary_operands_no_copy (DIV, <MODE>mode, operands);
(set_attr "mode" "SF")])
(define_expand "sqrt<mode>2"
- [(set (match_operand:VF2 0 "register_operand" "")
- (sqrt:VF2 (match_operand:VF2 1 "nonimmediate_operand" "")))]
+ [(set (match_operand:VF2 0 "register_operand")
+ (sqrt:VF2 (match_operand:VF2 1 "nonimmediate_operand")))]
"TARGET_SSE2")
(define_expand "sqrt<mode>2"
- [(set (match_operand:VF1 0 "register_operand" "")
- (sqrt:VF1 (match_operand:VF1 1 "nonimmediate_operand" "")))]
+ [(set (match_operand:VF1 0 "register_operand")
+ (sqrt:VF1 (match_operand:VF1 1 "nonimmediate_operand")))]
"TARGET_SSE"
{
if (TARGET_SSE_MATH
(set_attr "mode" "<ssescalarmode>")])
(define_expand "rsqrt<mode>2"
- [(set (match_operand:VF1 0 "register_operand" "")
+ [(set (match_operand:VF1 0 "register_operand")
(unspec:VF1
- [(match_operand:VF1 1 "nonimmediate_operand" "")] UNSPEC_RSQRT))]
+ [(match_operand:VF1 1 "nonimmediate_operand")] UNSPEC_RSQRT))]
"TARGET_SSE_MATH"
{
ix86_emit_swsqrtsf (operands[0], operands[1], <MODE>mode, true);
;; applied to NaNs. Hopefully the optimizers won't get too smart on us.
(define_expand "<code><mode>3"
- [(set (match_operand:VF 0 "register_operand" "")
+ [(set (match_operand:VF 0 "register_operand")
(smaxmin:VF
- (match_operand:VF 1 "nonimmediate_operand" "")
- (match_operand:VF 2 "nonimmediate_operand" "")))]
+ (match_operand:VF 1 "nonimmediate_operand")
+ (match_operand:VF 2 "nonimmediate_operand")))]
"TARGET_SSE"
{
if (!flag_finite_math_only)
(set_attr "mode" "V4SF")])
(define_expand "reduc_splus_v4df"
- [(match_operand:V4DF 0 "register_operand" "")
- (match_operand:V4DF 1 "register_operand" "")]
+ [(match_operand:V4DF 0 "register_operand")
+ (match_operand:V4DF 1 "register_operand")]
"TARGET_AVX"
{
rtx tmp = gen_reg_rtx (V4DFmode);
})
(define_expand "reduc_splus_v2df"
- [(match_operand:V2DF 0 "register_operand" "")
- (match_operand:V2DF 1 "register_operand" "")]
+ [(match_operand:V2DF 0 "register_operand")
+ (match_operand:V2DF 1 "register_operand")]
"TARGET_SSE3"
{
emit_insn (gen_sse3_haddv2df3 (operands[0], operands[1], operands[1]));
})
(define_expand "reduc_splus_v8sf"
- [(match_operand:V8SF 0 "register_operand" "")
- (match_operand:V8SF 1 "register_operand" "")]
+ [(match_operand:V8SF 0 "register_operand")
+ (match_operand:V8SF 1 "register_operand")]
"TARGET_AVX"
{
rtx tmp = gen_reg_rtx (V8SFmode);
})
(define_expand "reduc_splus_v4sf"
- [(match_operand:V4SF 0 "register_operand" "")
- (match_operand:V4SF 1 "register_operand" "")]
+ [(match_operand:V4SF 0 "register_operand")
+ (match_operand:V4SF 1 "register_operand")]
"TARGET_SSE"
{
if (TARGET_SSE3)
(define_expand "reduc_<code>_<mode>"
[(smaxmin:REDUC_SMINMAX_MODE
- (match_operand:REDUC_SMINMAX_MODE 0 "register_operand" "")
- (match_operand:REDUC_SMINMAX_MODE 1 "register_operand" ""))]
+ (match_operand:REDUC_SMINMAX_MODE 0 "register_operand")
+ (match_operand:REDUC_SMINMAX_MODE 1 "register_operand"))]
""
{
ix86_expand_reduc (gen_<code><mode>3, operands[0], operands[1]);
(define_expand "reduc_<code>_<mode>"
[(umaxmin:VI_256
- (match_operand:VI_256 0 "register_operand" "")
- (match_operand:VI_256 1 "register_operand" ""))]
+ (match_operand:VI_256 0 "register_operand")
+ (match_operand:VI_256 1 "register_operand"))]
"TARGET_AVX2"
{
ix86_expand_reduc (gen_<code><mode>3, operands[0], operands[1]);
(define_expand "reduc_umin_v8hi"
[(umin:V8HI
- (match_operand:V8HI 0 "register_operand" "")
- (match_operand:V8HI 1 "register_operand" ""))]
+ (match_operand:V8HI 0 "register_operand")
+ (match_operand:V8HI 1 "register_operand"))]
"TARGET_SSE4_1"
{
ix86_expand_reduc (gen_uminv8hi3, operands[0], operands[1]);
(set_attr "mode" "<MODE>")])
(define_expand "vcond<V_256:mode><VF_256:mode>"
- [(set (match_operand:V_256 0 "register_operand" "")
+ [(set (match_operand:V_256 0 "register_operand")
(if_then_else:V_256
(match_operator 3 ""
- [(match_operand:VF_256 4 "nonimmediate_operand" "")
- (match_operand:VF_256 5 "nonimmediate_operand" "")])
- (match_operand:V_256 1 "general_operand" "")
- (match_operand:V_256 2 "general_operand" "")))]
+ [(match_operand:VF_256 4 "nonimmediate_operand")
+ (match_operand:VF_256 5 "nonimmediate_operand")])
+ (match_operand:V_256 1 "general_operand")
+ (match_operand:V_256 2 "general_operand")))]
"TARGET_AVX
&& (GET_MODE_NUNITS (<V_256:MODE>mode)
== GET_MODE_NUNITS (<VF_256:MODE>mode))"
})
(define_expand "vcond<V_128:mode><VF_128:mode>"
- [(set (match_operand:V_128 0 "register_operand" "")
+ [(set (match_operand:V_128 0 "register_operand")
(if_then_else:V_128
(match_operator 3 ""
- [(match_operand:VF_128 4 "nonimmediate_operand" "")
- (match_operand:VF_128 5 "nonimmediate_operand" "")])
- (match_operand:V_128 1 "general_operand" "")
- (match_operand:V_128 2 "general_operand" "")))]
+ [(match_operand:VF_128 4 "nonimmediate_operand")
+ (match_operand:VF_128 5 "nonimmediate_operand")])
+ (match_operand:V_128 1 "general_operand")
+ (match_operand:V_128 2 "general_operand")))]
"TARGET_SSE
&& (GET_MODE_NUNITS (<V_128:MODE>mode)
== GET_MODE_NUNITS (<VF_128:MODE>mode))"
(set_attr "mode" "<MODE>")])
(define_expand "<code><mode>3"
- [(set (match_operand:VF 0 "register_operand" "")
+ [(set (match_operand:VF 0 "register_operand")
(any_logic:VF
- (match_operand:VF 1 "nonimmediate_operand" "")
- (match_operand:VF 2 "nonimmediate_operand" "")))]
+ (match_operand:VF 1 "nonimmediate_operand")
+ (match_operand:VF 2 "nonimmediate_operand")))]
"TARGET_SSE"
"ix86_fixup_binary_operands_no_copy (<CODE>, <MODE>mode, operands);")
[(set (match_dup 4)
(and:VF
(not:VF (match_dup 3))
- (match_operand:VF 1 "nonimmediate_operand" "")))
+ (match_operand:VF 1 "nonimmediate_operand")))
(set (match_dup 5)
(and:VF (match_dup 3)
- (match_operand:VF 2 "nonimmediate_operand" "")))
- (set (match_operand:VF 0 "register_operand" "")
+ (match_operand:VF 2 "nonimmediate_operand")))
+ (set (match_operand:VF 0 "register_operand")
(ior:VF (match_dup 4) (match_dup 5)))]
"TARGET_SSE"
{
(match_operand:VF_128 1 "nonimmediate_operand" "%x,x")
(match_operand:VF_128 2 "nonimmediate_operand" " x,m")
(match_operand:VF_128 3 "nonimmediate_operand" "xm,x"))
- (match_operand:VF_128 4 "const0_operand" "")
+ (match_operand:VF_128 4 "const0_operand")
(const_int 1)))]
"TARGET_FMA4"
"vfmadd<ssescalarmodesuffix>\t{%3, %2, %1, %0|%0, %1, %2, %3}"
(match_operand:VF_128 2 "nonimmediate_operand" " x,m")
(neg:VF_128
(match_operand:VF_128 3 "nonimmediate_operand" "xm,x")))
- (match_operand:VF_128 4 "const0_operand" "")
+ (match_operand:VF_128 4 "const0_operand")
(const_int 1)))]
"TARGET_FMA4"
"vfmsub<ssescalarmodesuffix>\t{%3, %2, %1, %0|%0, %1, %2, %3}"
(match_operand:VF_128 1 "nonimmediate_operand" "%x,x"))
(match_operand:VF_128 2 "nonimmediate_operand" " x,m")
(match_operand:VF_128 3 "nonimmediate_operand" "xm,x"))
- (match_operand:VF_128 4 "const0_operand" "")
+ (match_operand:VF_128 4 "const0_operand")
(const_int 1)))]
"TARGET_FMA4"
"vfnmadd<ssescalarmodesuffix>\t{%3, %2, %1, %0|%0, %1, %2, %3}"
(match_operand:VF_128 2 "nonimmediate_operand" " x,m")
(neg:VF_128
(match_operand:VF_128 3 "nonimmediate_operand" "xm,x")))
- (match_operand:VF_128 4 "const0_operand" "")
+ (match_operand:VF_128 4 "const0_operand")
(const_int 1)))]
"TARGET_FMA4"
"vfnmsub<ssescalarmodesuffix>\t{%3, %2, %1, %0|%0, %1, %2, %3}"
(set_attr "mode" "<sseinsnmode>")])
(define_expand "floatuns<sseintvecmodelower><mode>2"
- [(match_operand:VF1 0 "register_operand" "")
- (match_operand:<sseintvecmode> 1 "register_operand" "")]
+ [(match_operand:VF1 0 "register_operand")
+ (match_operand:<sseintvecmode> 1 "register_operand")]
"TARGET_SSE2 && (<MODE>mode == V4SFmode || TARGET_AVX2)"
{
ix86_expand_vector_convert_uns_vsivsf (operands[0], operands[1]);
(set_attr "mode" "TI")])
(define_expand "fixuns_trunc<mode><sseintvecmodelower>2"
- [(match_operand:<sseintvecmode> 0 "register_operand" "")
- (match_operand:VF1 1 "register_operand" "")]
+ [(match_operand:<sseintvecmode> 0 "register_operand")
+ (match_operand:VF1 1 "register_operand")]
"TARGET_SSE2"
{
rtx tmp[3];
(set_attr "mode" "OI")])
(define_expand "avx_cvtpd2dq256_2"
- [(set (match_operand:V8SI 0 "register_operand" "")
+ [(set (match_operand:V8SI 0 "register_operand")
(vec_concat:V8SI
- (unspec:V4SI [(match_operand:V4DF 1 "nonimmediate_operand" "")]
+ (unspec:V4SI [(match_operand:V4DF 1 "nonimmediate_operand")]
UNSPEC_FIX_NOTRUNC)
(match_dup 2)))]
"TARGET_AVX"
(vec_concat:V8SI
(unspec:V4SI [(match_operand:V4DF 1 "nonimmediate_operand" "xm")]
UNSPEC_FIX_NOTRUNC)
- (match_operand:V4SI 2 "const0_operand" "")))]
+ (match_operand:V4SI 2 "const0_operand")))]
"TARGET_AVX"
"vcvtpd2dq{y}\t{%1, %x0|%x0, %1}"
[(set_attr "type" "ssecvt")
(set_attr "mode" "OI")])
(define_expand "sse2_cvtpd2dq"
- [(set (match_operand:V4SI 0 "register_operand" "")
+ [(set (match_operand:V4SI 0 "register_operand")
(vec_concat:V4SI
- (unspec:V2SI [(match_operand:V2DF 1 "nonimmediate_operand" "")]
+ (unspec:V2SI [(match_operand:V2DF 1 "nonimmediate_operand")]
UNSPEC_FIX_NOTRUNC)
(match_dup 2)))]
"TARGET_SSE2"
(vec_concat:V4SI
(unspec:V2SI [(match_operand:V2DF 1 "nonimmediate_operand" "xm")]
UNSPEC_FIX_NOTRUNC)
- (match_operand:V2SI 2 "const0_operand" "")))]
+ (match_operand:V2SI 2 "const0_operand")))]
"TARGET_SSE2"
{
if (TARGET_AVX)
(set_attr "mode" "OI")])
(define_expand "avx_cvttpd2dq256_2"
- [(set (match_operand:V8SI 0 "register_operand" "")
+ [(set (match_operand:V8SI 0 "register_operand")
(vec_concat:V8SI
- (fix:V4SI (match_operand:V4DF 1 "nonimmediate_operand" ""))
+ (fix:V4SI (match_operand:V4DF 1 "nonimmediate_operand"))
(match_dup 2)))]
"TARGET_AVX"
"operands[2] = CONST0_RTX (V4SImode);")
[(set (match_operand:V8SI 0 "register_operand" "=x")
(vec_concat:V8SI
(fix:V4SI (match_operand:V4DF 1 "nonimmediate_operand" "xm"))
- (match_operand:V4SI 2 "const0_operand" "")))]
+ (match_operand:V4SI 2 "const0_operand")))]
"TARGET_AVX"
"vcvttpd2dq{y}\t{%1, %x0|%x0, %1}"
[(set_attr "type" "ssecvt")
(set_attr "mode" "OI")])
(define_expand "sse2_cvttpd2dq"
- [(set (match_operand:V4SI 0 "register_operand" "")
+ [(set (match_operand:V4SI 0 "register_operand")
(vec_concat:V4SI
- (fix:V2SI (match_operand:V2DF 1 "nonimmediate_operand" ""))
+ (fix:V2SI (match_operand:V2DF 1 "nonimmediate_operand"))
(match_dup 2)))]
"TARGET_SSE2"
"operands[2] = CONST0_RTX (V2SImode);")
[(set (match_operand:V4SI 0 "register_operand" "=x")
(vec_concat:V4SI
(fix:V2SI (match_operand:V2DF 1 "nonimmediate_operand" "xm"))
- (match_operand:V2SI 2 "const0_operand" "")))]
+ (match_operand:V2SI 2 "const0_operand")))]
"TARGET_SSE2"
{
if (TARGET_AVX)
(set_attr "mode" "V4SF")])
(define_expand "sse2_cvtpd2ps"
- [(set (match_operand:V4SF 0 "register_operand" "")
+ [(set (match_operand:V4SF 0 "register_operand")
(vec_concat:V4SF
(float_truncate:V2SF
- (match_operand:V2DF 1 "nonimmediate_operand" ""))
+ (match_operand:V2DF 1 "nonimmediate_operand"))
(match_dup 2)))]
"TARGET_SSE2"
"operands[2] = CONST0_RTX (V2SFmode);")
(vec_concat:V4SF
(float_truncate:V2SF
(match_operand:V2DF 1 "nonimmediate_operand" "xm"))
- (match_operand:V2SF 2 "const0_operand" "")))]
+ (match_operand:V2SF 2 "const0_operand")))]
"TARGET_SSE2"
{
if (TARGET_AVX)
(vec_select:V4SF
(vec_concat:V8SF
(match_dup 2)
- (match_operand:V4SF 1 "nonimmediate_operand" ""))
+ (match_operand:V4SF 1 "nonimmediate_operand"))
(parallel [(const_int 6) (const_int 7)
(const_int 2) (const_int 3)])))
- (set (match_operand:V2DF 0 "register_operand" "")
+ (set (match_operand:V2DF 0 "register_operand")
(float_extend:V2DF
(vec_select:V2SF
(match_dup 2)
(define_expand "vec_unpacks_hi_v8sf"
[(set (match_dup 2)
(vec_select:V4SF
- (match_operand:V8SF 1 "nonimmediate_operand" "")
+ (match_operand:V8SF 1 "nonimmediate_operand")
(parallel [(const_int 4) (const_int 5)
(const_int 6) (const_int 7)])))
- (set (match_operand:V4DF 0 "register_operand" "")
+ (set (match_operand:V4DF 0 "register_operand")
(float_extend:V4DF
(match_dup 2)))]
"TARGET_AVX"
"operands[2] = gen_reg_rtx (V4SFmode);")
(define_expand "vec_unpacks_lo_v4sf"
- [(set (match_operand:V2DF 0 "register_operand" "")
+ [(set (match_operand:V2DF 0 "register_operand")
(float_extend:V2DF
(vec_select:V2SF
- (match_operand:V4SF 1 "nonimmediate_operand" "")
+ (match_operand:V4SF 1 "nonimmediate_operand")
(parallel [(const_int 0) (const_int 1)]))))]
"TARGET_SSE2")
(define_expand "vec_unpacks_lo_v8sf"
- [(set (match_operand:V4DF 0 "register_operand" "")
+ [(set (match_operand:V4DF 0 "register_operand")
(float_extend:V4DF
(vec_select:V4SF
- (match_operand:V8SF 1 "nonimmediate_operand" "")
+ (match_operand:V8SF 1 "nonimmediate_operand")
(parallel [(const_int 0) (const_int 1)
(const_int 2) (const_int 3)]))))]
"TARGET_AVX")
[(V8HI "V4SF") (V4SI "V2DF") (V16HI "V8SF") (V8SI "V4DF")])
(define_expand "vec_unpacks_float_hi_<mode>"
- [(match_operand:<sseunpackfltmode> 0 "register_operand" "")
- (match_operand:VI2_AVX2 1 "register_operand" "")]
+ [(match_operand:<sseunpackfltmode> 0 "register_operand")
+ (match_operand:VI2_AVX2 1 "register_operand")]
"TARGET_SSE2"
{
rtx tmp = gen_reg_rtx (<sseunpackmode>mode);
})
(define_expand "vec_unpacks_float_lo_<mode>"
- [(match_operand:<sseunpackfltmode> 0 "register_operand" "")
- (match_operand:VI2_AVX2 1 "register_operand" "")]
+ [(match_operand:<sseunpackfltmode> 0 "register_operand")
+ (match_operand:VI2_AVX2 1 "register_operand")]
"TARGET_SSE2"
{
rtx tmp = gen_reg_rtx (<sseunpackmode>mode);
})
(define_expand "vec_unpacku_float_hi_<mode>"
- [(match_operand:<sseunpackfltmode> 0 "register_operand" "")
- (match_operand:VI2_AVX2 1 "register_operand" "")]
+ [(match_operand:<sseunpackfltmode> 0 "register_operand")
+ (match_operand:VI2_AVX2 1 "register_operand")]
"TARGET_SSE2"
{
rtx tmp = gen_reg_rtx (<sseunpackmode>mode);
})
(define_expand "vec_unpacku_float_lo_<mode>"
- [(match_operand:<sseunpackfltmode> 0 "register_operand" "")
- (match_operand:VI2_AVX2 1 "register_operand" "")]
+ [(match_operand:<sseunpackfltmode> 0 "register_operand")
+ (match_operand:VI2_AVX2 1 "register_operand")]
"TARGET_SSE2"
{
rtx tmp = gen_reg_rtx (<sseunpackmode>mode);
(define_expand "vec_unpacks_float_hi_v4si"
[(set (match_dup 2)
(vec_select:V4SI
- (match_operand:V4SI 1 "nonimmediate_operand" "")
+ (match_operand:V4SI 1 "nonimmediate_operand")
(parallel [(const_int 2) (const_int 3)
(const_int 2) (const_int 3)])))
- (set (match_operand:V2DF 0 "register_operand" "")
+ (set (match_operand:V2DF 0 "register_operand")
(float:V2DF
(vec_select:V2SI
(match_dup 2)
"operands[2] = gen_reg_rtx (V4SImode);")
(define_expand "vec_unpacks_float_lo_v4si"
- [(set (match_operand:V2DF 0 "register_operand" "")
+ [(set (match_operand:V2DF 0 "register_operand")
(float:V2DF
(vec_select:V2SI
- (match_operand:V4SI 1 "nonimmediate_operand" "")
+ (match_operand:V4SI 1 "nonimmediate_operand")
(parallel [(const_int 0) (const_int 1)]))))]
"TARGET_SSE2")
(define_expand "vec_unpacks_float_hi_v8si"
[(set (match_dup 2)
(vec_select:V4SI
- (match_operand:V8SI 1 "nonimmediate_operand" "")
+ (match_operand:V8SI 1 "nonimmediate_operand")
(parallel [(const_int 4) (const_int 5)
(const_int 6) (const_int 7)])))
- (set (match_operand:V4DF 0 "register_operand" "")
+ (set (match_operand:V4DF 0 "register_operand")
(float:V4DF
(match_dup 2)))]
"TARGET_AVX"
"operands[2] = gen_reg_rtx (V4SImode);")
(define_expand "vec_unpacks_float_lo_v8si"
- [(set (match_operand:V4DF 0 "register_operand" "")
+ [(set (match_operand:V4DF 0 "register_operand")
(float:V4DF
(vec_select:V4SI
- (match_operand:V8SI 1 "nonimmediate_operand" "")
+ (match_operand:V8SI 1 "nonimmediate_operand")
(parallel [(const_int 0) (const_int 1)
(const_int 2) (const_int 3)]))))]
"TARGET_AVX")
(define_expand "vec_unpacku_float_hi_v4si"
[(set (match_dup 5)
(vec_select:V4SI
- (match_operand:V4SI 1 "nonimmediate_operand" "")
+ (match_operand:V4SI 1 "nonimmediate_operand")
(parallel [(const_int 2) (const_int 3)
(const_int 2) (const_int 3)])))
(set (match_dup 6)
(lt:V2DF (match_dup 6) (match_dup 3)))
(set (match_dup 8)
(and:V2DF (match_dup 7) (match_dup 4)))
- (set (match_operand:V2DF 0 "register_operand" "")
+ (set (match_operand:V2DF 0 "register_operand")
(plus:V2DF (match_dup 6) (match_dup 8)))]
"TARGET_SSE2"
{
[(set (match_dup 5)
(float:V2DF
(vec_select:V2SI
- (match_operand:V4SI 1 "nonimmediate_operand" "")
+ (match_operand:V4SI 1 "nonimmediate_operand")
(parallel [(const_int 0) (const_int 1)]))))
(set (match_dup 6)
(lt:V2DF (match_dup 5) (match_dup 3)))
(set (match_dup 7)
(and:V2DF (match_dup 6) (match_dup 4)))
- (set (match_operand:V2DF 0 "register_operand" "")
+ (set (match_operand:V2DF 0 "register_operand")
(plus:V2DF (match_dup 5) (match_dup 7)))]
"TARGET_SSE2"
{
})
(define_expand "vec_unpacku_float_hi_v8si"
- [(match_operand:V4DF 0 "register_operand" "")
- (match_operand:V8SI 1 "register_operand" "")]
+ [(match_operand:V4DF 0 "register_operand")
+ (match_operand:V8SI 1 "register_operand")]
"TARGET_AVX"
{
REAL_VALUE_TYPE TWO32r;
})
(define_expand "vec_unpacku_float_lo_v8si"
- [(match_operand:V4DF 0 "register_operand" "")
- (match_operand:V8SI 1 "nonimmediate_operand" "")]
+ [(match_operand:V4DF 0 "register_operand")
+ (match_operand:V8SI 1 "nonimmediate_operand")]
"TARGET_AVX"
{
REAL_VALUE_TYPE TWO32r;
(define_expand "vec_pack_trunc_v4df"
[(set (match_dup 3)
(float_truncate:V4SF
- (match_operand:V4DF 1 "nonimmediate_operand" "")))
+ (match_operand:V4DF 1 "nonimmediate_operand")))
(set (match_dup 4)
(float_truncate:V4SF
- (match_operand:V4DF 2 "nonimmediate_operand" "")))
- (set (match_operand:V8SF 0 "register_operand" "")
+ (match_operand:V4DF 2 "nonimmediate_operand")))
+ (set (match_operand:V8SF 0 "register_operand")
(vec_concat:V8SF
(match_dup 3)
(match_dup 4)))]
})
(define_expand "vec_pack_trunc_v2df"
- [(match_operand:V4SF 0 "register_operand" "")
- (match_operand:V2DF 1 "nonimmediate_operand" "")
- (match_operand:V2DF 2 "nonimmediate_operand" "")]
+ [(match_operand:V4SF 0 "register_operand")
+ (match_operand:V2DF 1 "nonimmediate_operand")
+ (match_operand:V2DF 2 "nonimmediate_operand")]
"TARGET_SSE2"
{
rtx tmp0, tmp1;
})
(define_expand "vec_pack_sfix_trunc_v4df"
- [(match_operand:V8SI 0 "register_operand" "")
- (match_operand:V4DF 1 "nonimmediate_operand" "")
- (match_operand:V4DF 2 "nonimmediate_operand" "")]
+ [(match_operand:V8SI 0 "register_operand")
+ (match_operand:V4DF 1 "nonimmediate_operand")
+ (match_operand:V4DF 2 "nonimmediate_operand")]
"TARGET_AVX"
{
rtx r1, r2;
})
(define_expand "vec_pack_sfix_trunc_v2df"
- [(match_operand:V4SI 0 "register_operand" "")
- (match_operand:V2DF 1 "nonimmediate_operand" "")
- (match_operand:V2DF 2 "nonimmediate_operand" "")]
+ [(match_operand:V4SI 0 "register_operand")
+ (match_operand:V2DF 1 "nonimmediate_operand")
+ (match_operand:V2DF 2 "nonimmediate_operand")]
"TARGET_SSE2"
{
rtx tmp0, tmp1;
[(V4DF "V8SI") (V2DF "V4SI")])
(define_expand "vec_pack_ufix_trunc_<mode>"
- [(match_operand:<ssepackfltmode> 0 "register_operand" "")
- (match_operand:VF2 1 "register_operand" "")
- (match_operand:VF2 2 "register_operand" "")]
+ [(match_operand:<ssepackfltmode> 0 "register_operand")
+ (match_operand:VF2 1 "register_operand")
+ (match_operand:VF2 2 "register_operand")]
"TARGET_SSE2"
{
rtx tmp[7];
})
(define_expand "vec_pack_sfix_v4df"
- [(match_operand:V8SI 0 "register_operand" "")
- (match_operand:V4DF 1 "nonimmediate_operand" "")
- (match_operand:V4DF 2 "nonimmediate_operand" "")]
+ [(match_operand:V8SI 0 "register_operand")
+ (match_operand:V4DF 1 "nonimmediate_operand")
+ (match_operand:V4DF 2 "nonimmediate_operand")]
"TARGET_AVX"
{
rtx r1, r2;
})
(define_expand "vec_pack_sfix_v2df"
- [(match_operand:V4SI 0 "register_operand" "")
- (match_operand:V2DF 1 "nonimmediate_operand" "")
- (match_operand:V2DF 2 "nonimmediate_operand" "")]
+ [(match_operand:V4SI 0 "register_operand")
+ (match_operand:V2DF 1 "nonimmediate_operand")
+ (match_operand:V2DF 2 "nonimmediate_operand")]
"TARGET_SSE2"
{
rtx tmp0, tmp1;
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
(define_expand "sse_movhlps_exp"
- [(set (match_operand:V4SF 0 "nonimmediate_operand" "")
+ [(set (match_operand:V4SF 0 "nonimmediate_operand")
(vec_select:V4SF
(vec_concat:V8SF
- (match_operand:V4SF 1 "nonimmediate_operand" "")
- (match_operand:V4SF 2 "nonimmediate_operand" ""))
+ (match_operand:V4SF 1 "nonimmediate_operand")
+ (match_operand:V4SF 2 "nonimmediate_operand"))
(parallel [(const_int 6)
(const_int 7)
(const_int 2)
(set_attr "mode" "V4SF,V4SF,V2SF,V2SF,V2SF")])
(define_expand "sse_movlhps_exp"
- [(set (match_operand:V4SF 0 "nonimmediate_operand" "")
+ [(set (match_operand:V4SF 0 "nonimmediate_operand")
(vec_select:V4SF
(vec_concat:V8SF
- (match_operand:V4SF 1 "nonimmediate_operand" "")
- (match_operand:V4SF 2 "nonimmediate_operand" ""))
+ (match_operand:V4SF 1 "nonimmediate_operand")
+ (match_operand:V4SF 2 "nonimmediate_operand"))
(parallel [(const_int 0)
(const_int 1)
(const_int 4)
(const_int 3) (const_int 11)
(const_int 6) (const_int 14)
(const_int 7) (const_int 15)])))
- (set (match_operand:V8SF 0 "register_operand" "")
+ (set (match_operand:V8SF 0 "register_operand")
(vec_select:V8SF
(vec_concat:V16SF
(match_dup 3)
(const_int 3) (const_int 11)
(const_int 6) (const_int 14)
(const_int 7) (const_int 15)])))
- (set (match_operand:V8SF 0 "register_operand" "")
+ (set (match_operand:V8SF 0 "register_operand")
(vec_select:V8SF
(vec_concat:V16SF
(match_dup 3)
(set_attr "mode" "V4SF")])
(define_expand "avx_shufps256"
- [(match_operand:V8SF 0 "register_operand" "")
- (match_operand:V8SF 1 "register_operand" "")
- (match_operand:V8SF 2 "nonimmediate_operand" "")
- (match_operand:SI 3 "const_int_operand" "")]
+ [(match_operand:V8SF 0 "register_operand")
+ (match_operand:V8SF 1 "register_operand")
+ (match_operand:V8SF 2 "nonimmediate_operand")
+ (match_operand:SI 3 "const_int_operand")]
"TARGET_AVX"
{
int mask = INTVAL (operands[3]);
(vec_concat:V16SF
(match_operand:V8SF 1 "register_operand" "x")
(match_operand:V8SF 2 "nonimmediate_operand" "xm"))
- (parallel [(match_operand 3 "const_0_to_3_operand" "")
- (match_operand 4 "const_0_to_3_operand" "")
- (match_operand 5 "const_8_to_11_operand" "")
- (match_operand 6 "const_8_to_11_operand" "")
- (match_operand 7 "const_4_to_7_operand" "")
- (match_operand 8 "const_4_to_7_operand" "")
- (match_operand 9 "const_12_to_15_operand" "")
- (match_operand 10 "const_12_to_15_operand" "")])))]
+ (parallel [(match_operand 3 "const_0_to_3_operand" )
+ (match_operand 4 "const_0_to_3_operand" )
+ (match_operand 5 "const_8_to_11_operand" )
+ (match_operand 6 "const_8_to_11_operand" )
+ (match_operand 7 "const_4_to_7_operand" )
+ (match_operand 8 "const_4_to_7_operand" )
+ (match_operand 9 "const_12_to_15_operand")
+ (match_operand 10 "const_12_to_15_operand")])))]
"TARGET_AVX
&& (INTVAL (operands[3]) == (INTVAL (operands[7]) - 4)
&& INTVAL (operands[4]) == (INTVAL (operands[8]) - 4)
(set_attr "mode" "V8SF")])
(define_expand "sse_shufps"
- [(match_operand:V4SF 0 "register_operand" "")
- (match_operand:V4SF 1 "register_operand" "")
- (match_operand:V4SF 2 "nonimmediate_operand" "")
- (match_operand:SI 3 "const_int_operand" "")]
+ [(match_operand:V4SF 0 "register_operand")
+ (match_operand:V4SF 1 "register_operand")
+ (match_operand:V4SF 2 "nonimmediate_operand")
+ (match_operand:SI 3 "const_int_operand")]
"TARGET_SSE"
{
int mask = INTVAL (operands[3]);
(vec_concat:<ssedoublevecmode>
(match_operand:VI4F_128 1 "register_operand" "0,x")
(match_operand:VI4F_128 2 "nonimmediate_operand" "xm,xm"))
- (parallel [(match_operand 3 "const_0_to_3_operand" "")
- (match_operand 4 "const_0_to_3_operand" "")
- (match_operand 5 "const_4_to_7_operand" "")
- (match_operand 6 "const_4_to_7_operand" "")])))]
+ (parallel [(match_operand 3 "const_0_to_3_operand")
+ (match_operand 4 "const_0_to_3_operand")
+ (match_operand 5 "const_4_to_7_operand")
+ (match_operand 6 "const_4_to_7_operand")])))]
"TARGET_SSE"
{
int mask = 0;
(set_attr "mode" "V2SF,V4SF,V2SF")])
(define_expand "sse_loadhps_exp"
- [(set (match_operand:V4SF 0 "nonimmediate_operand" "")
+ [(set (match_operand:V4SF 0 "nonimmediate_operand")
(vec_concat:V4SF
(vec_select:V2SF
- (match_operand:V4SF 1 "nonimmediate_operand" "")
+ (match_operand:V4SF 1 "nonimmediate_operand")
(parallel [(const_int 0) (const_int 1)]))
- (match_operand:V2SF 2 "nonimmediate_operand" "")))]
+ (match_operand:V2SF 2 "nonimmediate_operand")))]
"TARGET_SSE"
{
rtx dst = ix86_fixup_binary_operands (UNKNOWN, V4SFmode, operands);
(set_attr "mode" "V2SF,V4SF,V2SF")])
(define_expand "sse_loadlps_exp"
- [(set (match_operand:V4SF 0 "nonimmediate_operand" "")
+ [(set (match_operand:V4SF 0 "nonimmediate_operand")
(vec_concat:V4SF
- (match_operand:V2SF 2 "nonimmediate_operand" "")
+ (match_operand:V2SF 2 "nonimmediate_operand")
(vec_select:V2SF
- (match_operand:V4SF 1 "nonimmediate_operand" "")
+ (match_operand:V4SF 1 "nonimmediate_operand")
(parallel [(const_int 2) (const_int 3)]))))]
"TARGET_SSE"
{
(set_attr "mode" "V4SF,V4SF,V2SF,V2SF")])
(define_expand "vec_init<mode>"
- [(match_operand:V_128 0 "register_operand" "")
- (match_operand 1 "" "")]
+ [(match_operand:V_128 0 "register_operand")
+ (match_operand 1)]
"TARGET_SSE"
{
ix86_expand_vector_init (false, operands[0], operands[1]);
(vec_duplicate:V4SF
(match_operand:SF 2 "nonimmediate_operand" "xm,xm"))
(match_operand:V4SF 1 "register_operand" "0,x")
- (match_operand:SI 3 "const_int_operand" "")))]
+ (match_operand:SI 3 "const_int_operand")))]
"TARGET_SSE4_1
&& ((unsigned) exact_log2 (INTVAL (operands[3]))
< GET_MODE_NUNITS (V4SFmode))"
(set_attr "mode" "V4SF")])
(define_split
- [(set (match_operand:VI4F_128 0 "memory_operand" "")
+ [(set (match_operand:VI4F_128 0 "memory_operand")
(vec_merge:VI4F_128
(vec_duplicate:VI4F_128
- (match_operand:<ssescalarmode> 1 "nonmemory_operand" ""))
+ (match_operand:<ssescalarmode> 1 "nonmemory_operand"))
(match_dup 0)
(const_int 1)))]
"TARGET_SSE && reload_completed"
})
(define_expand "vec_set<mode>"
- [(match_operand:V 0 "register_operand" "")
- (match_operand:<ssescalarmode> 1 "register_operand" "")
- (match_operand 2 "const_int_operand" "")]
+ [(match_operand:V 0 "register_operand")
+ (match_operand:<ssescalarmode> 1 "register_operand")
+ (match_operand 2 "const_int_operand")]
"TARGET_SSE"
{
ix86_expand_vector_set (false, operands[0], operands[1],
})
(define_expand "avx_vextractf128<mode>"
- [(match_operand:<ssehalfvecmode> 0 "nonimmediate_operand" "")
- (match_operand:V_256 1 "register_operand" "")
- (match_operand:SI 2 "const_0_to_1_operand" "")]
+ [(match_operand:<ssehalfvecmode> 0 "nonimmediate_operand")
+ (match_operand:V_256 1 "register_operand")
+ (match_operand:SI 2 "const_0_to_1_operand")]
"TARGET_AVX"
{
rtx (*insn)(rtx, rtx);
(V4DF "TARGET_AVX") V2DF])
(define_expand "vec_extract<mode>"
- [(match_operand:<ssescalarmode> 0 "register_operand" "")
- (match_operand:VEC_EXTRACT_MODE 1 "register_operand" "")
- (match_operand 2 "const_int_operand" "")]
+ [(match_operand:<ssescalarmode> 0 "register_operand")
+ (match_operand:VEC_EXTRACT_MODE 1 "register_operand")
+ (match_operand 2 "const_int_operand")]
"TARGET_SSE"
{
ix86_expand_vector_extract (false, operands[0], operands[1],
(match_dup 2))
(parallel [(const_int 1) (const_int 5)
(const_int 3) (const_int 7)])))
- (set (match_operand:V4DF 0 "register_operand" "")
+ (set (match_operand:V4DF 0 "register_operand")
(vec_select:V4DF
(vec_concat:V8DF
(match_dup 3)
(define_expand "vec_interleave_highv2df"
- [(set (match_operand:V2DF 0 "register_operand" "")
+ [(set (match_operand:V2DF 0 "register_operand")
(vec_select:V2DF
(vec_concat:V4DF
- (match_operand:V2DF 1 "nonimmediate_operand" "")
- (match_operand:V2DF 2 "nonimmediate_operand" ""))
+ (match_operand:V2DF 1 "nonimmediate_operand")
+ (match_operand:V2DF 2 "nonimmediate_operand"))
(parallel [(const_int 1)
(const_int 3)])))]
"TARGET_SSE2"
;; Recall that the 256-bit unpck insns only shuffle within their lanes.
(define_expand "avx_movddup256"
- [(set (match_operand:V4DF 0 "register_operand" "")
+ [(set (match_operand:V4DF 0 "register_operand")
(vec_select:V4DF
(vec_concat:V8DF
- (match_operand:V4DF 1 "nonimmediate_operand" "")
+ (match_operand:V4DF 1 "nonimmediate_operand")
(match_dup 1))
(parallel [(const_int 0) (const_int 4)
(const_int 2) (const_int 6)])))]
"TARGET_AVX")
(define_expand "avx_unpcklpd256"
- [(set (match_operand:V4DF 0 "register_operand" "")
+ [(set (match_operand:V4DF 0 "register_operand")
(vec_select:V4DF
(vec_concat:V8DF
- (match_operand:V4DF 1 "register_operand" "")
- (match_operand:V4DF 2 "nonimmediate_operand" ""))
+ (match_operand:V4DF 1 "register_operand")
+ (match_operand:V4DF 2 "nonimmediate_operand"))
(parallel [(const_int 0) (const_int 4)
(const_int 2) (const_int 6)])))]
"TARGET_AVX")
(match_dup 2))
(parallel [(const_int 1) (const_int 5)
(const_int 3) (const_int 7)])))
- (set (match_operand:V4DF 0 "register_operand" "")
+ (set (match_operand:V4DF 0 "register_operand")
(vec_select:V4DF
(vec_concat:V8DF
(match_dup 3)
})
(define_expand "vec_interleave_lowv2df"
- [(set (match_operand:V2DF 0 "register_operand" "")
+ [(set (match_operand:V2DF 0 "register_operand")
(vec_select:V2DF
(vec_concat:V4DF
- (match_operand:V2DF 1 "nonimmediate_operand" "")
- (match_operand:V2DF 2 "nonimmediate_operand" ""))
+ (match_operand:V2DF 1 "nonimmediate_operand")
+ (match_operand:V2DF 2 "nonimmediate_operand"))
(parallel [(const_int 0)
(const_int 2)])))]
"TARGET_SSE2"
(set_attr "mode" "V2DF,V2DF,V2DF,V1DF,V1DF,V1DF")])
(define_split
- [(set (match_operand:V2DF 0 "memory_operand" "")
+ [(set (match_operand:V2DF 0 "memory_operand")
(vec_select:V2DF
(vec_concat:V4DF
- (match_operand:V2DF 1 "register_operand" "")
+ (match_operand:V2DF 1 "register_operand")
(match_dup 1))
(parallel [(const_int 0)
(const_int 2)])))]
})
(define_split
- [(set (match_operand:V2DF 0 "register_operand" "")
+ [(set (match_operand:V2DF 0 "register_operand")
(vec_select:V2DF
(vec_concat:V4DF
- (match_operand:V2DF 1 "memory_operand" "")
+ (match_operand:V2DF 1 "memory_operand")
(match_dup 1))
- (parallel [(match_operand:SI 2 "const_0_to_1_operand" "")
- (match_operand:SI 3 "const_int_operand" "")])))]
+ (parallel [(match_operand:SI 2 "const_0_to_1_operand")
+ (match_operand:SI 3 "const_int_operand")])))]
"TARGET_SSE3 && INTVAL (operands[2]) + 2 == INTVAL (operands[3])"
[(set (match_dup 0) (vec_duplicate:V2DF (match_dup 1)))]
{
})
(define_expand "avx_shufpd256"
- [(match_operand:V4DF 0 "register_operand" "")
- (match_operand:V4DF 1 "register_operand" "")
- (match_operand:V4DF 2 "nonimmediate_operand" "")
- (match_operand:SI 3 "const_int_operand" "")]
+ [(match_operand:V4DF 0 "register_operand")
+ (match_operand:V4DF 1 "register_operand")
+ (match_operand:V4DF 2 "nonimmediate_operand")
+ (match_operand:SI 3 "const_int_operand")]
"TARGET_AVX"
{
int mask = INTVAL (operands[3]);
(vec_concat:V8DF
(match_operand:V4DF 1 "register_operand" "x")
(match_operand:V4DF 2 "nonimmediate_operand" "xm"))
- (parallel [(match_operand 3 "const_0_to_1_operand" "")
- (match_operand 4 "const_4_to_5_operand" "")
- (match_operand 5 "const_2_to_3_operand" "")
- (match_operand 6 "const_6_to_7_operand" "")])))]
+ (parallel [(match_operand 3 "const_0_to_1_operand")
+ (match_operand 4 "const_4_to_5_operand")
+ (match_operand 5 "const_2_to_3_operand")
+ (match_operand 6 "const_6_to_7_operand")])))]
"TARGET_AVX"
{
int mask;
(set_attr "mode" "V4DF")])
(define_expand "sse2_shufpd"
- [(match_operand:V2DF 0 "register_operand" "")
- (match_operand:V2DF 1 "register_operand" "")
- (match_operand:V2DF 2 "nonimmediate_operand" "")
- (match_operand:SI 3 "const_int_operand" "")]
+ [(match_operand:V2DF 0 "register_operand")
+ (match_operand:V2DF 1 "register_operand")
+ (match_operand:V2DF 2 "nonimmediate_operand")
+ (match_operand:SI 3 "const_int_operand")]
"TARGET_SSE2"
{
int mask = INTVAL (operands[3]);
(vec_concat:<ssedoublevecmode>
(match_operand:VI8F_128 1 "register_operand" "0,x")
(match_operand:VI8F_128 2 "nonimmediate_operand" "xm,xm"))
- (parallel [(match_operand 3 "const_0_to_1_operand" "")
- (match_operand 4 "const_2_to_3_operand" "")])))]
+ (parallel [(match_operand 3 "const_0_to_1_operand")
+ (match_operand 4 "const_2_to_3_operand")])))]
"TARGET_SSE2"
{
int mask;
(set_attr "mode" "V1DF,V1DF,V2DF,DF,DF,DF")])
(define_split
- [(set (match_operand:DF 0 "register_operand" "")
+ [(set (match_operand:DF 0 "register_operand")
(vec_select:DF
- (match_operand:V2DF 1 "memory_operand" "")
+ (match_operand:V2DF 1 "memory_operand")
(parallel [(const_int 1)])))]
"TARGET_SSE2 && reload_completed"
[(set (match_dup 0) (match_dup 1))]
(set_attr "mode" "V1DF,DF,DF,DF,DF")])
(define_split
- [(set (match_operand:DF 0 "register_operand" "")
+ [(set (match_operand:DF 0 "register_operand")
(vec_select:DF
- (match_operand:V2DF 1 "nonimmediate_operand" "")
+ (match_operand:V2DF 1 "nonimmediate_operand")
(parallel [(const_int 0)])))]
"TARGET_SSE2 && reload_completed"
[(const_int 0)]
(set_attr "mode" "V2SF,V4SF,V2SF")])
(define_expand "sse2_loadhpd_exp"
- [(set (match_operand:V2DF 0 "nonimmediate_operand" "")
+ [(set (match_operand:V2DF 0 "nonimmediate_operand")
(vec_concat:V2DF
(vec_select:DF
- (match_operand:V2DF 1 "nonimmediate_operand" "")
+ (match_operand:V2DF 1 "nonimmediate_operand")
(parallel [(const_int 0)]))
- (match_operand:DF 2 "nonimmediate_operand" "")))]
+ (match_operand:DF 2 "nonimmediate_operand")))]
"TARGET_SSE2"
{
rtx dst = ix86_fixup_binary_operands (UNKNOWN, V2DFmode, operands);
(set_attr "mode" "V1DF,V1DF,V2DF,V2DF,DF,DF,DF")])
(define_split
- [(set (match_operand:V2DF 0 "memory_operand" "")
+ [(set (match_operand:V2DF 0 "memory_operand")
(vec_concat:V2DF
(vec_select:DF (match_dup 0) (parallel [(const_int 0)]))
- (match_operand:DF 1 "register_operand" "")))]
+ (match_operand:DF 1 "register_operand")))]
"TARGET_SSE2 && reload_completed"
[(set (match_dup 0) (match_dup 1))]
"operands[0] = adjust_address (operands[0], DFmode, 8);")
(define_expand "sse2_loadlpd_exp"
- [(set (match_operand:V2DF 0 "nonimmediate_operand" "")
+ [(set (match_operand:V2DF 0 "nonimmediate_operand")
(vec_concat:V2DF
- (match_operand:DF 2 "nonimmediate_operand" "")
+ (match_operand:DF 2 "nonimmediate_operand")
(vec_select:DF
- (match_operand:V2DF 1 "nonimmediate_operand" "")
+ (match_operand:V2DF 1 "nonimmediate_operand")
(parallel [(const_int 1)]))))]
"TARGET_SSE2"
{
(set_attr "mode" "DF,V1DF,V1DF,V1DF,V1DF,V2DF,V1DF,V1DF,DF,DF,DF")])
(define_split
- [(set (match_operand:V2DF 0 "memory_operand" "")
+ [(set (match_operand:V2DF 0 "memory_operand")
(vec_concat:V2DF
- (match_operand:DF 1 "register_operand" "")
+ (match_operand:DF 1 "register_operand")
(vec_select:DF (match_dup 0) (parallel [(const_int 1)]))))]
"TARGET_SSE2 && reload_completed"
[(set (match_dup 0) (match_dup 1))]
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
(define_expand "neg<mode>2"
- [(set (match_operand:VI_AVX2 0 "register_operand" "")
+ [(set (match_operand:VI_AVX2 0 "register_operand")
(minus:VI_AVX2
(match_dup 2)
- (match_operand:VI_AVX2 1 "nonimmediate_operand" "")))]
+ (match_operand:VI_AVX2 1 "nonimmediate_operand")))]
"TARGET_SSE2"
"operands[2] = force_reg (<MODE>mode, CONST0_RTX (<MODE>mode));")
(define_expand "<plusminus_insn><mode>3"
- [(set (match_operand:VI_AVX2 0 "register_operand" "")
+ [(set (match_operand:VI_AVX2 0 "register_operand")
(plusminus:VI_AVX2
- (match_operand:VI_AVX2 1 "nonimmediate_operand" "")
- (match_operand:VI_AVX2 2 "nonimmediate_operand" "")))]
+ (match_operand:VI_AVX2 1 "nonimmediate_operand")
+ (match_operand:VI_AVX2 2 "nonimmediate_operand")))]
"TARGET_SSE2"
"ix86_fixup_binary_operands_no_copy (<CODE>, <MODE>mode, operands);")
(set_attr "mode" "<sseinsnmode>")])
(define_expand "<sse2_avx2>_<plusminus_insn><mode>3"
- [(set (match_operand:VI12_AVX2 0 "register_operand" "")
+ [(set (match_operand:VI12_AVX2 0 "register_operand")
(sat_plusminus:VI12_AVX2
- (match_operand:VI12_AVX2 1 "nonimmediate_operand" "")
- (match_operand:VI12_AVX2 2 "nonimmediate_operand" "")))]
+ (match_operand:VI12_AVX2 1 "nonimmediate_operand")
+ (match_operand:VI12_AVX2 2 "nonimmediate_operand")))]
"TARGET_SSE2"
"ix86_fixup_binary_operands_no_copy (<CODE>, <MODE>mode, operands);")
(set_attr "mode" "TI")])
(define_insn_and_split "mul<mode>3"
- [(set (match_operand:VI1_AVX2 0 "register_operand" "")
- (mult:VI1_AVX2 (match_operand:VI1_AVX2 1 "register_operand" "")
- (match_operand:VI1_AVX2 2 "register_operand" "")))]
+ [(set (match_operand:VI1_AVX2 0 "register_operand")
+ (mult:VI1_AVX2 (match_operand:VI1_AVX2 1 "register_operand")
+ (match_operand:VI1_AVX2 2 "register_operand")))]
"TARGET_SSE2
&& can_create_pseudo_p ()"
"#"
})
(define_expand "mul<mode>3"
- [(set (match_operand:VI2_AVX2 0 "register_operand" "")
- (mult:VI2_AVX2 (match_operand:VI2_AVX2 1 "nonimmediate_operand" "")
- (match_operand:VI2_AVX2 2 "nonimmediate_operand" "")))]
+ [(set (match_operand:VI2_AVX2 0 "register_operand")
+ (mult:VI2_AVX2 (match_operand:VI2_AVX2 1 "nonimmediate_operand")
+ (match_operand:VI2_AVX2 2 "nonimmediate_operand")))]
"TARGET_SSE2"
"ix86_fixup_binary_operands_no_copy (MULT, <MODE>mode, operands);")
(set_attr "mode" "<sseinsnmode>")])
(define_expand "<s>mul<mode>3_highpart"
- [(set (match_operand:VI2_AVX2 0 "register_operand" "")
+ [(set (match_operand:VI2_AVX2 0 "register_operand")
(truncate:VI2_AVX2
(lshiftrt:<ssedoublemode>
(mult:<ssedoublemode>
(any_extend:<ssedoublemode>
- (match_operand:VI2_AVX2 1 "nonimmediate_operand" ""))
+ (match_operand:VI2_AVX2 1 "nonimmediate_operand"))
(any_extend:<ssedoublemode>
- (match_operand:VI2_AVX2 2 "nonimmediate_operand" "")))
+ (match_operand:VI2_AVX2 2 "nonimmediate_operand")))
(const_int 16))))]
"TARGET_SSE2"
"ix86_fixup_binary_operands_no_copy (MULT, <MODE>mode, operands);")
(set_attr "mode" "<sseinsnmode>")])
(define_expand "avx2_umulv4siv4di3"
- [(set (match_operand:V4DI 0 "register_operand" "")
+ [(set (match_operand:V4DI 0 "register_operand")
(mult:V4DI
(zero_extend:V4DI
(vec_select:V4SI
- (match_operand:V8SI 1 "nonimmediate_operand" "")
+ (match_operand:V8SI 1 "nonimmediate_operand")
(parallel [(const_int 0) (const_int 2)
(const_int 4) (const_int 6)])))
(zero_extend:V4DI
(vec_select:V4SI
- (match_operand:V8SI 2 "nonimmediate_operand" "")
+ (match_operand:V8SI 2 "nonimmediate_operand")
(parallel [(const_int 0) (const_int 2)
(const_int 4) (const_int 6)])))))]
"TARGET_AVX2"
(set_attr "mode" "OI")])
(define_expand "sse2_umulv2siv2di3"
- [(set (match_operand:V2DI 0 "register_operand" "")
+ [(set (match_operand:V2DI 0 "register_operand")
(mult:V2DI
(zero_extend:V2DI
(vec_select:V2SI
- (match_operand:V4SI 1 "nonimmediate_operand" "")
+ (match_operand:V4SI 1 "nonimmediate_operand")
(parallel [(const_int 0) (const_int 2)])))
(zero_extend:V2DI
(vec_select:V2SI
- (match_operand:V4SI 2 "nonimmediate_operand" "")
+ (match_operand:V4SI 2 "nonimmediate_operand")
(parallel [(const_int 0) (const_int 2)])))))]
"TARGET_SSE2"
"ix86_fixup_binary_operands_no_copy (MULT, V4SImode, operands);")
(set_attr "mode" "TI")])
(define_expand "avx2_mulv4siv4di3"
- [(set (match_operand:V4DI 0 "register_operand" "")
+ [(set (match_operand:V4DI 0 "register_operand")
(mult:V4DI
(sign_extend:V4DI
(vec_select:V4SI
- (match_operand:V8SI 1 "nonimmediate_operand" "")
+ (match_operand:V8SI 1 "nonimmediate_operand")
(parallel [(const_int 0) (const_int 2)
(const_int 4) (const_int 6)])))
(sign_extend:V4DI
(vec_select:V4SI
- (match_operand:V8SI 2 "nonimmediate_operand" "")
+ (match_operand:V8SI 2 "nonimmediate_operand")
(parallel [(const_int 0) (const_int 2)
(const_int 4) (const_int 6)])))))]
"TARGET_AVX2"
(set_attr "mode" "OI")])
(define_expand "sse4_1_mulv2siv2di3"
- [(set (match_operand:V2DI 0 "register_operand" "")
+ [(set (match_operand:V2DI 0 "register_operand")
(mult:V2DI
(sign_extend:V2DI
(vec_select:V2SI
- (match_operand:V4SI 1 "nonimmediate_operand" "")
+ (match_operand:V4SI 1 "nonimmediate_operand")
(parallel [(const_int 0) (const_int 2)])))
(sign_extend:V2DI
(vec_select:V2SI
- (match_operand:V4SI 2 "nonimmediate_operand" "")
+ (match_operand:V4SI 2 "nonimmediate_operand")
(parallel [(const_int 0) (const_int 2)])))))]
"TARGET_SSE4_1"
"ix86_fixup_binary_operands_no_copy (MULT, V4SImode, operands);")
(set_attr "mode" "TI")])
(define_expand "avx2_pmaddwd"
- [(set (match_operand:V8SI 0 "register_operand" "")
+ [(set (match_operand:V8SI 0 "register_operand")
(plus:V8SI
(mult:V8SI
(sign_extend:V8SI
(vec_select:V8HI
- (match_operand:V16HI 1 "nonimmediate_operand" "")
+ (match_operand:V16HI 1 "nonimmediate_operand")
(parallel [(const_int 0)
(const_int 2)
(const_int 4)
(const_int 14)])))
(sign_extend:V8SI
(vec_select:V8HI
- (match_operand:V16HI 2 "nonimmediate_operand" "")
+ (match_operand:V16HI 2 "nonimmediate_operand")
(parallel [(const_int 0)
(const_int 2)
(const_int 4)
"ix86_fixup_binary_operands_no_copy (MULT, V16HImode, operands);")
(define_expand "sse2_pmaddwd"
- [(set (match_operand:V4SI 0 "register_operand" "")
+ [(set (match_operand:V4SI 0 "register_operand")
(plus:V4SI
(mult:V4SI
(sign_extend:V4SI
(vec_select:V4HI
- (match_operand:V8HI 1 "nonimmediate_operand" "")
+ (match_operand:V8HI 1 "nonimmediate_operand")
(parallel [(const_int 0)
(const_int 2)
(const_int 4)
(const_int 6)])))
(sign_extend:V4SI
(vec_select:V4HI
- (match_operand:V8HI 2 "nonimmediate_operand" "")
+ (match_operand:V8HI 2 "nonimmediate_operand")
(parallel [(const_int 0)
(const_int 2)
(const_int 4)
(set_attr "mode" "TI")])
(define_expand "mul<mode>3"
- [(set (match_operand:VI4_AVX2 0 "register_operand" "")
- (mult:VI4_AVX2 (match_operand:VI4_AVX2 1 "register_operand" "")
- (match_operand:VI4_AVX2 2 "register_operand" "")))]
+ [(set (match_operand:VI4_AVX2 0 "register_operand")
+ (mult:VI4_AVX2 (match_operand:VI4_AVX2 1 "register_operand")
+ (match_operand:VI4_AVX2 2 "register_operand")))]
"TARGET_SSE2"
{
if (TARGET_SSE4_1 || TARGET_AVX)
(set_attr "mode" "<sseinsnmode>")])
(define_insn_and_split "*sse2_mulv4si3"
- [(set (match_operand:V4SI 0 "register_operand" "")
- (mult:V4SI (match_operand:V4SI 1 "register_operand" "")
- (match_operand:V4SI 2 "register_operand" "")))]
+ [(set (match_operand:V4SI 0 "register_operand")
+ (mult:V4SI (match_operand:V4SI 1 "register_operand")
+ (match_operand:V4SI 2 "register_operand")))]
"TARGET_SSE2 && !TARGET_SSE4_1 && !TARGET_AVX
&& can_create_pseudo_p ()"
"#"
})
(define_insn_and_split "mul<mode>3"
- [(set (match_operand:VI8_AVX2 0 "register_operand" "")
- (mult:VI8_AVX2 (match_operand:VI8_AVX2 1 "register_operand" "")
- (match_operand:VI8_AVX2 2 "register_operand" "")))]
+ [(set (match_operand:VI8_AVX2 0 "register_operand")
+ (mult:VI8_AVX2 (match_operand:VI8_AVX2 1 "register_operand")
+ (match_operand:VI8_AVX2 2 "register_operand")))]
"TARGET_SSE2
&& can_create_pseudo_p ()"
"#"
})
(define_expand "vec_widen_<s>mult_hi_<mode>"
- [(match_operand:<sseunpackmode> 0 "register_operand" "")
+ [(match_operand:<sseunpackmode> 0 "register_operand")
(any_extend:<sseunpackmode>
- (match_operand:VI2_AVX2 1 "register_operand" ""))
- (match_operand:VI2_AVX2 2 "register_operand" "")]
+ (match_operand:VI2_AVX2 1 "register_operand"))
+ (match_operand:VI2_AVX2 2 "register_operand")]
"TARGET_SSE2"
{
rtx op1, op2, t1, t2, dest;
})
(define_expand "vec_widen_<s>mult_lo_<mode>"
- [(match_operand:<sseunpackmode> 0 "register_operand" "")
+ [(match_operand:<sseunpackmode> 0 "register_operand")
(any_extend:<sseunpackmode>
- (match_operand:VI2_AVX2 1 "register_operand" ""))
- (match_operand:VI2_AVX2 2 "register_operand" "")]
+ (match_operand:VI2_AVX2 1 "register_operand"))
+ (match_operand:VI2_AVX2 2 "register_operand")]
"TARGET_SSE2"
{
rtx op1, op2, t1, t2, dest;
})
(define_expand "vec_widen_<s>mult_hi_v8si"
- [(match_operand:V4DI 0 "register_operand" "")
- (any_extend:V4DI (match_operand:V8SI 1 "nonimmediate_operand" ""))
- (match_operand:V8SI 2 "nonimmediate_operand" "")]
+ [(match_operand:V4DI 0 "register_operand")
+ (any_extend:V4DI (match_operand:V8SI 1 "nonimmediate_operand"))
+ (match_operand:V8SI 2 "nonimmediate_operand")]
"TARGET_AVX2"
{
rtx t1, t2, t3, t4;
})
(define_expand "vec_widen_<s>mult_lo_v8si"
- [(match_operand:V4DI 0 "register_operand" "")
- (any_extend:V4DI (match_operand:V8SI 1 "nonimmediate_operand" ""))
- (match_operand:V8SI 2 "nonimmediate_operand" "")]
+ [(match_operand:V4DI 0 "register_operand")
+ (any_extend:V4DI (match_operand:V8SI 1 "nonimmediate_operand"))
+ (match_operand:V8SI 2 "nonimmediate_operand")]
"TARGET_AVX2"
{
rtx t1, t2, t3, t4;
})
(define_expand "vec_widen_smult_hi_v4si"
- [(match_operand:V2DI 0 "register_operand" "")
- (match_operand:V4SI 1 "register_operand" "")
- (match_operand:V4SI 2 "register_operand" "")]
+ [(match_operand:V2DI 0 "register_operand")
+ (match_operand:V4SI 1 "register_operand")
+ (match_operand:V4SI 2 "register_operand")]
"TARGET_SSE4_1"
{
rtx op1, op2, t1, t2;
})
(define_expand "vec_widen_smult_lo_v4si"
- [(match_operand:V2DI 0 "register_operand" "")
- (match_operand:V4SI 1 "register_operand" "")
- (match_operand:V4SI 2 "register_operand" "")]
+ [(match_operand:V2DI 0 "register_operand")
+ (match_operand:V4SI 1 "register_operand")
+ (match_operand:V4SI 2 "register_operand")]
"TARGET_SSE4_1"
{
rtx op1, op2, t1, t2;
})
(define_expand "vec_widen_umult_hi_v4si"
- [(match_operand:V2DI 0 "register_operand" "")
- (match_operand:V4SI 1 "register_operand" "")
- (match_operand:V4SI 2 "register_operand" "")]
+ [(match_operand:V2DI 0 "register_operand")
+ (match_operand:V4SI 1 "register_operand")
+ (match_operand:V4SI 2 "register_operand")]
"TARGET_SSE2"
{
rtx op1, op2, t1, t2;
})
(define_expand "vec_widen_umult_lo_v4si"
- [(match_operand:V2DI 0 "register_operand" "")
- (match_operand:V4SI 1 "register_operand" "")
- (match_operand:V4SI 2 "register_operand" "")]
+ [(match_operand:V2DI 0 "register_operand")
+ (match_operand:V4SI 1 "register_operand")
+ (match_operand:V4SI 2 "register_operand")]
"TARGET_SSE2"
{
rtx op1, op2, t1, t2;
})
(define_expand "sdot_prod<mode>"
- [(match_operand:<sseunpackmode> 0 "register_operand" "")
- (match_operand:VI2_AVX2 1 "register_operand" "")
- (match_operand:VI2_AVX2 2 "register_operand" "")
- (match_operand:<sseunpackmode> 3 "register_operand" "")]
+ [(match_operand:<sseunpackmode> 0 "register_operand")
+ (match_operand:VI2_AVX2 1 "register_operand")
+ (match_operand:VI2_AVX2 2 "register_operand")
+ (match_operand:<sseunpackmode> 3 "register_operand")]
"TARGET_SSE2"
{
rtx t = gen_reg_rtx (<sseunpackmode>mode);
[(zero_extend "sse2") (sign_extend "sse4_1")])
(define_expand "<s>dot_prodv4si"
- [(match_operand:V2DI 0 "register_operand" "")
- (any_extend:V2DI (match_operand:V4SI 1 "register_operand" ""))
- (match_operand:V4SI 2 "register_operand" "")
- (match_operand:V2DI 3 "register_operand" "")]
+ [(match_operand:V2DI 0 "register_operand")
+ (any_extend:V2DI (match_operand:V4SI 1 "register_operand"))
+ (match_operand:V4SI 2 "register_operand")
+ (match_operand:V2DI 3 "register_operand")]
"<CODE> == ZERO_EXTEND ? TARGET_SSE2 : TARGET_SSE4_1"
{
rtx t1, t2, t3, t4;
})
(define_expand "<s>dot_prodv8si"
- [(match_operand:V4DI 0 "register_operand" "")
- (any_extend:V4DI (match_operand:V8SI 1 "register_operand" ""))
- (match_operand:V8SI 2 "register_operand" "")
- (match_operand:V4DI 3 "register_operand" "")]
+ [(match_operand:V4DI 0 "register_operand")
+ (any_extend:V4DI (match_operand:V8SI 1 "register_operand"))
+ (match_operand:V8SI 2 "register_operand")
+ (match_operand:V4DI 3 "register_operand")]
"TARGET_AVX2"
{
rtx t1, t2, t3, t4;
[(set_attr "isa" "noavx,avx")
(set_attr "type" "sseishft")
(set (attr "length_immediate")
- (if_then_else (match_operand 2 "const_int_operand" "")
+ (if_then_else (match_operand 2 "const_int_operand")
(const_string "1")
(const_string "0")))
(set_attr "prefix_data16" "1,*")
[(set_attr "isa" "noavx,avx")
(set_attr "type" "sseishft")
(set (attr "length_immediate")
- (if_then_else (match_operand 2 "const_int_operand" "")
+ (if_then_else (match_operand 2 "const_int_operand")
(const_string "1")
(const_string "0")))
(set_attr "prefix_data16" "1,*")
(set_attr "mode" "<sseinsnmode>")])
(define_expand "vec_shl_<mode>"
- [(set (match_operand:VI_128 0 "register_operand" "")
+ [(set (match_operand:VI_128 0 "register_operand")
(ashift:V1TI
- (match_operand:VI_128 1 "register_operand" "")
- (match_operand:SI 2 "const_0_to_255_mul_8_operand" "")))]
+ (match_operand:VI_128 1 "register_operand")
+ (match_operand:SI 2 "const_0_to_255_mul_8_operand")))]
"TARGET_SSE2"
{
operands[0] = gen_lowpart (V1TImode, operands[0]);
(set_attr "mode" "<sseinsnmode>")])
(define_expand "vec_shr_<mode>"
- [(set (match_operand:VI_128 0 "register_operand" "")
+ [(set (match_operand:VI_128 0 "register_operand")
(lshiftrt:V1TI
- (match_operand:VI_128 1 "register_operand" "")
- (match_operand:SI 2 "const_0_to_255_mul_8_operand" "")))]
+ (match_operand:VI_128 1 "register_operand")
+ (match_operand:SI 2 "const_0_to_255_mul_8_operand")))]
"TARGET_SSE2"
{
operands[0] = gen_lowpart (V1TImode, operands[0]);
(define_expand "<code><mode>3"
- [(set (match_operand:VI124_256 0 "register_operand" "")
+ [(set (match_operand:VI124_256 0 "register_operand")
(maxmin:VI124_256
- (match_operand:VI124_256 1 "nonimmediate_operand" "")
- (match_operand:VI124_256 2 "nonimmediate_operand" "")))]
+ (match_operand:VI124_256 1 "nonimmediate_operand")
+ (match_operand:VI124_256 2 "nonimmediate_operand")))]
"TARGET_AVX2"
"ix86_fixup_binary_operands_no_copy (<CODE>, <MODE>mode, operands);")
(set_attr "mode" "OI")])
(define_expand "<code><mode>3"
- [(set (match_operand:VI8_AVX2 0 "register_operand" "")
+ [(set (match_operand:VI8_AVX2 0 "register_operand")
(maxmin:VI8_AVX2
- (match_operand:VI8_AVX2 1 "register_operand" "")
- (match_operand:VI8_AVX2 2 "register_operand" "")))]
+ (match_operand:VI8_AVX2 1 "register_operand")
+ (match_operand:VI8_AVX2 2 "register_operand")))]
"TARGET_SSE4_2"
{
enum rtx_code code;
})
(define_expand "<code><mode>3"
- [(set (match_operand:VI124_128 0 "register_operand" "")
+ [(set (match_operand:VI124_128 0 "register_operand")
(smaxmin:VI124_128
- (match_operand:VI124_128 1 "nonimmediate_operand" "")
- (match_operand:VI124_128 2 "nonimmediate_operand" "")))]
+ (match_operand:VI124_128 1 "nonimmediate_operand")
+ (match_operand:VI124_128 2 "nonimmediate_operand")))]
"TARGET_SSE2"
{
if (TARGET_SSE4_1 || <MODE>mode == V8HImode)
(set_attr "mode" "TI")])
(define_expand "<code><mode>3"
- [(set (match_operand:VI124_128 0 "register_operand" "")
+ [(set (match_operand:VI124_128 0 "register_operand")
(umaxmin:VI124_128
- (match_operand:VI124_128 1 "nonimmediate_operand" "")
- (match_operand:VI124_128 2 "nonimmediate_operand" "")))]
+ (match_operand:VI124_128 1 "nonimmediate_operand")
+ (match_operand:VI124_128 2 "nonimmediate_operand")))]
"TARGET_SSE2"
{
if (TARGET_SSE4_1 || <MODE>mode == V16QImode)
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
(define_expand "avx2_eq<mode>3"
- [(set (match_operand:VI_256 0 "register_operand" "")
+ [(set (match_operand:VI_256 0 "register_operand")
(eq:VI_256
- (match_operand:VI_256 1 "nonimmediate_operand" "")
- (match_operand:VI_256 2 "nonimmediate_operand" "")))]
+ (match_operand:VI_256 1 "nonimmediate_operand")
+ (match_operand:VI_256 2 "nonimmediate_operand")))]
"TARGET_AVX2"
"ix86_fixup_binary_operands_no_copy (EQ, <MODE>mode, operands);")
(set_attr "mode" "TI")])
(define_expand "sse2_eq<mode>3"
- [(set (match_operand:VI124_128 0 "register_operand" "")
+ [(set (match_operand:VI124_128 0 "register_operand")
(eq:VI124_128
- (match_operand:VI124_128 1 "nonimmediate_operand" "")
- (match_operand:VI124_128 2 "nonimmediate_operand" "")))]
+ (match_operand:VI124_128 1 "nonimmediate_operand")
+ (match_operand:VI124_128 2 "nonimmediate_operand")))]
"TARGET_SSE2 && !TARGET_XOP "
"ix86_fixup_binary_operands_no_copy (EQ, <MODE>mode, operands);")
(define_expand "sse4_1_eqv2di3"
- [(set (match_operand:V2DI 0 "register_operand" "")
+ [(set (match_operand:V2DI 0 "register_operand")
(eq:V2DI
- (match_operand:V2DI 1 "nonimmediate_operand" "")
- (match_operand:V2DI 2 "nonimmediate_operand" "")))]
+ (match_operand:V2DI 1 "nonimmediate_operand")
+ (match_operand:V2DI 2 "nonimmediate_operand")))]
"TARGET_SSE4_1"
"ix86_fixup_binary_operands_no_copy (EQ, V2DImode, operands);")
(set_attr "mode" "TI")])
(define_expand "vcond<V_256:mode><VI_256:mode>"
- [(set (match_operand:V_256 0 "register_operand" "")
+ [(set (match_operand:V_256 0 "register_operand")
(if_then_else:V_256
(match_operator 3 ""
- [(match_operand:VI_256 4 "nonimmediate_operand" "")
- (match_operand:VI_256 5 "general_operand" "")])
- (match_operand:V_256 1 "" "")
- (match_operand:V_256 2 "" "")))]
+ [(match_operand:VI_256 4 "nonimmediate_operand")
+ (match_operand:VI_256 5 "general_operand")])
+ (match_operand:V_256 1)
+ (match_operand:V_256 2)))]
"TARGET_AVX2
&& (GET_MODE_NUNITS (<V_256:MODE>mode)
== GET_MODE_NUNITS (<VI_256:MODE>mode))"
})
(define_expand "vcond<V_128:mode><VI124_128:mode>"
- [(set (match_operand:V_128 0 "register_operand" "")
+ [(set (match_operand:V_128 0 "register_operand")
(if_then_else:V_128
(match_operator 3 ""
- [(match_operand:VI124_128 4 "nonimmediate_operand" "")
- (match_operand:VI124_128 5 "general_operand" "")])
- (match_operand:V_128 1 "" "")
- (match_operand:V_128 2 "" "")))]
+ [(match_operand:VI124_128 4 "nonimmediate_operand")
+ (match_operand:VI124_128 5 "general_operand")])
+ (match_operand:V_128 1)
+ (match_operand:V_128 2)))]
"TARGET_SSE2
&& (GET_MODE_NUNITS (<V_128:MODE>mode)
== GET_MODE_NUNITS (<VI124_128:MODE>mode))"
})
(define_expand "vcond<VI8F_128:mode>v2di"
- [(set (match_operand:VI8F_128 0 "register_operand" "")
+ [(set (match_operand:VI8F_128 0 "register_operand")
(if_then_else:VI8F_128
(match_operator 3 ""
- [(match_operand:V2DI 4 "nonimmediate_operand" "")
- (match_operand:V2DI 5 "general_operand" "")])
- (match_operand:VI8F_128 1 "" "")
- (match_operand:VI8F_128 2 "" "")))]
+ [(match_operand:V2DI 4 "nonimmediate_operand")
+ (match_operand:V2DI 5 "general_operand")])
+ (match_operand:VI8F_128 1)
+ (match_operand:VI8F_128 2)))]
"TARGET_SSE4_2"
{
bool ok = ix86_expand_int_vcond (operands);
})
(define_expand "vcondu<V_256:mode><VI_256:mode>"
- [(set (match_operand:V_256 0 "register_operand" "")
+ [(set (match_operand:V_256 0 "register_operand")
(if_then_else:V_256
(match_operator 3 ""
- [(match_operand:VI_256 4 "nonimmediate_operand" "")
- (match_operand:VI_256 5 "nonimmediate_operand" "")])
- (match_operand:V_256 1 "general_operand" "")
- (match_operand:V_256 2 "general_operand" "")))]
+ [(match_operand:VI_256 4 "nonimmediate_operand")
+ (match_operand:VI_256 5 "nonimmediate_operand")])
+ (match_operand:V_256 1 "general_operand")
+ (match_operand:V_256 2 "general_operand")))]
"TARGET_AVX2
&& (GET_MODE_NUNITS (<V_256:MODE>mode)
== GET_MODE_NUNITS (<VI_256:MODE>mode))"
})
(define_expand "vcondu<V_128:mode><VI124_128:mode>"
- [(set (match_operand:V_128 0 "register_operand" "")
+ [(set (match_operand:V_128 0 "register_operand")
(if_then_else:V_128
(match_operator 3 ""
- [(match_operand:VI124_128 4 "nonimmediate_operand" "")
- (match_operand:VI124_128 5 "nonimmediate_operand" "")])
- (match_operand:V_128 1 "general_operand" "")
- (match_operand:V_128 2 "general_operand" "")))]
+ [(match_operand:VI124_128 4 "nonimmediate_operand")
+ (match_operand:VI124_128 5 "nonimmediate_operand")])
+ (match_operand:V_128 1 "general_operand")
+ (match_operand:V_128 2 "general_operand")))]
"TARGET_SSE2
&& (GET_MODE_NUNITS (<V_128:MODE>mode)
== GET_MODE_NUNITS (<VI124_128:MODE>mode))"
})
(define_expand "vcondu<VI8F_128:mode>v2di"
- [(set (match_operand:VI8F_128 0 "register_operand" "")
+ [(set (match_operand:VI8F_128 0 "register_operand")
(if_then_else:VI8F_128
(match_operator 3 ""
- [(match_operand:V2DI 4 "nonimmediate_operand" "")
- (match_operand:V2DI 5 "nonimmediate_operand" "")])
- (match_operand:VI8F_128 1 "general_operand" "")
- (match_operand:VI8F_128 2 "general_operand" "")))]
+ [(match_operand:V2DI 4 "nonimmediate_operand")
+ (match_operand:V2DI 5 "nonimmediate_operand")])
+ (match_operand:VI8F_128 1 "general_operand")
+ (match_operand:VI8F_128 2 "general_operand")))]
"TARGET_SSE4_2"
{
bool ok = ix86_expand_int_vcond (operands);
(V8SF "TARGET_AVX2") (V4DF "TARGET_AVX2")])
(define_expand "vec_perm<mode>"
- [(match_operand:VEC_PERM_AVX2 0 "register_operand" "")
- (match_operand:VEC_PERM_AVX2 1 "register_operand" "")
- (match_operand:VEC_PERM_AVX2 2 "register_operand" "")
- (match_operand:<sseintvecmode> 3 "register_operand" "")]
+ [(match_operand:VEC_PERM_AVX2 0 "register_operand")
+ (match_operand:VEC_PERM_AVX2 1 "register_operand")
+ (match_operand:VEC_PERM_AVX2 2 "register_operand")
+ (match_operand:<sseintvecmode> 3 "register_operand")]
"TARGET_SSSE3 || TARGET_AVX || TARGET_XOP"
{
ix86_expand_vec_perm (operands);
(V32QI "TARGET_AVX2") (V16HI "TARGET_AVX2")])
(define_expand "vec_perm_const<mode>"
- [(match_operand:VEC_PERM_CONST 0 "register_operand" "")
- (match_operand:VEC_PERM_CONST 1 "register_operand" "")
- (match_operand:VEC_PERM_CONST 2 "register_operand" "")
- (match_operand:<sseintvecmode> 3 "" "")]
+ [(match_operand:VEC_PERM_CONST 0 "register_operand")
+ (match_operand:VEC_PERM_CONST 1 "register_operand")
+ (match_operand:VEC_PERM_CONST 2 "register_operand")
+ (match_operand:<sseintvecmode> 3)]
""
{
if (ix86_expand_vec_perm_const (operands))
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
(define_expand "one_cmpl<mode>2"
- [(set (match_operand:VI 0 "register_operand" "")
- (xor:VI (match_operand:VI 1 "nonimmediate_operand" "")
+ [(set (match_operand:VI 0 "register_operand")
+ (xor:VI (match_operand:VI 1 "nonimmediate_operand")
(match_dup 2)))]
"TARGET_SSE"
{
})
(define_expand "<sse2_avx2>_andnot<mode>3"
- [(set (match_operand:VI_AVX2 0 "register_operand" "")
+ [(set (match_operand:VI_AVX2 0 "register_operand")
(and:VI_AVX2
- (not:VI_AVX2 (match_operand:VI_AVX2 1 "register_operand" ""))
- (match_operand:VI_AVX2 2 "nonimmediate_operand" "")))]
+ (not:VI_AVX2 (match_operand:VI_AVX2 1 "register_operand"))
+ (match_operand:VI_AVX2 2 "nonimmediate_operand")))]
"TARGET_SSE2")
(define_insn "*andnot<mode>3"
(const_string "<sseinsnmode>")))])
(define_expand "<code><mode>3"
- [(set (match_operand:VI 0 "register_operand" "")
+ [(set (match_operand:VI 0 "register_operand")
(any_logic:VI
- (match_operand:VI 1 "nonimmediate_operand" "")
- (match_operand:VI 2 "nonimmediate_operand" "")))]
+ (match_operand:VI 1 "nonimmediate_operand")
+ (match_operand:VI 2 "nonimmediate_operand")))]
"TARGET_SSE"
"ix86_fixup_binary_operands_no_copy (<CODE>, <MODE>mode, operands);")
(set_attr "mode" "TI")])
(define_expand "<code>tf3"
- [(set (match_operand:TF 0 "register_operand" "")
+ [(set (match_operand:TF 0 "register_operand")
(any_logic:TF
- (match_operand:TF 1 "nonimmediate_operand" "")
- (match_operand:TF 2 "nonimmediate_operand" "")))]
+ (match_operand:TF 1 "nonimmediate_operand")
+ (match_operand:TF 2 "nonimmediate_operand")))]
"TARGET_SSE2"
"ix86_fixup_binary_operands_no_copy (<CODE>, TFmode, operands);")
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
(define_expand "vec_pack_trunc_<mode>"
- [(match_operand:<ssepackmode> 0 "register_operand" "")
- (match_operand:VI248_AVX2 1 "register_operand" "")
- (match_operand:VI248_AVX2 2 "register_operand" "")]
+ [(match_operand:<ssepackmode> 0 "register_operand")
+ (match_operand:VI248_AVX2 1 "register_operand")
+ (match_operand:VI248_AVX2 2 "register_operand")]
"TARGET_SSE2"
{
rtx op1 = gen_lowpart (<ssepackmode>mode, operands[1]);
(vec_duplicate:PINSR_MODE
(match_operand:<ssescalarmode> 2 "nonimmediate_operand" "r,m,r,m"))
(match_operand:PINSR_MODE 1 "register_operand" "0,0,x,x")
- (match_operand:SI 3 "const_int_operand" "")))]
+ (match_operand:SI 3 "const_int_operand")))]
"TARGET_SSE2
&& ((unsigned) exact_log2 (INTVAL (operands[3]))
< GET_MODE_NUNITS (<MODE>mode))"
(set_attr "mode" "TI")])
(define_expand "avx2_pshufdv3"
- [(match_operand:V8SI 0 "register_operand" "")
- (match_operand:V8SI 1 "nonimmediate_operand" "")
- (match_operand:SI 2 "const_0_to_255_operand" "")]
+ [(match_operand:V8SI 0 "register_operand")
+ (match_operand:V8SI 1 "nonimmediate_operand")
+ (match_operand:SI 2 "const_0_to_255_operand")]
"TARGET_AVX2"
{
int mask = INTVAL (operands[2]);
[(set (match_operand:V8SI 0 "register_operand" "=x")
(vec_select:V8SI
(match_operand:V8SI 1 "nonimmediate_operand" "xm")
- (parallel [(match_operand 2 "const_0_to_3_operand" "")
- (match_operand 3 "const_0_to_3_operand" "")
- (match_operand 4 "const_0_to_3_operand" "")
- (match_operand 5 "const_0_to_3_operand" "")
- (match_operand 6 "const_4_to_7_operand" "")
- (match_operand 7 "const_4_to_7_operand" "")
- (match_operand 8 "const_4_to_7_operand" "")
- (match_operand 9 "const_4_to_7_operand" "")])))]
+ (parallel [(match_operand 2 "const_0_to_3_operand")
+ (match_operand 3 "const_0_to_3_operand")
+ (match_operand 4 "const_0_to_3_operand")
+ (match_operand 5 "const_0_to_3_operand")
+ (match_operand 6 "const_4_to_7_operand")
+ (match_operand 7 "const_4_to_7_operand")
+ (match_operand 8 "const_4_to_7_operand")
+ (match_operand 9 "const_4_to_7_operand")])))]
"TARGET_AVX2
&& INTVAL (operands[2]) + 4 == INTVAL (operands[6])
&& INTVAL (operands[3]) + 4 == INTVAL (operands[7])
(set_attr "mode" "OI")])
(define_expand "sse2_pshufd"
- [(match_operand:V4SI 0 "register_operand" "")
- (match_operand:V4SI 1 "nonimmediate_operand" "")
- (match_operand:SI 2 "const_int_operand" "")]
+ [(match_operand:V4SI 0 "register_operand")
+ (match_operand:V4SI 1 "nonimmediate_operand")
+ (match_operand:SI 2 "const_int_operand")]
"TARGET_SSE2"
{
int mask = INTVAL (operands[2]);
[(set (match_operand:V4SI 0 "register_operand" "=x")
(vec_select:V4SI
(match_operand:V4SI 1 "nonimmediate_operand" "xm")
- (parallel [(match_operand 2 "const_0_to_3_operand" "")
- (match_operand 3 "const_0_to_3_operand" "")
- (match_operand 4 "const_0_to_3_operand" "")
- (match_operand 5 "const_0_to_3_operand" "")])))]
+ (parallel [(match_operand 2 "const_0_to_3_operand")
+ (match_operand 3 "const_0_to_3_operand")
+ (match_operand 4 "const_0_to_3_operand")
+ (match_operand 5 "const_0_to_3_operand")])))]
"TARGET_SSE2"
{
int mask = 0;
(set_attr "mode" "TI")])
(define_expand "avx2_pshuflwv3"
- [(match_operand:V16HI 0 "register_operand" "")
- (match_operand:V16HI 1 "nonimmediate_operand" "")
- (match_operand:SI 2 "const_0_to_255_operand" "")]
+ [(match_operand:V16HI 0 "register_operand")
+ (match_operand:V16HI 1 "nonimmediate_operand")
+ (match_operand:SI 2 "const_0_to_255_operand")]
"TARGET_AVX2"
{
int mask = INTVAL (operands[2]);
[(set (match_operand:V16HI 0 "register_operand" "=x")
(vec_select:V16HI
(match_operand:V16HI 1 "nonimmediate_operand" "xm")
- (parallel [(match_operand 2 "const_0_to_3_operand" "")
- (match_operand 3 "const_0_to_3_operand" "")
- (match_operand 4 "const_0_to_3_operand" "")
- (match_operand 5 "const_0_to_3_operand" "")
+ (parallel [(match_operand 2 "const_0_to_3_operand")
+ (match_operand 3 "const_0_to_3_operand")
+ (match_operand 4 "const_0_to_3_operand")
+ (match_operand 5 "const_0_to_3_operand")
(const_int 4)
(const_int 5)
(const_int 6)
(const_int 7)
- (match_operand 6 "const_8_to_11_operand" "")
- (match_operand 7 "const_8_to_11_operand" "")
- (match_operand 8 "const_8_to_11_operand" "")
- (match_operand 9 "const_8_to_11_operand" "")
+ (match_operand 6 "const_8_to_11_operand")
+ (match_operand 7 "const_8_to_11_operand")
+ (match_operand 8 "const_8_to_11_operand")
+ (match_operand 9 "const_8_to_11_operand")
(const_int 12)
(const_int 13)
(const_int 14)
(set_attr "mode" "OI")])
(define_expand "sse2_pshuflw"
- [(match_operand:V8HI 0 "register_operand" "")
- (match_operand:V8HI 1 "nonimmediate_operand" "")
- (match_operand:SI 2 "const_int_operand" "")]
+ [(match_operand:V8HI 0 "register_operand")
+ (match_operand:V8HI 1 "nonimmediate_operand")
+ (match_operand:SI 2 "const_int_operand")]
"TARGET_SSE2"
{
int mask = INTVAL (operands[2]);
[(set (match_operand:V8HI 0 "register_operand" "=x")
(vec_select:V8HI
(match_operand:V8HI 1 "nonimmediate_operand" "xm")
- (parallel [(match_operand 2 "const_0_to_3_operand" "")
- (match_operand 3 "const_0_to_3_operand" "")
- (match_operand 4 "const_0_to_3_operand" "")
- (match_operand 5 "const_0_to_3_operand" "")
+ (parallel [(match_operand 2 "const_0_to_3_operand")
+ (match_operand 3 "const_0_to_3_operand")
+ (match_operand 4 "const_0_to_3_operand")
+ (match_operand 5 "const_0_to_3_operand")
(const_int 4)
(const_int 5)
(const_int 6)
(set_attr "mode" "TI")])
(define_expand "avx2_pshufhwv3"
- [(match_operand:V16HI 0 "register_operand" "")
- (match_operand:V16HI 1 "nonimmediate_operand" "")
- (match_operand:SI 2 "const_0_to_255_operand" "")]
+ [(match_operand:V16HI 0 "register_operand")
+ (match_operand:V16HI 1 "nonimmediate_operand")
+ (match_operand:SI 2 "const_0_to_255_operand")]
"TARGET_AVX2"
{
int mask = INTVAL (operands[2]);
(const_int 1)
(const_int 2)
(const_int 3)
- (match_operand 2 "const_4_to_7_operand" "")
- (match_operand 3 "const_4_to_7_operand" "")
- (match_operand 4 "const_4_to_7_operand" "")
- (match_operand 5 "const_4_to_7_operand" "")
+ (match_operand 2 "const_4_to_7_operand")
+ (match_operand 3 "const_4_to_7_operand")
+ (match_operand 4 "const_4_to_7_operand")
+ (match_operand 5 "const_4_to_7_operand")
(const_int 8)
(const_int 9)
(const_int 10)
(const_int 11)
- (match_operand 6 "const_12_to_15_operand" "")
- (match_operand 7 "const_12_to_15_operand" "")
- (match_operand 8 "const_12_to_15_operand" "")
- (match_operand 9 "const_12_to_15_operand" "")])))]
+ (match_operand 6 "const_12_to_15_operand")
+ (match_operand 7 "const_12_to_15_operand")
+ (match_operand 8 "const_12_to_15_operand")
+ (match_operand 9 "const_12_to_15_operand")])))]
"TARGET_AVX2
&& INTVAL (operands[2]) + 8 == INTVAL (operands[6])
&& INTVAL (operands[3]) + 8 == INTVAL (operands[7])
(set_attr "mode" "OI")])
(define_expand "sse2_pshufhw"
- [(match_operand:V8HI 0 "register_operand" "")
- (match_operand:V8HI 1 "nonimmediate_operand" "")
- (match_operand:SI 2 "const_int_operand" "")]
+ [(match_operand:V8HI 0 "register_operand")
+ (match_operand:V8HI 1 "nonimmediate_operand")
+ (match_operand:SI 2 "const_int_operand")]
"TARGET_SSE2"
{
int mask = INTVAL (operands[2]);
(const_int 1)
(const_int 2)
(const_int 3)
- (match_operand 2 "const_4_to_7_operand" "")
- (match_operand 3 "const_4_to_7_operand" "")
- (match_operand 4 "const_4_to_7_operand" "")
- (match_operand 5 "const_4_to_7_operand" "")])))]
+ (match_operand 2 "const_4_to_7_operand")
+ (match_operand 3 "const_4_to_7_operand")
+ (match_operand 4 "const_4_to_7_operand")
+ (match_operand 5 "const_4_to_7_operand")])))]
"TARGET_SSE2"
{
int mask = 0;
(set_attr "mode" "TI")])
(define_expand "sse2_loadd"
- [(set (match_operand:V4SI 0 "register_operand" "")
+ [(set (match_operand:V4SI 0 "register_operand")
(vec_merge:V4SI
(vec_duplicate:V4SI
- (match_operand:SI 1 "nonimmediate_operand" ""))
+ (match_operand:SI 1 "nonimmediate_operand"))
(match_dup 2)
(const_int 1)))]
"TARGET_SSE"
[(set (match_operand:SI 0 "register_operand" "=r")
(vec_select:SI
(match_operand:V4SI 1 "memory_operand" "o")
- (parallel [(match_operand 2 "const_0_to_3_operand" "")])))]
+ (parallel [(match_operand 2 "const_0_to_3_operand")])))]
""
"#"
"reload_completed"
})
(define_expand "sse_storeq"
- [(set (match_operand:DI 0 "nonimmediate_operand" "")
+ [(set (match_operand:DI 0 "nonimmediate_operand")
(vec_select:DI
- (match_operand:V2DI 1 "register_operand" "")
+ (match_operand:V2DI 1 "register_operand")
(parallel [(const_int 0)])))]
"TARGET_SSE")
"#")
(define_split
- [(set (match_operand:DI 0 "nonimmediate_operand" "")
+ [(set (match_operand:DI 0 "nonimmediate_operand")
(vec_select:DI
- (match_operand:V2DI 1 "register_operand" "")
+ (match_operand:V2DI 1 "register_operand")
(parallel [(const_int 0)])))]
"TARGET_SSE
&& reload_completed
(set_attr "mode" "TI,TI,TI,TI,V4SF,V2SF,V2SF")])
(define_expand "vec_unpacks_lo_<mode>"
- [(match_operand:<sseunpackmode> 0 "register_operand" "")
- (match_operand:VI124_AVX2 1 "register_operand" "")]
+ [(match_operand:<sseunpackmode> 0 "register_operand")
+ (match_operand:VI124_AVX2 1 "register_operand")]
"TARGET_SSE2"
"ix86_expand_sse_unpack (operands, false, false); DONE;")
(define_expand "vec_unpacks_hi_<mode>"
- [(match_operand:<sseunpackmode> 0 "register_operand" "")
- (match_operand:VI124_AVX2 1 "register_operand" "")]
+ [(match_operand:<sseunpackmode> 0 "register_operand")
+ (match_operand:VI124_AVX2 1 "register_operand")]
"TARGET_SSE2"
"ix86_expand_sse_unpack (operands, false, true); DONE;")
(define_expand "vec_unpacku_lo_<mode>"
- [(match_operand:<sseunpackmode> 0 "register_operand" "")
- (match_operand:VI124_AVX2 1 "register_operand" "")]
+ [(match_operand:<sseunpackmode> 0 "register_operand")
+ (match_operand:VI124_AVX2 1 "register_operand")]
"TARGET_SSE2"
"ix86_expand_sse_unpack (operands, true, false); DONE;")
(define_expand "vec_unpacku_hi_<mode>"
- [(match_operand:<sseunpackmode> 0 "register_operand" "")
- (match_operand:VI124_AVX2 1 "register_operand" "")]
+ [(match_operand:<sseunpackmode> 0 "register_operand")
+ (match_operand:VI124_AVX2 1 "register_operand")]
"TARGET_SSE2"
"ix86_expand_sse_unpack (operands, true, true); DONE;")
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
(define_expand "avx2_uavgv32qi3"
- [(set (match_operand:V32QI 0 "register_operand" "")
+ [(set (match_operand:V32QI 0 "register_operand")
(truncate:V32QI
(lshiftrt:V32HI
(plus:V32HI
(plus:V32HI
(zero_extend:V32HI
- (match_operand:V32QI 1 "nonimmediate_operand" ""))
+ (match_operand:V32QI 1 "nonimmediate_operand"))
(zero_extend:V32HI
- (match_operand:V32QI 2 "nonimmediate_operand" "")))
+ (match_operand:V32QI 2 "nonimmediate_operand")))
(const_vector:V32QI [(const_int 1) (const_int 1)
(const_int 1) (const_int 1)
(const_int 1) (const_int 1)
"ix86_fixup_binary_operands_no_copy (PLUS, V32QImode, operands);")
(define_expand "sse2_uavgv16qi3"
- [(set (match_operand:V16QI 0 "register_operand" "")
+ [(set (match_operand:V16QI 0 "register_operand")
(truncate:V16QI
(lshiftrt:V16HI
(plus:V16HI
(plus:V16HI
(zero_extend:V16HI
- (match_operand:V16QI 1 "nonimmediate_operand" ""))
+ (match_operand:V16QI 1 "nonimmediate_operand"))
(zero_extend:V16HI
- (match_operand:V16QI 2 "nonimmediate_operand" "")))
+ (match_operand:V16QI 2 "nonimmediate_operand")))
(const_vector:V16QI [(const_int 1) (const_int 1)
(const_int 1) (const_int 1)
(const_int 1) (const_int 1)
(set_attr "mode" "TI")])
(define_expand "avx2_uavgv16hi3"
- [(set (match_operand:V16HI 0 "register_operand" "")
+ [(set (match_operand:V16HI 0 "register_operand")
(truncate:V16HI
(lshiftrt:V16SI
(plus:V16SI
(plus:V16SI
(zero_extend:V16SI
- (match_operand:V16HI 1 "nonimmediate_operand" ""))
+ (match_operand:V16HI 1 "nonimmediate_operand"))
(zero_extend:V16SI
- (match_operand:V16HI 2 "nonimmediate_operand" "")))
+ (match_operand:V16HI 2 "nonimmediate_operand")))
(const_vector:V16HI [(const_int 1) (const_int 1)
(const_int 1) (const_int 1)
(const_int 1) (const_int 1)
"ix86_fixup_binary_operands_no_copy (PLUS, V16HImode, operands);")
(define_expand "sse2_uavgv8hi3"
- [(set (match_operand:V8HI 0 "register_operand" "")
+ [(set (match_operand:V8HI 0 "register_operand")
(truncate:V8HI
(lshiftrt:V8SI
(plus:V8SI
(plus:V8SI
(zero_extend:V8SI
- (match_operand:V8HI 1 "nonimmediate_operand" ""))
+ (match_operand:V8HI 1 "nonimmediate_operand"))
(zero_extend:V8SI
- (match_operand:V8HI 2 "nonimmediate_operand" "")))
+ (match_operand:V8HI 2 "nonimmediate_operand")))
(const_vector:V8HI [(const_int 1) (const_int 1)
(const_int 1) (const_int 1)
(const_int 1) (const_int 1)
(set_attr "mode" "SI")])
(define_expand "sse2_maskmovdqu"
- [(set (match_operand:V16QI 0 "memory_operand" "")
- (unspec:V16QI [(match_operand:V16QI 1 "register_operand" "")
- (match_operand:V16QI 2 "register_operand" "")
+ [(set (match_operand:V16QI 0 "memory_operand")
+ (unspec:V16QI [(match_operand:V16QI 1 "register_operand")
+ (match_operand:V16QI 2 "register_operand")
(match_dup 0)]
UNSPEC_MASKMOV))]
"TARGET_SSE2")
(set_attr "mode" "DI")])
(define_expand "avx2_umulhrswv16hi3"
- [(set (match_operand:V16HI 0 "register_operand" "")
+ [(set (match_operand:V16HI 0 "register_operand")
(truncate:V16HI
(lshiftrt:V16SI
(plus:V16SI
(lshiftrt:V16SI
(mult:V16SI
(sign_extend:V16SI
- (match_operand:V16HI 1 "nonimmediate_operand" ""))
+ (match_operand:V16HI 1 "nonimmediate_operand"))
(sign_extend:V16SI
- (match_operand:V16HI 2 "nonimmediate_operand" "")))
+ (match_operand:V16HI 2 "nonimmediate_operand")))
(const_int 14))
(const_vector:V16HI [(const_int 1) (const_int 1)
(const_int 1) (const_int 1)
(set_attr "mode" "OI")])
(define_expand "ssse3_pmulhrswv8hi3"
- [(set (match_operand:V8HI 0 "register_operand" "")
+ [(set (match_operand:V8HI 0 "register_operand")
(truncate:V8HI
(lshiftrt:V8SI
(plus:V8SI
(lshiftrt:V8SI
(mult:V8SI
(sign_extend:V8SI
- (match_operand:V8HI 1 "nonimmediate_operand" ""))
+ (match_operand:V8HI 1 "nonimmediate_operand"))
(sign_extend:V8SI
- (match_operand:V8HI 2 "nonimmediate_operand" "")))
+ (match_operand:V8HI 2 "nonimmediate_operand")))
(const_int 14))
(const_vector:V8HI [(const_int 1) (const_int 1)
(const_int 1) (const_int 1)
(set_attr "mode" "TI")])
(define_expand "ssse3_pmulhrswv4hi3"
- [(set (match_operand:V4HI 0 "register_operand" "")
+ [(set (match_operand:V4HI 0 "register_operand")
(truncate:V4HI
(lshiftrt:V4SI
(plus:V4SI
(lshiftrt:V4SI
(mult:V4SI
(sign_extend:V4SI
- (match_operand:V4HI 1 "nonimmediate_operand" ""))
+ (match_operand:V4HI 1 "nonimmediate_operand"))
(sign_extend:V4SI
- (match_operand:V4HI 2 "nonimmediate_operand" "")))
+ (match_operand:V4HI 2 "nonimmediate_operand")))
(const_int 14))
(const_vector:V4HI [(const_int 1) (const_int 1)
(const_int 1) (const_int 1)]))
(define_insn "sse4a_extrqi"
[(set (match_operand:V2DI 0 "register_operand" "=x")
(unspec:V2DI [(match_operand:V2DI 1 "register_operand" "0")
- (match_operand 2 "const_0_to_255_operand" "")
- (match_operand 3 "const_0_to_255_operand" "")]
+ (match_operand 2 "const_0_to_255_operand")
+ (match_operand 3 "const_0_to_255_operand")]
UNSPEC_EXTRQI))]
"TARGET_SSE4A"
"extrq\t{%3, %2, %0|%0, %2, %3}"
[(set (match_operand:V2DI 0 "register_operand" "=x")
(unspec:V2DI [(match_operand:V2DI 1 "register_operand" "0")
(match_operand:V2DI 2 "register_operand" "x")
- (match_operand 3 "const_0_to_255_operand" "")
- (match_operand 4 "const_0_to_255_operand" "")]
+ (match_operand 3 "const_0_to_255_operand")
+ (match_operand 4 "const_0_to_255_operand")]
UNSPEC_INSERTQI))]
"TARGET_SSE4A"
"insertq\t{%4, %3, %2, %0|%0, %2, %3, %4}"
(vec_merge:VF
(match_operand:VF 2 "nonimmediate_operand" "xm,xm")
(match_operand:VF 1 "register_operand" "0,x")
- (match_operand:SI 3 "const_0_to_<blendbits>_operand" "")))]
+ (match_operand:SI 3 "const_0_to_<blendbits>_operand")))]
"TARGET_SSE4_1"
"@
blend<ssemodesuffix>\t{%3, %2, %0|%0, %2, %3}
;; The builtin uses an 8-bit immediate. Expand that.
(define_expand "avx2_pblendw"
- [(set (match_operand:V16HI 0 "register_operand" "")
+ [(set (match_operand:V16HI 0 "register_operand")
(vec_merge:V16HI
- (match_operand:V16HI 2 "nonimmediate_operand" "")
- (match_operand:V16HI 1 "register_operand" "")
- (match_operand:SI 3 "const_0_to_255_operand" "")))]
+ (match_operand:V16HI 2 "nonimmediate_operand")
+ (match_operand:V16HI 1 "register_operand")
+ (match_operand:SI 3 "const_0_to_255_operand")))]
"TARGET_AVX2"
{
HOST_WIDE_INT val = INTVAL (operands[3]) & 0xff;
(set_attr "mode" "<MODE>")])
(define_expand "<sse4_1>_round<ssemodesuffix>_sfix<avxsizesuffix>"
- [(match_operand:<sseintvecmode> 0 "register_operand" "")
- (match_operand:VF1 1 "nonimmediate_operand" "")
- (match_operand:SI 2 "const_0_to_15_operand" "")]
+ [(match_operand:<sseintvecmode> 0 "register_operand")
+ (match_operand:VF1 1 "nonimmediate_operand")
+ (match_operand:SI 2 "const_0_to_15_operand")]
"TARGET_ROUND"
{
rtx tmp = gen_reg_rtx (<MODE>mode);
})
(define_expand "<sse4_1>_round<ssemodesuffix>_vec_pack_sfix<avxsizesuffix>"
- [(match_operand:<ssepackfltmode> 0 "register_operand" "")
- (match_operand:VF2 1 "nonimmediate_operand" "")
- (match_operand:VF2 2 "nonimmediate_operand" "")
- (match_operand:SI 3 "const_0_to_15_operand" "")]
+ [(match_operand:<ssepackfltmode> 0 "register_operand")
+ (match_operand:VF2 1 "nonimmediate_operand")
+ (match_operand:VF2 2 "nonimmediate_operand")
+ (match_operand:SI 3 "const_0_to_15_operand")]
"TARGET_ROUND"
{
rtx tmp0, tmp1;
(define_expand "round<mode>2"
[(set (match_dup 4)
(plus:VF
- (match_operand:VF 1 "register_operand" "")
+ (match_operand:VF 1 "register_operand")
(match_dup 3)))
- (set (match_operand:VF 0 "register_operand" "")
+ (set (match_operand:VF 0 "register_operand")
(unspec:VF
[(match_dup 4) (match_dup 5)]
UNSPEC_ROUND))]
})
(define_expand "round<mode>2_sfix"
- [(match_operand:<sseintvecmode> 0 "register_operand" "")
- (match_operand:VF1 1 "register_operand" "")]
+ [(match_operand:<sseintvecmode> 0 "register_operand")
+ (match_operand:VF1 1 "register_operand")]
"TARGET_ROUND && !flag_trapping_math"
{
rtx tmp = gen_reg_rtx (<MODE>mode);
})
(define_expand "round<mode>2_vec_pack_sfix"
- [(match_operand:<ssepackfltmode> 0 "register_operand" "")
- (match_operand:VF2 1 "register_operand" "")
- (match_operand:VF2 2 "register_operand" "")]
+ [(match_operand:<ssepackfltmode> 0 "register_operand")
+ (match_operand:VF2 1 "register_operand")
+ (match_operand:VF2 2 "register_operand")]
"TARGET_ROUND && !flag_trapping_math"
{
rtx tmp0, tmp1;
;; XOP packed rotate instructions
(define_expand "rotl<mode>3"
- [(set (match_operand:VI_128 0 "register_operand" "")
+ [(set (match_operand:VI_128 0 "register_operand")
(rotate:VI_128
- (match_operand:VI_128 1 "nonimmediate_operand" "")
+ (match_operand:VI_128 1 "nonimmediate_operand")
(match_operand:SI 2 "general_operand")))]
"TARGET_XOP"
{
})
(define_expand "rotr<mode>3"
- [(set (match_operand:VI_128 0 "register_operand" "")
+ [(set (match_operand:VI_128 0 "register_operand")
(rotatert:VI_128
- (match_operand:VI_128 1 "nonimmediate_operand" "")
+ (match_operand:VI_128 1 "nonimmediate_operand")
(match_operand:SI 2 "general_operand")))]
"TARGET_XOP"
{
(set_attr "mode" "TI")])
(define_expand "vrotr<mode>3"
- [(match_operand:VI_128 0 "register_operand" "")
- (match_operand:VI_128 1 "register_operand" "")
- (match_operand:VI_128 2 "register_operand" "")]
+ [(match_operand:VI_128 0 "register_operand")
+ (match_operand:VI_128 1 "register_operand")
+ (match_operand:VI_128 2 "register_operand")]
"TARGET_XOP"
{
rtx reg = gen_reg_rtx (<MODE>mode);
})
(define_expand "vrotl<mode>3"
- [(match_operand:VI_128 0 "register_operand" "")
- (match_operand:VI_128 1 "register_operand" "")
- (match_operand:VI_128 2 "register_operand" "")]
+ [(match_operand:VI_128 0 "register_operand")
+ (match_operand:VI_128 1 "register_operand")
+ (match_operand:VI_128 2 "register_operand")]
"TARGET_XOP"
{
emit_insn (gen_xop_vrotl<mode>3 (operands[0], operands[1], operands[2]));
;; XOP packed shift instructions.
(define_expand "vlshr<mode>3"
- [(set (match_operand:VI12_128 0 "register_operand" "")
+ [(set (match_operand:VI12_128 0 "register_operand")
(lshiftrt:VI12_128
- (match_operand:VI12_128 1 "register_operand" "")
- (match_operand:VI12_128 2 "nonimmediate_operand" "")))]
+ (match_operand:VI12_128 1 "register_operand")
+ (match_operand:VI12_128 2 "nonimmediate_operand")))]
"TARGET_XOP"
{
rtx neg = gen_reg_rtx (<MODE>mode);
})
(define_expand "vlshr<mode>3"
- [(set (match_operand:VI48_128 0 "register_operand" "")
+ [(set (match_operand:VI48_128 0 "register_operand")
(lshiftrt:VI48_128
- (match_operand:VI48_128 1 "register_operand" "")
- (match_operand:VI48_128 2 "nonimmediate_operand" "")))]
+ (match_operand:VI48_128 1 "register_operand")
+ (match_operand:VI48_128 2 "nonimmediate_operand")))]
"TARGET_AVX2 || TARGET_XOP"
{
if (!TARGET_AVX2)
})
(define_expand "vlshr<mode>3"
- [(set (match_operand:VI48_256 0 "register_operand" "")
+ [(set (match_operand:VI48_256 0 "register_operand")
(lshiftrt:VI48_256
- (match_operand:VI48_256 1 "register_operand" "")
- (match_operand:VI48_256 2 "nonimmediate_operand" "")))]
+ (match_operand:VI48_256 1 "register_operand")
+ (match_operand:VI48_256 2 "nonimmediate_operand")))]
"TARGET_AVX2")
(define_expand "vashr<mode>3"
- [(set (match_operand:VI128_128 0 "register_operand" "")
+ [(set (match_operand:VI128_128 0 "register_operand")
(ashiftrt:VI128_128
- (match_operand:VI128_128 1 "register_operand" "")
- (match_operand:VI128_128 2 "nonimmediate_operand" "")))]
+ (match_operand:VI128_128 1 "register_operand")
+ (match_operand:VI128_128 2 "nonimmediate_operand")))]
"TARGET_XOP"
{
rtx neg = gen_reg_rtx (<MODE>mode);
})
(define_expand "vashrv4si3"
- [(set (match_operand:V4SI 0 "register_operand" "")
- (ashiftrt:V4SI (match_operand:V4SI 1 "register_operand" "")
- (match_operand:V4SI 2 "nonimmediate_operand" "")))]
+ [(set (match_operand:V4SI 0 "register_operand")
+ (ashiftrt:V4SI (match_operand:V4SI 1 "register_operand")
+ (match_operand:V4SI 2 "nonimmediate_operand")))]
"TARGET_AVX2 || TARGET_XOP"
{
if (!TARGET_AVX2)
})
(define_expand "vashrv8si3"
- [(set (match_operand:V8SI 0 "register_operand" "")
- (ashiftrt:V8SI (match_operand:V8SI 1 "register_operand" "")
- (match_operand:V8SI 2 "nonimmediate_operand" "")))]
+ [(set (match_operand:V8SI 0 "register_operand")
+ (ashiftrt:V8SI (match_operand:V8SI 1 "register_operand")
+ (match_operand:V8SI 2 "nonimmediate_operand")))]
"TARGET_AVX2")
(define_expand "vashl<mode>3"
- [(set (match_operand:VI12_128 0 "register_operand" "")
+ [(set (match_operand:VI12_128 0 "register_operand")
(ashift:VI12_128
- (match_operand:VI12_128 1 "register_operand" "")
- (match_operand:VI12_128 2 "nonimmediate_operand" "")))]
+ (match_operand:VI12_128 1 "register_operand")
+ (match_operand:VI12_128 2 "nonimmediate_operand")))]
"TARGET_XOP"
{
emit_insn (gen_xop_sha<mode>3 (operands[0], operands[1], operands[2]));
})
(define_expand "vashl<mode>3"
- [(set (match_operand:VI48_128 0 "register_operand" "")
+ [(set (match_operand:VI48_128 0 "register_operand")
(ashift:VI48_128
- (match_operand:VI48_128 1 "register_operand" "")
- (match_operand:VI48_128 2 "nonimmediate_operand" "")))]
+ (match_operand:VI48_128 1 "register_operand")
+ (match_operand:VI48_128 2 "nonimmediate_operand")))]
"TARGET_AVX2 || TARGET_XOP"
{
if (!TARGET_AVX2)
})
(define_expand "vashl<mode>3"
- [(set (match_operand:VI48_256 0 "register_operand" "")
+ [(set (match_operand:VI48_256 0 "register_operand")
(ashift:VI48_256
- (match_operand:VI48_256 1 "register_operand" "")
- (match_operand:VI48_256 2 "nonimmediate_operand" "")))]
+ (match_operand:VI48_256 1 "register_operand")
+ (match_operand:VI48_256 2 "nonimmediate_operand")))]
"TARGET_AVX2")
(define_insn "xop_sha<mode>3"
;; SSE2 doesn't have some shift variants, so define versions for XOP
(define_expand "ashlv16qi3"
- [(set (match_operand:V16QI 0 "register_operand" "")
+ [(set (match_operand:V16QI 0 "register_operand")
(ashift:V16QI
- (match_operand:V16QI 1 "register_operand" "")
- (match_operand:SI 2 "nonmemory_operand" "")))]
+ (match_operand:V16QI 1 "register_operand")
+ (match_operand:SI 2 "nonmemory_operand")))]
"TARGET_XOP"
{
rtx reg = gen_reg_rtx (V16QImode);
})
(define_expand "<shift_insn>v16qi3"
- [(set (match_operand:V16QI 0 "register_operand" "")
+ [(set (match_operand:V16QI 0 "register_operand")
(any_shiftrt:V16QI
- (match_operand:V16QI 1 "register_operand" "")
- (match_operand:SI 2 "nonmemory_operand" "")))]
+ (match_operand:V16QI 1 "register_operand")
+ (match_operand:SI 2 "nonmemory_operand")))]
"TARGET_XOP"
{
rtx reg = gen_reg_rtx (V16QImode);
})
(define_expand "ashrv2di3"
- [(set (match_operand:V2DI 0 "register_operand" "")
+ [(set (match_operand:V2DI 0 "register_operand")
(ashiftrt:V2DI
- (match_operand:V2DI 1 "register_operand" "")
- (match_operand:DI 2 "nonmemory_operand" "")))]
+ (match_operand:V2DI 1 "register_operand")
+ (match_operand:DI 2 "nonmemory_operand")))]
"TARGET_XOP"
{
rtx reg = gen_reg_rtx (V2DImode);
;; Clear the upper 128bits of AVX registers, equivalent to a NOP
;; if the upper 128bits are unused.
(define_insn "avx_vzeroupper"
- [(unspec_volatile [(match_operand 0 "const_int_operand" "")]
+ [(unspec_volatile [(match_operand 0 "const_int_operand")]
UNSPECV_VZEROUPPER)]
"TARGET_AVX"
"vzeroupper"
(set_attr "mode" "OI")])
(define_expand "avx2_perm<mode>"
- [(match_operand:VI8F_256 0 "register_operand" "")
- (match_operand:VI8F_256 1 "nonimmediate_operand" "")
- (match_operand:SI 2 "const_0_to_255_operand" "")]
+ [(match_operand:VI8F_256 0 "register_operand")
+ (match_operand:VI8F_256 1 "nonimmediate_operand")
+ (match_operand:SI 2 "const_0_to_255_operand")]
"TARGET_AVX2"
{
int mask = INTVAL (operands[2]);
[(set (match_operand:VI8F_256 0 "register_operand" "=x")
(vec_select:VI8F_256
(match_operand:VI8F_256 1 "nonimmediate_operand" "xm")
- (parallel [(match_operand 2 "const_0_to_3_operand" "")
- (match_operand 3 "const_0_to_3_operand" "")
- (match_operand 4 "const_0_to_3_operand" "")
- (match_operand 5 "const_0_to_3_operand" "")])))]
+ (parallel [(match_operand 2 "const_0_to_3_operand")
+ (match_operand 3 "const_0_to_3_operand")
+ (match_operand 4 "const_0_to_3_operand")
+ (match_operand 5 "const_0_to_3_operand")])))]
"TARGET_AVX2"
{
int mask = 0;
(set_attr "mode" "OI")])
(define_split
- [(set (match_operand:AVX_VEC_DUP_MODE 0 "register_operand" "")
+ [(set (match_operand:AVX_VEC_DUP_MODE 0 "register_operand")
(vec_duplicate:AVX_VEC_DUP_MODE
- (match_operand:<ssescalarmode> 1 "register_operand" "")))]
+ (match_operand:<ssescalarmode> 1 "register_operand")))]
"TARGET_AVX && reload_completed"
[(set (match_dup 2)
(vec_duplicate:<ssehalfvecmode> (match_dup 1)))
})
(define_expand "avx_vpermil<mode>"
- [(set (match_operand:VF2 0 "register_operand" "")
+ [(set (match_operand:VF2 0 "register_operand")
(vec_select:VF2
- (match_operand:VF2 1 "nonimmediate_operand" "")
- (match_operand:SI 2 "const_0_to_255_operand" "")))]
+ (match_operand:VF2 1 "nonimmediate_operand")
+ (match_operand:SI 2 "const_0_to_255_operand")))]
"TARGET_AVX"
{
int mask = INTVAL (operands[2]);
})
(define_expand "avx_vpermil<mode>"
- [(set (match_operand:VF1 0 "register_operand" "")
+ [(set (match_operand:VF1 0 "register_operand")
(vec_select:VF1
- (match_operand:VF1 1 "nonimmediate_operand" "")
- (match_operand:SI 2 "const_0_to_255_operand" "")))]
+ (match_operand:VF1 1 "nonimmediate_operand")
+ (match_operand:SI 2 "const_0_to_255_operand")))]
"TARGET_AVX"
{
int mask = INTVAL (operands[2]);
(vec_select:VF
(match_operand:VF 1 "nonimmediate_operand" "xm")
(match_parallel 2 ""
- [(match_operand 3 "const_int_operand" "")])))]
+ [(match_operand 3 "const_int_operand")])))]
"TARGET_AVX
&& avx_vpermilp_parallel (operands[2], <MODE>mode)"
{
(set_attr "mode" "<MODE>")])
(define_expand "avx_vperm2f128<mode>3"
- [(set (match_operand:AVX256MODE2P 0 "register_operand" "")
+ [(set (match_operand:AVX256MODE2P 0 "register_operand")
(unspec:AVX256MODE2P
- [(match_operand:AVX256MODE2P 1 "register_operand" "")
- (match_operand:AVX256MODE2P 2 "nonimmediate_operand" "")
- (match_operand:SI 3 "const_0_to_255_operand" "")]
+ [(match_operand:AVX256MODE2P 1 "register_operand")
+ (match_operand:AVX256MODE2P 2 "nonimmediate_operand")
+ (match_operand:SI 3 "const_0_to_255_operand")]
UNSPEC_VPERMIL2F128))]
"TARGET_AVX"
{
(match_operand:AVX256MODE2P 1 "register_operand" "x")
(match_operand:AVX256MODE2P 2 "nonimmediate_operand" "xm"))
(match_parallel 3 ""
- [(match_operand 4 "const_int_operand" "")])))]
+ [(match_operand 4 "const_int_operand")])))]
"TARGET_AVX
&& avx_vperm2f128_parallel (operands[3], <MODE>mode)"
{
(set_attr "mode" "<sseinsnmode>")])
(define_expand "avx_vinsertf128<mode>"
- [(match_operand:V_256 0 "register_operand" "")
- (match_operand:V_256 1 "register_operand" "")
- (match_operand:<ssehalfvecmode> 2 "nonimmediate_operand" "")
- (match_operand:SI 3 "const_0_to_1_operand" "")]
+ [(match_operand:V_256 0 "register_operand")
+ (match_operand:V_256 1 "register_operand")
+ (match_operand:<ssehalfvecmode> 2 "nonimmediate_operand")
+ (match_operand:SI 3 "const_0_to_1_operand")]
"TARGET_AVX"
{
rtx (*insn)(rtx, rtx, rtx);
})
(define_expand "vec_init<mode>"
- [(match_operand:V_256 0 "register_operand" "")
- (match_operand 1 "" "")]
+ [(match_operand:V_256 0 "register_operand")
+ (match_operand 1)]
"TARGET_AVX"
{
ix86_expand_vector_init (false, operands[0], operands[1]);
})
(define_expand "avx2_extracti128"
- [(match_operand:V2DI 0 "nonimmediate_operand" "")
- (match_operand:V4DI 1 "register_operand" "")
- (match_operand:SI 2 "const_0_to_1_operand" "")]
+ [(match_operand:V2DI 0 "nonimmediate_operand")
+ (match_operand:V4DI 1 "register_operand")
+ (match_operand:SI 2 "const_0_to_1_operand")]
"TARGET_AVX2"
{
rtx (*insn)(rtx, rtx);
})
(define_expand "avx2_inserti128"
- [(match_operand:V4DI 0 "register_operand" "")
- (match_operand:V4DI 1 "register_operand" "")
- (match_operand:V2DI 2 "nonimmediate_operand" "")
- (match_operand:SI 3 "const_0_to_1_operand" "")]
+ [(match_operand:V4DI 0 "register_operand")
+ (match_operand:V4DI 1 "register_operand")
+ (match_operand:V2DI 2 "nonimmediate_operand")
+ (match_operand:SI 3 "const_0_to_1_operand")]
"TARGET_AVX2"
{
rtx (*insn)(rtx, rtx, rtx);
(set_attr "mode" "V8SF")])
(define_expand "vcvtps2ph"
- [(set (match_operand:V8HI 0 "register_operand" "")
+ [(set (match_operand:V8HI 0 "register_operand")
(vec_concat:V8HI
- (unspec:V4HI [(match_operand:V4SF 1 "register_operand" "")
- (match_operand:SI 2 "const_0_to_255_operand" "")]
+ (unspec:V4HI [(match_operand:V4SF 1 "register_operand")
+ (match_operand:SI 2 "const_0_to_255_operand")]
UNSPEC_VCVTPS2PH)
(match_dup 3)))]
"TARGET_F16C"
(unspec:V4HI [(match_operand:V4SF 1 "register_operand" "x")
(match_operand:SI 2 "const_0_to_255_operand" "N")]
UNSPEC_VCVTPS2PH)
- (match_operand:V4HI 3 "const0_operand" "")))]
+ (match_operand:V4HI 3 "const0_operand")))]
"TARGET_F16C"
"vcvtps2ph\t{%2, %1, %0|%0, %1, %2}"
[(set_attr "type" "ssecvt")
(V8SI "V4SI") (V8SF "V4SF")])
(define_expand "avx2_gathersi<mode>"
- [(parallel [(set (match_operand:VEC_GATHER_MODE 0 "register_operand" "")
+ [(parallel [(set (match_operand:VEC_GATHER_MODE 0 "register_operand")
(unspec:VEC_GATHER_MODE
- [(match_operand:VEC_GATHER_MODE 1 "register_operand" "")
+ [(match_operand:VEC_GATHER_MODE 1 "register_operand")
(mem:<ssescalarmode>
(match_par_dup 7
- [(match_operand 2 "vsib_address_operand" "")
+ [(match_operand 2 "vsib_address_operand")
(match_operand:<VEC_GATHER_IDXSI>
- 3 "register_operand" "")
- (match_operand:SI 5 "const1248_operand " "")]))
+ 3 "register_operand")
+ (match_operand:SI 5 "const1248_operand ")]))
(mem:BLK (scratch))
- (match_operand:VEC_GATHER_MODE 4 "register_operand" "")]
+ (match_operand:VEC_GATHER_MODE 4 "register_operand")]
UNSPEC_GATHER))
- (clobber (match_scratch:VEC_GATHER_MODE 6 ""))])]
+ (clobber (match_scratch:VEC_GATHER_MODE 6))])]
"TARGET_AVX2"
{
operands[7]
(set_attr "mode" "<sseinsnmode>")])
(define_expand "avx2_gatherdi<mode>"
- [(parallel [(set (match_operand:VEC_GATHER_MODE 0 "register_operand" "")
+ [(parallel [(set (match_operand:VEC_GATHER_MODE 0 "register_operand")
(unspec:VEC_GATHER_MODE
- [(match_operand:<VEC_GATHER_SRCDI> 1 "register_operand" "")
+ [(match_operand:<VEC_GATHER_SRCDI> 1 "register_operand")
(mem:<ssescalarmode>
(match_par_dup 7
- [(match_operand 2 "vsib_address_operand" "")
+ [(match_operand 2 "vsib_address_operand")
(match_operand:<VEC_GATHER_IDXDI>
- 3 "register_operand" "")
- (match_operand:SI 5 "const1248_operand " "")]))
+ 3 "register_operand")
+ (match_operand:SI 5 "const1248_operand ")]))
(mem:BLK (scratch))
(match_operand:<VEC_GATHER_SRCDI>
- 4 "register_operand" "")]
+ 4 "register_operand")]
UNSPEC_GATHER))
- (clobber (match_scratch:VEC_GATHER_MODE 6 ""))])]
+ (clobber (match_scratch:VEC_GATHER_MODE 6))])]
"TARGET_AVX2"
{
operands[7]
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