VORRQ_N_S VORRQ_N_U
])
+(define_int_iterator MVE_SHIFT_M_R [
+ VQSHLQ_M_R_S VQSHLQ_M_R_U
+ VSHLQ_M_R_S VSHLQ_M_R_U
+ ])
+
+(define_int_iterator MVE_SHIFT_M_N [
+ VQSHLQ_M_N_S VQSHLQ_M_N_U
+ VSHLQ_M_N_S VSHLQ_M_N_U
+ ])
+
+(define_int_iterator MVE_SHIFT_N [
+ VQSHLQ_N_S VQSHLQ_N_U
+ VSHLQ_N_S VSHLQ_N_U
+ ])
+
+(define_int_iterator MVE_SHIFT_R [
+ VQSHLQ_R_S VQSHLQ_R_U
+ VSHLQ_R_S VSHLQ_R_U
+ ])
+
(define_int_iterator MVE_RSHIFT_M_N [
VQRSHLQ_M_N_S VQRSHLQ_M_N_U
VRSHLQ_M_N_S VRSHLQ_M_N_U
(VQRSHLQ_M_S "vqrshl") (VQRSHLQ_M_U "vqrshl")
(VQRSHLQ_N_S "vqrshl") (VQRSHLQ_N_U "vqrshl")
(VQRSHLQ_S "vqrshl") (VQRSHLQ_U "vqrshl")
+ (VQSHLQ_M_N_S "vqshl") (VQSHLQ_M_N_U "vqshl")
+ (VQSHLQ_M_R_S "vqshl") (VQSHLQ_M_R_U "vqshl")
(VQSHLQ_M_S "vqshl") (VQSHLQ_M_U "vqshl")
+ (VQSHLQ_N_S "vqshl") (VQSHLQ_N_U "vqshl")
+ (VQSHLQ_R_S "vqshl") (VQSHLQ_R_U "vqshl")
(VQSHLQ_S "vqshl") (VQSHLQ_U "vqshl")
(VQSUBQ_M_N_S "vqsub") (VQSUBQ_M_N_U "vqsub")
(VQSUBQ_M_S "vqsub") (VQSUBQ_M_U "vqsub")
(VRSHLQ_M_S "vrshl") (VRSHLQ_M_U "vrshl")
(VRSHLQ_N_S "vrshl") (VRSHLQ_N_U "vrshl")
(VRSHLQ_S "vrshl") (VRSHLQ_U "vrshl")
+ (VSHLQ_M_N_S "vshl") (VSHLQ_M_N_U "vshl")
+ (VSHLQ_M_R_S "vshl") (VSHLQ_M_R_U "vshl")
(VSHLQ_M_S "vshl") (VSHLQ_M_U "vshl")
+ (VSHLQ_N_S "vshl") (VSHLQ_N_U "vshl")
+ (VSHLQ_R_S "vshl") (VSHLQ_R_U "vshl")
+ (VSHLQ_S "vshl") (VSHLQ_U "vshl")
(VSUBQ_M_N_S "vsub") (VSUBQ_M_N_U "vsub") (VSUBQ_M_N_F "vsub")
(VSUBQ_M_S "vsub") (VSUBQ_M_U "vsub") (VSUBQ_M_F "vsub")
(VSUBQ_N_S "vsub") (VSUBQ_N_U "vsub") (VSUBQ_N_F "vsub")
])
;;
-;; [vqshlq_n_s, vqshlq_n_u])
+;; [vqshlq_n_s, vqshlq_n_u]
+;; [vshlq_n_u, vshlq_n_s]
;;
-(define_insn "mve_vqshlq_n_<supf><mode>"
+(define_insn "@mve_<mve_insn>q_n_<supf><mode>"
[
(set (match_operand:MVE_2 0 "s_register_operand" "=w")
(unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "w")
(match_operand:SI 2 "immediate_operand" "i")]
- VQSHLQ_N))
+ MVE_SHIFT_N))
]
"TARGET_HAVE_MVE"
- "vqshl.<supf>%#<V_sz_elem>\t%q0, %q1, %2"
+ "<mve_insn>.<supf>%#<V_sz_elem>\t%q0, %q1, %2"
[(set_attr "type" "mve_move")
])
;;
-;; [vqshlq_r_u, vqshlq_r_s])
+;; [vqshlq_r_u, vqshlq_r_s]
+;; [vshlq_r_s, vshlq_r_u]
;;
-(define_insn "mve_vqshlq_r_<supf><mode>"
+(define_insn "@mve_<mve_insn>q_r_<supf><mode>"
[
(set (match_operand:MVE_2 0 "s_register_operand" "=w")
(unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
(match_operand:SI 2 "s_register_operand" "r")]
- VQSHLQ_R))
+ MVE_SHIFT_R))
]
"TARGET_HAVE_MVE"
- "vqshl.<supf>%#<V_sz_elem>\t%q0, %2"
+ "<mve_insn>.<supf>%#<V_sz_elem>\t%q0, %2"
[(set_attr "type" "mve_move")
])
[(set_attr "type" "mve_move")
])
-;;
-;; [vshlq_n_u, vshlq_n_s])
-;;
-(define_insn "mve_vshlq_n_<supf><mode>"
- [
- (set (match_operand:MVE_2 0 "s_register_operand" "=w")
- (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "w")
- (match_operand:SI 2 "immediate_operand" "i")]
- VSHLQ_N))
- ]
- "TARGET_HAVE_MVE"
- "vshl.<supf>%#<V_sz_elem>\t%q0, %q1, %2"
- [(set_attr "type" "mve_move")
-])
-
-;;
-;; [vshlq_r_s, vshlq_r_u])
-;;
-(define_insn "mve_vshlq_r_<supf><mode>"
- [
- (set (match_operand:MVE_2 0 "s_register_operand" "=w")
- (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
- (match_operand:SI 2 "s_register_operand" "r")]
- VSHLQ_R))
- ]
- "TARGET_HAVE_MVE"
- "vshl.<supf>%#<V_sz_elem>\t%q0, %2"
- [(set_attr "type" "mve_move")
-])
-
;;
;; [vabdq_f])
;;
(set_attr "length""8")])
;;
-;; [vqshlq_m_r_u, vqshlq_m_r_s])
+;; [vqshlq_m_r_u, vqshlq_m_r_s]
+;; [vshlq_m_r_u, vshlq_m_r_s]
;;
-(define_insn "mve_vqshlq_m_r_<supf><mode>"
+(define_insn "@mve_<mve_insn>q_m_r_<supf><mode>"
[
(set (match_operand:MVE_2 0 "s_register_operand" "=w")
(unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
(match_operand:SI 2 "s_register_operand" "r")
(match_operand:<MVE_VPRED> 3 "vpr_register_operand" "Up")]
- VQSHLQ_M_R))
+ MVE_SHIFT_M_R))
]
"TARGET_HAVE_MVE"
- "vpst\;vqshlt.<supf>%#<V_sz_elem>\t%q0, %2"
+ "vpst\;<mve_insn>t.<supf>%#<V_sz_elem>\t%q0, %2"
[(set_attr "type" "mve_move")
(set_attr "length""8")])
[(set_attr "type" "mve_move")
(set_attr "length""8")])
-;;
-;; [vshlq_m_r_u, vshlq_m_r_s])
-;;
-(define_insn "mve_vshlq_m_r_<supf><mode>"
- [
- (set (match_operand:MVE_2 0 "s_register_operand" "=w")
- (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
- (match_operand:SI 2 "s_register_operand" "r")
- (match_operand:<MVE_VPRED> 3 "vpr_register_operand" "Up")]
- VSHLQ_M_R))
- ]
- "TARGET_HAVE_MVE"
- "vpst\;vshlt.<supf>%#<V_sz_elem>\t%q0, %2"
- [(set_attr "type" "mve_move")
- (set_attr "length""8")])
-
;;
;; [vsliq_n_u, vsliq_n_s])
;;
(set_attr "length""8")])
;;
-;; [vqshlq_m_n_s, vqshlq_m_n_u])
+;; [vqshlq_m_n_s, vqshlq_m_n_u]
+;; [vshlq_m_n_s, vshlq_m_n_u]
;;
-(define_insn "mve_vqshlq_m_n_<supf><mode>"
+(define_insn "@mve_<mve_insn>q_m_n_<supf><mode>"
[
(set (match_operand:MVE_2 0 "s_register_operand" "=w")
(unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
(match_operand:MVE_2 2 "s_register_operand" "w")
(match_operand:SI 3 "immediate_operand" "i")
(match_operand:<MVE_VPRED> 4 "vpr_register_operand" "Up")]
- VQSHLQ_M_N))
+ MVE_SHIFT_M_N))
]
"TARGET_HAVE_MVE"
- "vpst\;vqshlt.<supf>%#<V_sz_elem>\t%q0, %q2, %3"
+ "vpst\;<mve_insn>t.<supf>%#<V_sz_elem>\t%q0, %q2, %3"
[(set_attr "type" "mve_move")
(set_attr "length""8")])
[(set_attr "type" "mve_move")
(set_attr "length""8")])
-;;
-;; [vshlq_m_n_s, vshlq_m_n_u])
-;;
-(define_insn "mve_vshlq_m_n_<supf><mode>"
- [
- (set (match_operand:MVE_2 0 "s_register_operand" "=w")
- (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
- (match_operand:MVE_2 2 "s_register_operand" "w")
- (match_operand:SI 3 "immediate_operand" "i")
- (match_operand:<MVE_VPRED> 4 "vpr_register_operand" "Up")]
- VSHLQ_M_N))
- ]
- "TARGET_HAVE_MVE"
- "vpst\;vshlt.<supf>%#<V_sz_elem>\t%q0, %q2, %3"
- [(set_attr "type" "mve_move")
- (set_attr "length""8")])
-
;;
;; [vshrq_m_n_s, vshrq_m_n_u])
;;