Add register source to movddup so that IRA will allow register source
for *vec_dupv2di when SSE3 is enabled.
gcc/
PR target/87599
* config/i386/sse.md (*vec_dupv2di): Add register source to
movddup.
gcc/testsuite/
PR target/87599
* gcc.target/i386/pr87599.c: New test.
From-SVN: r265151
+2018-10-14 H.J. Lu <hongjiu.lu@intel.com>
+
+ PR target/87599
+ * config/i386/sse.md (*vec_dupv2di): Add register source to
+ movddup.
+
2018-10-14 H.J. Lu <hongjiu.lu@intel.com>
PR target/87572
(define_insn "*vec_dupv2di"
[(set (match_operand:V2DI 0 "register_operand" "=x,v,v,x")
(vec_duplicate:V2DI
- (match_operand:DI 1 "nonimmediate_operand" " 0,Yv,m,0")))]
+ (match_operand:DI 1 "nonimmediate_operand" " 0,Yv,vm,0")))]
"TARGET_SSE"
"@
punpcklqdq\t%0, %0
+2018-10-14 H.J. Lu <hongjiu.lu@intel.com>
+
+ PR target/87599
+ * gcc.target/i386/pr87599.c: New test.
+
2018-10-14 H.J. Lu <hongjiu.lu@intel.com>
PR target/87572
--- /dev/null
+/* { dg-do compile { target { ! ia32 } } } */
+/* { dg-options "-march=corei7 -O2" } */
+/* { dg-final { scan-assembler-times "punpcklqdq\[ \\t\]+%xmm\[0-9\]+,\[ \\t\]+%xmm\[0-9\]+" 1 } } */
+
+#include <immintrin.h>
+
+__m128i
+foo (long long val)
+{
+ __m128i rval = {val, val};
+ return rval;
+}