{
unsigned int size = get_frame_size ();
- /* For simplicity, we just movm all the callee saved registers to
- the stack with one instruction, then set up the frame pointer
- (if needed), and finally allocate the new stack. */
- emit_insn (gen_store_movm ());
-
+ /* And now store all the registers onto the stack with a
+ single two byte instruction. */
+ if (regs_ever_live[2] || regs_ever_live[3]
+ || regs_ever_live[6] || regs_ever_live[7]
+ || frame_pointer_needed)
+ emit_insn (gen_store_movm ());
+
+ /* Now put the frame pointer into the frame pointer register. */
if (frame_pointer_needed)
emit_move_insn (frame_pointer_rtx, stack_pointer_rtx);
+ /* Allocate stack for this frame. */
if (size)
emit_insn (gen_addsi3 (stack_pointer_rtx,
stack_pointer_rtx,
size = 0;
}
- /* Deallocate remaining stack, restore registers and return. And return. */
- emit_jump_insn (gen_return_internal (GEN_INT (size)));
+ /* For simplicity, we just movm all the callee saved registers to
+ the stack with one instruction.
+
+ ?!? Only save registers which are actually used. Reduces
+ stack requireents and is faster. */
+ if (regs_ever_live[2] || regs_ever_live[3]
+ || regs_ever_live[6] || regs_ever_live[7]
+ || frame_pointer_needed)
+ emit_jump_insn (gen_return_internal_regs (GEN_INT (size)));
+ else
+ {
+ if (size)
+ emit_insn (gen_addsi3 (stack_pointer_rtx,
+ stack_pointer_rtx,
+ GEN_INT (size)));
+ emit_jump_insn (gen_return_internal ());
+ }
}
/* Update the condition code from the insn. */
V is always set to 0. C may or may not be set to 0 but that's ok
because alter_cond will change tests to use EQ/NE. */
CC_STATUS_INIT;
- cc_status.flags |= CC_NO_OVERFLOW;
+ cc_status.flags |= CC_NO_OVERFLOW | CC_OVERFLOW_UNUSABLE;
cc_status.value1 = recog_operand[0];
break;
- case CC_SET:
+ case CC_TST:
/* The insn sets all the condition codes, except v is bogus. */
CC_STATUS_INIT;
- cc_status.flags |= CC_OVERFLOW_UNUSABLE;
cc_status.value1 = recog_operand[0];
break;
/* We can't directly load sp + const_int into a data register;
we must use an address register as an intermediate. */
- if (class == DATA_REGS
+ if (class != SP_REGS
+ && class != ADDRESS_REGS
+ && class != SP_OR_ADDRESS_REGS
&& (in == stack_pointer_rtx
|| (GET_CODE (in) == PLUS
- && XEXP (in, 0) == stack_pointer_rtx)))
+ && (XEXP (in, 0) == stack_pointer_rtx
+ || XEXP (in, 1) == stack_pointer_rtx))))
return ADDRESS_REGS;
- /* Get the true register. */
- if (GET_CODE (in) == REG)
+ /* Otherwise assume no secondary reloads are needed. */
+ return NO_REGS;
+}
+
+int
+initial_offset (from, to)
+ int from, to;
+{
+ if (from == ARG_POINTER_REGNUM && to == FRAME_POINTER_REGNUM)
{
- regno = REGNO (in);
- if (regno >= FIRST_PSEUDO_REGISTER)
- regno = true_regnum (in);
+ if (regs_ever_live[2] || regs_ever_live[3]
+ || regs_ever_live[6] || regs_ever_live[7]
+ || frame_pointer_needed)
+ return 20;
+ else
+ return 4;
}
- /* We can't copy directly from a data register into the stack
- pointer. */
- if (class == SP_REGS
- && GET_CODE (in) == REG
- && regno < 4)
- return ADDRESS_REGS;
+ if (from == ARG_POINTER_REGNUM && to == STACK_POINTER_REGNUM)
+ {
+ if (regs_ever_live[2] || regs_ever_live[3]
+ || regs_ever_live[6] || regs_ever_live[7]
+ || frame_pointer_needed)
+ return get_frame_size () + 20;
+ else
+ return get_frame_size () + 4;
+ }
- /* Otherwise assume no secondary reloads are needed. */
- return NO_REGS;
+ if (from == FRAME_POINTER_REGNUM && to == STACK_POINTER_REGNUM)
+ return get_frame_size ();
+
+ abort ();
}
All registers that the compiler knows about must be given numbers,
even those that are not normally considered general registers. */
-#define FIRST_PSEUDO_REGISTER 9
+#define FIRST_PSEUDO_REGISTER 10
/* 1 for registers that have pervasive standard uses
and are not available for the register allocator. */
#define FIXED_REGISTERS \
- { 0, 0, 0, 0, 0, 0, 0, 0, 1}
+ { 0, 0, 0, 0, 0, 0, 0, 0, 1, 1}
/* 1 for registers not available across function calls.
These must include the FIXED_REGISTERS and also any
like. */
#define CALL_USED_REGISTERS \
- { 1, 1, 0, 0, 1, 1, 0, 0, 1}
+ { 1, 1, 0, 0, 1, 1, 0, 0, 1, 1}
#define REG_ALLOC_ORDER \
- { 0, 1, 4, 5, 2, 3, 6, 7, 8}
+ { 0, 1, 4, 5, 2, 3, 6, 7, 8, 9}
/* Return number of consecutive hard regs needed starting at reg REGNO
to hold something of mode MODE.
class that represents their union. */
enum reg_class {
- NO_REGS, DATA_REGS, ADDRESS_REGS, SP_REGS, DATA_OR_ADDRESS_REGS, DATA_OR_SP_REGS, SP_OR_ADDRESS_REGS, GENERAL_REGS, ALL_REGS, LIM_REG_CLASSES
+ NO_REGS, DATA_REGS, ADDRESS_REGS, SP_REGS, DATA_OR_ADDRESS_REGS, SP_OR_ADDRESS_REGS, GENERAL_REGS, ALL_REGS, LIM_REG_CLASSES
};
#define N_REG_CLASSES (int) LIM_REG_CLASSES
#define REG_CLASS_NAMES \
{ "NO_REGS", "DATA_REGS", "ADDRESS_REGS", \
- "SP_REGS", "DATA_OR_ADDRESS_REGS", "DATA_OR_SP_REGS", \
- "SP_OR_ADDRESS_REGS", "GENERAL_REGS", "ALL_REGS", "LIM_REGS" }
+ "SP_REGS", "DATA_OR_ADDRESS_REGS", "SP_OR_ADDRESS_REGS", \
+ "GENERAL_REGS", "ALL_REGS", "LIM_REGS" }
/* Define which registers fit in which classes.
This is an initializer for a vector of HARD_REG_SET
#define REG_CLASS_CONTENTS \
{ 0, /* No regs */ \
0x00f, /* DATA_REGS */ \
- 0x0f0, /* ADDRESS_REGS */ \
- 0x100, /* SP_REGS */ \
- 0x0ff, /* DATA_OR_ADDRESS_REGS */\
- 0x00f, /* DATA_OR_SP_REGS */ \
- 0x0f0, /* SP_OR_ADDRESS_REGS */\
- 0x0ff, /* GENERAL_REGS */ \
- 0x0ff, /* ALL_REGS */ \
+ 0x1f0, /* ADDRESS_REGS */ \
+ 0x200, /* SP_REGS */ \
+ 0x1ff, /* DATA_OR_ADDRESS_REGS */\
+ 0x1f0, /* SP_OR_ADDRESS_REGS */\
+ 0x1ff, /* GENERAL_REGS */ \
+ 0x3ff, /* ALL_REGS */ \
}
/* The same information, inverted:
#define REGNO_REG_CLASS(REGNO) \
((REGNO) < 4 ? DATA_REGS : \
- (REGNO) < 8 ? ADDRESS_REGS : \
- (REGNO) == 8 ? SP_REGS: 0)
+ (REGNO) < 9 ? ADDRESS_REGS : \
+ (REGNO) == 9 ? SP_REGS: 0)
/* The class value for index registers, and the one for base regs. */
#define PREFERRED_RELOAD_CLASS(X,CLASS) \
(X == stack_pointer_rtx && CLASS != SP_REGS ? ADDRESS_REGS : CLASS)
+#define PREFERRED_OUTPUT_RELOAD_CLASS(X,CLASS) \
+ (X == stack_pointer_rtx && CLASS != SP_REGS ? ADDRESS_REGS : CLASS)
+
#define LIMIT_RELOAD_CLASS(MODE, CLASS) \
((MODE == QImode || MODE == HImode) ? DATA_REGS : CLASS)
#define CONST_OK_FOR_J(VALUE) ((VALUE) == 1)
#define CONST_OK_FOR_K(VALUE) ((VALUE) == 2)
#define CONST_OK_FOR_L(VALUE) ((VALUE) == 4)
+#define CONST_OK_FOR_M(VALUE) ((VALUE) == 3)
#define CONST_OK_FOR_LETTER_P(VALUE, C) \
((C) == 'I' ? CONST_OK_FOR_I (VALUE) : \
(C) == 'J' ? CONST_OK_FOR_J (VALUE) : \
(C) == 'K' ? CONST_OK_FOR_K (VALUE) : \
- (C) == 'L' ? CONST_OK_FOR_L (VALUE) : 0)
+ (C) == 'L' ? CONST_OK_FOR_L (VALUE) : \
+ (C) == 'M' ? CONST_OK_FOR_M (VALUE) : 0)
/* Similar, but for floating constants, and defining letters G and H.
/* Is equal to the size of the saved fp + pc, even if an fp isn't
saved since the value is used before we know. */
-#define FIRST_PARM_OFFSET(FNDECL) (-4 + 20)
+#define FIRST_PARM_OFFSET(FNDECL) -4
/* Specify the registers used for certain standard purposes.
The values of these macros are register numbers. */
/* Register to use for pushing function arguments. */
-#define STACK_POINTER_REGNUM 8
+#define STACK_POINTER_REGNUM 9
/* Base register for access to local variables of the function. */
#define FRAME_POINTER_REGNUM 7
-/* Base register for access to arguments of the function. */
-#define ARG_POINTER_REGNUM 7
+/* Base register for access to arguments of the function. This
+ is a fake register and will be eliminated into either the frame
+ pointer or stack pointer. */
+#define ARG_POINTER_REGNUM 8
/* Register in which static-chain is passed to a function. */
#define STATIC_CHAIN_REGNUM 5
/* Value should be nonzero if functions must have frame pointers.
Zero means the frame pointer need not be set up (and parms
may be accessed via the stack pointer) in functions that seem suitable.
- This is computed in `reload', in reload1.c.
+ This is computed in `reload', in reload1.c.
+
+ We allow frame pointers to be eliminated when not having one will
+ not interfere with debugging.
+
+ * If this is a leaf function, then we can keep the stack pointer
+ constant throughout the function, and therefore gdb can easily
+ find the base of the current frame.
+
+ * If this function never allocates stack space for outgoing
+ args (ie calls functions with either no args, or args only
+ in registers), then the stack pointer will be constant and
+ gdb can easily find the base of the current frame.
+
+ We'd really like to define ACCUMULATE_OUTGOING_ARGS and eliminate
+ all frame pointer, but currently we can't.
+
+ We probably also want a -m option to eliminate frame pointer, even
+ if the resulting executable can not be debugged. */
+
+#define ELIMINABLE_REGS \
+{{ ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
+ { ARG_POINTER_REGNUM, FRAME_POINTER_REGNUM}, \
+ { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}}
+
+#define CAN_ELIMINATE(FROM, TO) 1
- Currently we always need a frame pointer. In the future we'd like
- to be able to eliminate it. */
-#define FRAME_POINTER_REQUIRED 1
+#define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
+ OFFSET = initial_offset (FROM, TO)
-/* Store in the variable DEPTH the initial difference between the
- frame pointer reg contents and the stack pointer reg contents,
- as of the start of the function body. This depends on the layout
- of the fixed parts of the stack frame and on how registers are saved. */
+#define FRAME_POINTER_REQUIRED \
+ !(leaf_function_p () || current_function_outgoing_args_size == 0)
-#define INITIAL_FRAME_POINTER_OFFSET(DEPTH) (DEPTH) = 20
+#define CAN_DEBUG_WITHOUT_FP
/* A guess for the MN10300. */
#define PROMOTE_PROTOTYPES 1
/* Nonzero if X is a hard reg that can be used as a base reg
or if it is a pseudo reg. */
#define REG_OK_FOR_BASE_P(X) \
- ((REGNO (X) >= 4 && REGNO(X) <= 8) || REGNO (X) >= FIRST_PSEUDO_REGISTER)
+ ((REGNO (X) >= 4 && REGNO(X) <= 9) || REGNO (X) >= FIRST_PSEUDO_REGISTER)
#else
/* Nonzero if X is a hard reg that can be used as an index. */
#define REG_OK_FOR_INDEX_P(X) REGNO_OK_FOR_INDEX_P (REGNO (X))
{ \
if (GET_CODE (index) == CONST_INT) \
goto ADDR; \
- if (GET_CODE (index) == REG \
+ if (REG_P (index) \
&& REG_OK_FOR_INDEX_P (index)) \
goto ADDR; \
} \
default: { int _zxy= const_costs(RTX, CODE); \
if(_zxy) return _zxy; break;}
-#define REGISTER_MOVE_COST(CLASS1, CLASS2) 3
+#define REGISTER_MOVE_COST(CLASS1, CLASS2) (CLASS1 != CLASS2 ? 4 : 0)
/* A crude cut at RTX_COSTS for the MN10300. */
This sequence is indexed by compiler's hard-register-number (see above). */
#define REGISTER_NAMES \
-{ "d0", "d1", "d2", "d3", "a0", "a1", "a2", "a3", "sp" }
+{ "d0", "d1", "d2", "d3", "a0", "a1", "a2", "a3", "ap", "sp" }
/* Print an instruction operand X on file FILE.
look in mn10300.c for details */
extern void notice_update_cc ();
extern int call_address_operand ();
extern enum reg_class secondary_reload_class ();
+extern int initial_offset ();
;; be known (if it isn't that's ok, we don't need it anyway).
;; compare - compare instruction
;; clobber - value of cc is unknown
-(define_attr "cc" "none,none_0hit,set,set_zn_c0,compare,clobber"
+(define_attr "cc" "none,none_0hit,tst,set_zn_c0,compare,clobber"
(const_string "clobber"))
\f
;; ----------------------------------------------------------------------
[(set (cc0) (match_operand:SI 0 "register_operand" "da"))]
""
"cmp 0,%0"
- [(set_attr "cc" "set_zn_c0")])
+ [(set_attr "cc" "tst")])
(define_insn "cmpsi"
[(set (cc0)
(compare:SI (match_operand:SI 0 "register_operand" "da")
- (match_operand:SI 1 "nonmemory_operand" "dai")))]
+ (match_operand:SI 1 "register_operand" "dai")))]
""
"cmp %1,%0"
[(set_attr "cc" "compare")])
inc4 %0
add %2,%0
add %2,%0"
- [(set_attr "cc" "set,none_0hit,none_0hit,set,none_0hit")])
+ [(set_attr "cc" "set_zn_c0,none_0hit,none_0hit,set_zn_c0,none_0hit")])
;; ----------------------------------------------------------------------
;; SUBTRACT INSTRUCTIONS
(match_operand:SI 2 "register_operand" "dai")))]
""
"sub %2,%0"
- [(set_attr "cc" "set")])
+ [(set_attr "cc" "set_zn_c0")])
(define_expand "negsi2"
[(set (match_operand:SI 0 "register_operand" "")
;; EXTEND INSTRUCTIONS
;; ----------------------------------------------------------------------
-(define_insn "zero_extendhisi2"
- [(set (match_operand:SI 0 "register_operand" "=d")
+(define_insn "zero_extendqisi2"
+ [(set (match_operand:SI 0 "general_operand" "=d,d,d")
(zero_extend:SI
- (match_operand:HI 1 "register_operand" "0")))]
+ (match_operand:QI 1 "general_operand" "0,d,m")))]
""
- "exthu %0"
+ "@
+ extbu %0
+ mov %1,%0\;extbu %0
+ movbu %1,%0"
[(set_attr "cc" "none_0hit")])
-(define_insn "zero_extendqisi2"
- [(set (match_operand:SI 0 "register_operand" "=d")
+(define_insn "zero_extendhisi2"
+ [(set (match_operand:SI 0 "general_operand" "=d,d,d")
(zero_extend:SI
- (match_operand:QI 1 "register_operand" "0")))]
+ (match_operand:HI 1 "general_operand" "0,d,m")))]
""
- "extbu %0"
+ "@
+ exthu %0
+ mov %1,%0\;exthu %0
+ movhu %1,%0"
[(set_attr "cc" "none_0hit")])
;;- sign extension instructions
-(define_insn "extendhisi2"
- [(set (match_operand:SI 0 "register_operand" "=d")
+(define_insn "extendqisi2"
+ [(set (match_operand:SI 0 "general_operand" "=d,d")
(sign_extend:SI
- (match_operand:HI 1 "register_operand" "0")))]
+ (match_operand:QI 1 "general_operand" "0,d")))]
""
- "exth %0"
+ "@
+ extb %0
+ mov %1,%0"
[(set_attr "cc" "none_0hit")])
-(define_insn "extendqisi2"
- [(set (match_operand:SI 0 "register_operand" "=d")
+(define_insn "extendhisi2"
+ [(set (match_operand:SI 0 "general_operand" "=d,d")
(sign_extend:SI
- (match_operand:QI 1 "register_operand" "0")))]
+ (match_operand:HI 1 "general_operand" "0,d")))]
""
- "extb %0"
+ "@
+ exth %0
+ mov %1,%0"
[(set_attr "cc" "none_0hit")])
\f
;; ----------------------------------------------------------------------
(define_insn "ashlsi3"
- [(set (match_operand:SI 0 "register_operand" "=d,d")
+ [(set (match_operand:SI 0 "register_operand" "=da,d,a,d,a,d,a,d")
(ashift:SI
- (match_operand:SI 1 "register_operand" "0,0")
- (match_operand:QI 2 "nonmemory_operand" "K,di")))]
+ (match_operand:SI 1 "register_operand" "0,0,0,0,0,0,0,0")
+ (match_operand:QI 2 "nonmemory_operand" "J,K,K,M,M,L,L,di")))]
""
"@
+ add %0,%0
asl2 %0
+ add %0,%0\;add %0,%0
+ asl2 %0\;add %0,%0
+ add %0,%0\;add %0,%0\;add %0,%0
+ asl2 %0\;asl2 %0
+ add %0,%0\;add %0,%0\;add %0,%0\;add %0,%0
asl %2,%0"
[(set_attr "cc" "set_zn_c0")])
DONE;
}")
-(define_insn "return"
- [(return)]
- "0"
+(define_insn "return_internal"
+ [(const_int 2)]
+ ""
"rets"
[(set_attr "cc" "clobber")])
;; This insn restores the callee saved registers and does a return, it
;; can also deallocate stack space.
-(define_insn "return_internal"
+(define_insn "return_internal_regs"
[(const_int 0)
(match_operand:SI 0 "const_int_operand" "i")
(return)]
""
"movm [d2,d3,a2,a3],(sp)"
[(set_attr "cc" "clobber")])
+
+;; Try to combine consecutive updates of the stack pointer (or any
+;; other register for that matter).
+(define_peephole
+ [(set (match_operand:SI 0 "register_operand" "=dax")
+ (plus:SI (match_dup 0)
+ (match_operand 1 "const_int_operand" "")))
+ (set (match_dup 0)
+ (plus:SI (match_dup 0)
+ (match_operand 2 "const_int_operand" "")))]
+ ""
+ "*
+{
+ operands[1] = GEN_INT (INTVAL (operands[2]) + INTVAL (operands[1]));
+ return \"add %1,%0\";
+}"
+ [(set_attr "cc" "clobber")])
git://gcc.gnu.org / gcc.git / commitdiff