#define HAVE_SQRT_P() (mips_isa != 1)
/* ISA has instructions for managing 64 bit fp and gp regs (eg. mips3). */
-#define ISA_HAS_64BIT_REGS (mips_isa == 3 || mips_isa == 4 || mips_isa == 64)
+#define ISA_HAS_64BIT_REGS (mips_isa == 3 || mips_isa == 4 \
+ )
/* ISA has branch likely instructions (eg. mips2). */
#define ISA_HAS_BRANCHLIKELY (mips_isa != 1)
-/* ISA has the FP instructions introduced in mips4. */
-#define ISA_HAS_FP4 (mips_isa == 4)
+/* ISA has the conditional move instructions introduced in mips4. */
+#define ISA_HAS_CONDMOVE (mips_isa == 4 \
+ )
+
+/* ISA has the mips4 FP condition code instructions: FP-compare to CC,
+ branch on CC, and move (both FP and non-FP) on CC. */
+#define ISA_HAS_8CC (mips_isa == 4 \
+ )
+
+
+/* This is a catch all for the other new mips4 instructions: indexed load and
+ indexed prefetch instructions, the FP madd,msub,nmadd, and nmsub instructions,
+ and the FP recip and recip sqrt instructions */
+#define ISA_HAS_FP4 (mips_isa == 4 \
+ )
+
-/* ISA has the non-FP conditional move instructions introduced in mips4. */
-#define ISA_HAS_CONDMOVE (mips_isa == 4)
/* CC1_SPEC causes -mips3 and -mips4 to set -mfp64 and -mgp64; -mips1 or
-mips2 sets -mfp32 and -mgp32. This can be overridden by an explicit
for (regno = ST_REG_FIRST; regno <= ST_REG_LAST; regno++) \
fixed_regs[regno] = call_used_regs[regno] = 1; \
} \
- else if (! ISA_HAS_FP4) \
+ else if (! ISA_HAS_8CC) \
{ \
int regno; \
\
(define_insn "movcc"
[(set (match_operand:CC 0 "nonimmediate_operand" "=d,*d,*d,*d,*R,*m,*d,*f,*f,*f,*f,*R,*m")
(match_operand:CC 1 "general_operand" "z,*d,*R,*m,*d,*d,*f,*d,*f,*R,*m,*f,*f"))]
- "ISA_HAS_FP4 && TARGET_HARD_FLOAT"
+ "ISA_HAS_8CC && TARGET_HARD_FLOAT"
"* return mips_move_1word (operands, insn, FALSE);"
[(set_attr "type" "move,move,load,load,store,store,xfer,xfer,move,load,load,store,store")
(set_attr "mode" "SI")
[(set (match_operand:CC 0 "register_operand" "=z")
(match_operand:CC 1 "general_operand" "z"))
(clobber (match_operand:TF 2 "register_operand" "=&f"))]
- "ISA_HAS_FP4 && TARGET_HARD_FLOAT"
+ "ISA_HAS_8CC && TARGET_HARD_FLOAT"
"
{
rtx source;
[(set (match_operand:CC 0 "general_operand" "=z")
(match_operand:CC 1 "register_operand" "z"))
(clobber (match_operand:CC 2 "register_operand" "=&d"))]
- "ISA_HAS_FP4 && TARGET_HARD_FLOAT"
+ "ISA_HAS_8CC && TARGET_HARD_FLOAT"
"
{
/* This is called when we are copying a condition code register out
(const_int 0)])
(match_operand:SI 1 "reg_or_0_operand" "dJ,0")
(match_operand:SI 2 "reg_or_0_operand" "0,dJ")))]
- "ISA_HAS_FP4 && TARGET_HARD_FLOAT"
+ "ISA_HAS_CONDMOVE && TARGET_HARD_FLOAT"
"@
mov%T3\\t%0,%z1,%4
mov%t3\\t%0,%z2,%4"
(const_int 0)])
(match_operand:DI 1 "se_reg_or_0_operand" "dJ,0")
(match_operand:DI 2 "se_reg_or_0_operand" "0,dJ")))]
- "ISA_HAS_FP4 && TARGET_HARD_FLOAT"
+ "ISA_HAS_CONDMOVE && TARGET_HARD_FLOAT"
"@
mov%T3\\t%0,%z1,%4
mov%t3\\t%0,%z2,%4"
(const_int 0)])
(match_operand:SF 2 "register_operand" "f,0")
(match_operand:SF 3 "register_operand" "0,f")))]
- "ISA_HAS_FP4 && TARGET_HARD_FLOAT"
+ "ISA_HAS_CONDMOVE && TARGET_HARD_FLOAT"
"@
mov%B4.s\\t%0,%2,%1
mov%b4.s\\t%0,%3,%1"
(const_int 0)])
(match_operand:SF 2 "register_operand" "f,0")
(match_operand:SF 3 "register_operand" "0,f")))]
- "ISA_HAS_FP4 && TARGET_HARD_FLOAT"
+ "ISA_HAS_CONDMOVE && TARGET_HARD_FLOAT"
"@
mov%B4.s\\t%0,%2,%1
mov%b4.s\\t%0,%3,%1"
(const_int 0)])
(match_operand:SF 1 "register_operand" "f,0")
(match_operand:SF 2 "register_operand" "0,f")))]
- "ISA_HAS_FP4 && TARGET_HARD_FLOAT"
+ "ISA_HAS_CONDMOVE && TARGET_HARD_FLOAT"
"@
mov%T3.s\\t%0,%1,%4
mov%t3.s\\t%0,%2,%4"
(const_int 0)])
(match_operand:DF 2 "register_operand" "f,0")
(match_operand:DF 3 "register_operand" "0,f")))]
- "ISA_HAS_FP4 && TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
+ "ISA_HAS_CONDMOVE && TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
"@
mov%B4.d\\t%0,%2,%1
mov%b4.d\\t%0,%3,%1"
(const_int 0)])
(match_operand:DF 2 "register_operand" "f,0")
(match_operand:DF 3 "register_operand" "0,f")))]
- "ISA_HAS_FP4 && TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
+ "ISA_HAS_CONDMOVE && TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
"@
mov%B4.d\\t%0,%2,%1
mov%b4.d\\t%0,%3,%1"
(const_int 0)])
(match_operand:DF 1 "register_operand" "f,0")
(match_operand:DF 2 "register_operand" "0,f")))]
- "ISA_HAS_FP4 && TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
+ "ISA_HAS_CONDMOVE && TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
"@
mov%T3.d\\t%0,%1,%4
mov%t3.d\\t%0,%2,%4"
(if_then_else:SI (match_dup 5)
(match_operand:SI 2 "reg_or_0_operand" "")
(match_operand:SI 3 "reg_or_0_operand" "")))]
- "ISA_HAS_CONDMOVE || ISA_HAS_FP4"
+ "ISA_HAS_CONDMOVE"
"
{
gen_conditional_move (operands);
(if_then_else:DI (match_dup 5)
(match_operand:DI 2 "se_reg_or_0_operand" "")
(match_operand:DI 3 "se_reg_or_0_operand" "")))]
- "ISA_HAS_CONDMOVE || ISA_HAS_FP4"
+ "ISA_HAS_CONDMOVE"
"
{
gen_conditional_move (operands);
(if_then_else:SF (match_dup 5)
(match_operand:SF 2 "register_operand" "")
(match_operand:SF 3 "register_operand" "")))]
- "ISA_HAS_FP4 && TARGET_HARD_FLOAT"
+ "ISA_HAS_CONDMOVE && TARGET_HARD_FLOAT"
"
{
gen_conditional_move (operands);
(if_then_else:DF (match_dup 5)
(match_operand:DF 2 "register_operand" "")
(match_operand:DF 3 "register_operand" "")))]
- "ISA_HAS_FP4 && TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
+ "ISA_HAS_CONDMOVE && TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
"
{
gen_conditional_move (operands);