#define TARGET_RNG (AARCH64_ISA_RNG)
/* Memory Tagging instructions optional to Armv8.5 enabled through +memtag. */
-#define TARGET_MEMTAG (AARCH64_ISA_V8_5A && AARCH64_ISA_MEMTAG)
+#define TARGET_MEMTAG (AARCH64_ISA_MEMTAG)
/* I8MM instructions are enabled through +i8mm. */
#define TARGET_I8MM (AARCH64_ISA_I8MM)
#pragma GCC pop_options
#pragma GCC push_options
-#pragma GCC target ("arch=armv8.5-a+memtag")
+#pragma GCC target ("+nothing+memtag")
#define __arm_mte_create_random_tag(__ptr, __u64_mask) \
__builtin_aarch64_memtag_irg(__ptr, __u64_mask)
#include <stdint.h>
#pragma GCC push_options
-#pragma GCC target ("arch=armv8.2-a+fp16")
+#pragma GCC target ("+nothing+fp16")
typedef __fp16 float16_t;
#include "arm_fp16.h"
#pragma GCC push_options
-#pragma GCC target ("arch=armv8.2-a+fp16")
+#pragma GCC target ("+nothing+simd+fp16")
/* ARMv8.2-A FP16 one operand vector intrinsics. */
/* AdvSIMD Dot Product intrinsics. */
#pragma GCC push_options
-#pragma GCC target ("arch=armv8.2-a+dotprod")
+#pragma GCC target ("+nothing+dotprod")
__extension__ extern __inline uint32x2_t
__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
#pragma GCC pop_options
#pragma GCC push_options
-#pragma GCC target ("arch=armv8.2-a+sm4")
+#pragma GCC target ("+nothing+sm4")
__extension__ extern __inline uint32x4_t
__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
#pragma GCC pop_options
#pragma GCC push_options
-#pragma GCC target ("arch=armv8.2-a+sha3")
+#pragma GCC target ("+nothing+sha3")
__extension__ extern __inline uint64x2_t
__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
#pragma GCC pop_options
#pragma GCC push_options
-#pragma GCC target ("arch=armv8.2-a+fp16fml")
+#pragma GCC target ("+nothing+fp16fml")
__extension__ extern __inline float32x2_t
__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
#include "arm_bf16.h"
#pragma GCC push_options
-#pragma GCC target ("arch=armv8.2-a+bf16")
+#pragma GCC target ("+nothing+bf16")
__extension__ extern __inline bfloat16x4_t
__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
/* AdvSIMD 8-bit Integer Matrix Multiply (I8MM) intrinsics. */
#pragma GCC push_options
-#pragma GCC target ("arch=armv8.2-a+i8mm")
+#pragma GCC target ("+nothing+i8mm")
__extension__ extern __inline int32x2_t
__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
--- /dev/null
+/* { dg-do compile } */
+/* { dg-additional-options "-march=armv8-a+bf16" } */
+
+#include <arm_neon.h>
+
+float32x4_t bar (float32x4_t r, bfloat16x8_t a, bfloat16x8_t b) {
+ return vbfmlalbq_f32 (r, a, b);
+}
+
+/* { dg-final { scan-assembler {\tbfmlalb\t} } } */
--- /dev/null
+/* { dg-do compile } */
+/* { dg-additional-options "-march=armv8-a+dotprod" } */
+
+#include <arm_neon.h>
+
+uint32x4_t bar (uint32x4_t r, uint8x16_t a, uint8x16_t b) {
+ return vdotq_u32(r, a, b);
+}
+
+/* { dg-final { scan-assembler {\tudot\t} } } */
--- /dev/null
+/* { dg-do compile } */
+/* { dg-additional-options "-march=armv8-a+fp16" } */
+
+#include <arm_neon.h>
+
+float16x8_t bar (float16x8_t a, float16x8_t b) {
+ return vaddq_f16(a, b);
+}
+
+/* { dg-final { scan-assembler {\tfadd\t} } } */
--- /dev/null
+/* { dg-do compile } */
+/* { dg-additional-options "-march=armv8-a+fp16+nosimd" } */
+
+#include <arm_fp16.h>
+
+float16_t bar (float16_t a, float16_t b) {
+ return vaddh_f16(a, b);
+}
+
+/* { dg-final { scan-assembler {\tfadd\t} } } */
--- /dev/null
+/* { dg-do compile } */
+/* { dg-additional-options "-march=armv8-a+fp16fml" } */
+
+#include <arm_neon.h>
+
+float32x4_t bar (float32x4_t r, float16x8_t a, float16x8_t b) {
+ return vfmlalq_high_f16 (r, a, b);
+}
+
+/* { dg-final { scan-assembler {\tfmlal2\t} } } */
--- /dev/null
+/* { dg-do compile } */
+/* { dg-additional-options "-march=armv8-a+i8mm" } */
+
+#include <arm_neon.h>
+
+int32x4_t bar (int32x4_t r, int8x16_t a, int8x16_t b) {
+ return vmmlaq_s32 (r, a, b);
+}
+
+/* { dg-final { scan-assembler {\tsmmla\t} } } */
--- /dev/null
+/* { dg-do compile } */
+/* { dg-additional-options "-march=armv8-a+memtag" } */
+
+#include <arm_acle.h>
+
+int *bar (int *src) {
+ return __arm_mte_create_random_tag(src, 2<<16-1);
+}
+
+/* { dg-final { scan-assembler {\tirg\t} } } */
--- /dev/null
+/* { dg-do compile } */
+/* { dg-additional-options "-march=armv8-a+sha3" } */
+
+#include <arm_neon.h>
+
+uint64x2_t bar (uint64x2_t a, uint64x2_t b, uint64x2_t c) {
+ return vsha512hq_u64(a, b, c);
+}
+
+/* { dg-final { scan-assembler {\tsha512h\t} } } */
--- /dev/null
+/* { dg-do compile } */
+/* { dg-additional-options "-march=armv8-a+sm4" } */
+
+#include <arm_neon.h>
+
+uint32x4_t bar (uint32x4_t a, uint32x4_t b, uint32x4_t c) {
+ return vsm3tt1aq_u32(a, b, c, 2);
+}
+
+/* { dg-final { scan-assembler {\tsm3tt1a\t} } } */