sh.md (*prefetch_i4, [...]): Merge into ...

	* config/sh/sh.md (*prefetch_i4, prefetch_m2a): Merge into ...
	(*prefetch): ... this new insn.

	* gcc.target/sh/sh2a-prefetch.c: Rename to ...
	* gcc.target/sh/prefetch.c: ... this.  Enable test case for m4*.

From-SVN: r186225

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 6ce0a71088826b547571be861b6a85a37e55f930..ed9130e84766de708159df6968eca0430de86ed2 100644 (file)
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,8 @@
+2012-04-08  Oleg Endo  <olegendo@gcc.gnu.org>
+
+       * config/sh/sh.md (*prefetch_i4, prefetch_m2a): Merge into ...
+       (*prefetch): ... this new insn.
+
 2012-04-07  Oleg Endo  <olegendo@gcc.gnu.org>
 
        * config/sh/sh.h (high_life_started): Remove

diff --git a/gcc/config/sh/sh.md b/gcc/config/sh/sh.md
index c0456319b50d03d09db489a5ff4a936ae04b5429..0fe9fca2bed45ede036bb72ab7771f3117dfa01e 100644 (file)
--- a/gcc/config/sh/sh.md
+++ b/gcc/config/sh/sh.md
@@ -909,8 +909,10 @@
                       (match_operand:DI 1 "arith_operand" "r"))
               (const_int 0)))]
   "TARGET_SH1"
-  "* return output_branchy_insn (EQ, \"tst\\t%S1,%S0\;bf\\t%l9\;tst\\t%R1,%R0\",
-                                insn, operands);"
+{
+  return output_branchy_insn (EQ, "tst\t%S1,%S0;bf\t%l9;tst\t%R1,%R0",
+                             insn, operands);
+}
   [(set_attr "length" "6")
    (set_attr "type" "arith3b")])
 
@@ -3156,7 +3158,6 @@ label:
        (and:SI (match_operand:SI 1 "logical_reg_operand" "")
                (match_operand:SI 2 "logical_operand" "")))]
   ""
-  "
 {
   if (TARGET_SH1
       && CONST_INT_P (operands[2]) && INTVAL (operands[2]) == 255)
@@ -3165,7 +3166,7 @@ label:
                                       gen_lowpart (QImode, operands[1])));
       DONE;
     }
-}")
+})
 
 (define_insn_and_split "anddi3"
   [(set (match_operand:DI 0 "arith_reg_dest" "=r,r,r")
@@ -3179,14 +3180,13 @@ label:
   "reload_completed
    && ! logical_operand (operands[2], DImode)"
   [(const_int 0)]
-  "
 {
   if ((unsigned)INTVAL (operands[2]) == (unsigned) 0xffffffff)
     emit_insn (gen_mshflo_l_di (operands[0], operands[1], CONST0_RTX (DImode)));
   else
     emit_insn (gen_mshfhi_l_di (operands[0], CONST0_RTX (DImode), operands[1]));
   DONE;
-}"
+}
   [(set_attr "type" "arith_media")])
 
 (define_insn "andcsi3"
@@ -5638,7 +5638,9 @@ label:
   "TARGET_SH1
    && (arith_reg_operand (operands[0], DImode)
        || arith_reg_operand (operands[1], DImode))"
-  "* return output_movedouble (insn, operands, DImode);"
+{
+  return output_movedouble (insn, operands, DImode);
+}
   [(set_attr "length" "4")
    (set_attr "type" "pcload,move,load,store,move,pcload,move,move")])
 
@@ -13559,14 +13561,6 @@ label:
 }
   [(set_attr "type" "other")])
 
-(define_insn "*prefetch_i4"
-  [(prefetch (match_operand:SI 0 "register_operand" "r")
-             (match_operand:SI 1 "const_int_operand" "n")
-             (match_operand:SI 2 "const_int_operand" "n"))]
-  "(TARGET_HARD_SH4 || TARGET_SHCOMPACT) && !TARGET_VXWORKS_RTP"
-  "pref        @%0";
-  [(set_attr "type" "other")])
-
 ;; In user mode, the "pref" instruction will raise a RADDERR exception
 ;; for accesses to [0x80000000,0xffffffff].  This makes it an unsuitable
 ;; implementation of __builtin_prefetch for VxWorks RTPs.
@@ -13585,12 +13579,12 @@ label:
     operands[0] = force_reg (Pmode, operands[0]);
 })
 
-(define_insn "prefetch_m2a"
+(define_insn "*prefetch"
   [(prefetch (match_operand:SI 0 "register_operand" "r")
             (match_operand:SI 1 "const_int_operand" "n")
             (match_operand:SI 2 "const_int_operand" "n"))]
-  "TARGET_SH2A"
-  "pref\\t@%0"
+  "(TARGET_SH2A || TARGET_HARD_SH4 || TARGET_SHCOMPACT) && !TARGET_VXWORKS_RTP"
+  "pref        @%0"
   [(set_attr "type" "other")])
 
 (define_insn "alloco_i"

diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog
index 9553599aee4d2568345b072528f18dc870669ef2..49f0eb38433f282837601d4c5be788cd997546db 100644 (file)
--- a/gcc/testsuite/ChangeLog
+++ b/gcc/testsuite/ChangeLog
@@ -1,3 +1,8 @@
+2012-04-08  Oleg Endo  <olegendo@gcc.gnu.org>
+
+       * gcc.target/sh/sh2a-prefetch.c: Rename to ...
+       * gcc.target/sh/prefetch.c: ... this.  Enable test case for m4*.
+
 2012-04-08  Tobias Burnus  <burnus@net-b.de>
 
        PR fortran/40973
@@ -295,9 +300,9 @@
 2012-03-21  Oleg Endo  <olegendo@gcc.gnu.org>
 
        PR target/50751
-       * gcc/target/sh/pr50751-1.c: New.
-       * gcc/target/sh/pr50751-2.c: New.
-       * gcc/target/sh/pr50751-3.c: New.
+       * gcc.target/sh/pr50751-1.c: New.
+       * gcc.target/sh/pr50751-2.c: New.
+       * gcc.target/sh/pr50751-3.c: New.
 
 2012-03-21  Oleg Endo  <olegendo@gcc.gnu.org>
 

diff --git a/gcc/testsuite/gcc.target/sh/sh2a-prefetch.c b/gcc/testsuite/gcc.target/sh/prefetch.c
similarity index 80%
rename from gcc/testsuite/gcc.target/sh/sh2a-prefetch.c
rename to gcc/testsuite/gcc.target/sh/prefetch.c
index e0c9a0d7dc65a24d288f3c1fd226b899c4dcc61c..b34b115d6b8fde66d6ae2d8c7941f329549cd6c3 100644 (file)
--- a/gcc/testsuite/gcc.target/sh/sh2a-prefetch.c
+++ b/gcc/testsuite/gcc.target/sh/prefetch.c
@@ -1,7 +1,8 @@
-/* Testcase to check generation of a SH2A specific instruction PREF @Rm.  */
+/* Testcase to check generation of a SH4 and SH2A operand cache prefetch
+   instruction PREF @Rm.  */
 /* { dg-do assemble {target sh*-*-*}}  */
 /* { dg-options "-O0" }  */
-/* { dg-skip-if "" { "sh*-*-*" } "*" "-m2a -m2a-nofpu -m2a-single -m2a-single-only" }  */
+/* { dg-skip-if "" { "sh*-*-*" } { "*" } { "-m2a*" "-m4*" } }  */
 /* { dg-final { scan-assembler "pref"} }  */
 
 void