resource.c (find_free_register): Mark class_str argument const.

1999-10-04 21:58 -0700  Zack Weinberg  <zack@bitmover.com>

	* resource.c (find_free_register): Mark class_str argument const.
	* resource.h: Update prototype to match.

	* i386.h (PREDICATE_CODES): Add entry for long_memory_operand.
	* i386.md: Give all anonymous insns names.

From-SVN: r29821

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 38dfc2433c9c4b3953e307922bb7aeb7c3c16ce9..6e281153f848bb8b066edbe30c239209cf2a56b0 100644 (file)
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,11 @@
+1999-10-04 21:58 -0700  Zack Weinberg  <zack@bitmover.com>
+
+       * resource.c (find_free_register): Mark class_str argument const.
+       * resource.h: Update prototype to match.
+
+       * i386.h (PREDICATE_CODES): Add entry for long_memory_operand.
+       * i386.md: Give all anonymous insns names.
+
 Mon Oct  4 21:12:02 1999  Jeffrey A Law  (law@cygnus.com)
 
        * flow.c (merge_blocks): Avoid assing BASIC_BLOCK for non-existent

diff --git a/gcc/config/i386/i386.h b/gcc/config/i386/i386.h
index 3b302a254efcc03b2a7f57a4ea6bdfd5ae7fca86..4ad4ca9e7dba4304b8503d220fbf69d6840d02ff 100644 (file)
--- a/gcc/config/i386/i386.h
+++ b/gcc/config/i386/i386.h
@@ -2395,7 +2395,8 @@ do { long l;                                              \
                                 LSHIFTRT, ROTATERT}},                  \
   {"memory_displacement_operand", {MEM}},                              \
   {"cmpsi_operand", {CONST_INT, CONST_DOUBLE, CONST, SYMBOL_REF,       \
-                    LABEL_REF, SUBREG, REG, MEM, AND}},
+                    LABEL_REF, SUBREG, REG, MEM, AND}},                \
+  {"long_memory_operand", {MEM}},
 \f
 /* Variables in i386.c */
 extern const char *ix86_cpu_string;            /* for -mcpu=<xxx> */

diff --git a/gcc/config/i386/i386.md b/gcc/config/i386/i386.md
index 9c47e2d8abbd3c919225472ce741fe9757c5b704..ddb106bf4f95a97a1279236d3fdcbf97349bbde8 100644 (file)
--- a/gcc/config/i386/i386.md
+++ b/gcc/config/i386/i386.md
@@ -70,6 +70,10 @@
 ;; 9  This is an `fnstsw' operation.
 ;; 10 This is a `sahf' operation.
 ;; 11 This is a `fstcw' operation
+;;
+;; Insns whose names begin with "x86_" are emitted by gen_FOO calls
+;; from i386.c.
+
 \f
 ;; Processor type.  This attribute must exactly match the processor_type
 ;; enumeration in i386.h.
@@ -953,7 +957,7 @@
   "* return output_fp_compare (insn, operands, 0, 0);"
   [(set_attr "type" "fcmp")])
 
-(define_insn ""
+(define_insn "*cmpfp_2_sf_1"
   [(set (match_operand:HI 0 "register_operand" "=a")
        (unspec:HI
          [(compare:CCFP
@@ -972,7 +976,7 @@
   "* return output_fp_compare (insn, operands, 0, 0);"
   [(set_attr "type" "fcmp")])
 
-(define_insn ""
+(define_insn "*cmpfp_2_df_1"
   [(set (match_operand:HI 0 "register_operand" "=a")
        (unspec:HI
          [(compare:CCFP
@@ -991,7 +995,7 @@
   "* return output_fp_compare (insn, operands, 0, 0);"
   [(set_attr "type" "fcmp")])
 
-(define_insn ""
+(define_insn "*cmpfp_2_xf_1"
   [(set (match_operand:HI 0 "register_operand" "=a")
        (unspec:HI
          [(compare:CCFP
@@ -1012,7 +1016,7 @@
   "* return output_fp_compare (insn, operands, 0, 1);"
   [(set_attr "type" "fcmp")])
 
-(define_insn ""
+(define_insn "*cmpfp_2u_1"
   [(set (match_operand:HI 0 "register_operand" "=a")
        (unspec:HI
          [(compare:CCFPU
@@ -1031,7 +1035,7 @@
 ;; can get rid of this once we teach reload to do memory input reloads 
 ;; via pushes.
 
-(define_insn ""
+(define_insn "*ficom_1"
   [(set (reg:CCFP 18)
        (compare:CCFP
          (match_operand 0 "register_operand" "f,f")
@@ -2372,7 +2376,7 @@
 ;; emit moves.
 
 ;; %%% Kill these when call knows how to work out a DFmode push earlier. 
-(define_insn ""
+(define_insn "*dummy_extendsfdf2"
   [(set (match_operand:DF 0 "push_operand" "=<")
        (float_extend:DF (match_operand:SF 1 "nonimmediate_operand" "f")))]
   "0"
@@ -2385,7 +2389,7 @@
   [(set (reg:SI 7) (plus:SI (reg:SI 7) (const_int -8)))
    (set (mem:DF (reg:SI 7)) (float_extend:DF (match_dup 1)))])
 
-(define_insn ""
+(define_insn "*dummy_extendsfxf2"
   [(set (match_operand:XF 0 "push_operand" "=<")
        (float_extend:XF (match_operand:SF 1 "nonimmediate_operand" "f")))]
   "0"
@@ -2398,7 +2402,7 @@
   [(set (reg:SI 7) (plus:SI (reg:SI 7) (const_int -12)))
    (set (mem:DF (reg:SI 7)) (float_extend:XF (match_dup 1)))])
 
-(define_insn ""
+(define_insn "*dummy_extenddfxf2"
   [(set (match_operand:XF 0 "push_operand" "=<")
        (float_extend:XF (match_operand:DF 1 "nonimmediate_operand" "f")))]
   "0"
@@ -3117,7 +3121,7 @@
   [(set_attr "type" "alu")])
 
 ;; %%% Conditionally split these post-reload for better scheduling.
-(define_insn ""
+(define_insn "*addsi_lea_1"
   [(set (match_operand:SI 0 "register_operand" "=r")
         (plus:SI (plus:SI (match_operand:SI 1 "register_operand" "r")
                          (match_operand:SI 2 "register_operand" "%r"))
@@ -3130,7 +3134,7 @@
 }"
   [(set_attr "type" "lea")])
 
-(define_insn ""
+(define_insn "*addsi_lea_2"
   [(set (match_operand:SI 0 "register_operand" "=r")
         (plus:SI (mult:SI (match_operand:SI 1 "reg_no_sp_operand" "r")
                          (match_operand:SI 2 "const248_operand" "I"))
@@ -3143,7 +3147,7 @@
 }"
   [(set_attr "type" "lea")])
 
-(define_insn ""
+(define_insn "*addsi_lea_3"
   [(set (match_operand:SI 0 "register_operand" "=r")
         (plus:SI (plus:SI (mult:SI (match_operand:SI 1 "reg_no_sp_operand" "r")
                                   (match_operand:SI 2 "const248_operand" "I"))
@@ -3855,7 +3859,7 @@
   "{cltd|cdq}\;idiv{l}\\t%2"
   [(set_attr "type" "multi")])
 
-(define_insn ""
+(define_insn "*divmodsi_noext"
   [(set (match_operand:SI 0 "register_operand" "=a")
        (div:SI (match_operand:SI 1 "register_operand" "A")
                (match_operand:SI 2 "nonimmediate_operand" "rm")))
@@ -3920,7 +3924,7 @@
   "xor{l}\\t%3, %3\;div{l}\\t%2"
   [(set_attr "type" "multi")])
 
-(define_insn ""
+(define_insn "*udivmodsi4_noext"
   [(set (match_operand:SI 0 "register_operand" "=a")
        (udiv:SI (match_operand:SI 1 "register_operand" "0")
                 (match_operand:SI 2 "nonimmediate_operand" "rm")))
@@ -3964,7 +3968,7 @@
   ""
   "operands[4] = gen_reg_rtx (HImode);")
 
-(define_insn "*udivmodhi_1"
+(define_insn "*udivmodhi_noext"
   [(set (match_operand:HI 0 "register_operand" "=a")
        (udiv:HI (match_operand:HI 1 "register_operand" "0")
                 (match_operand:HI 2 "nonimmediate_operand" "rm")))
@@ -4084,7 +4088,7 @@
   [(set_attr "type" "icmp")])
 
 ;; Combine likes to form bit extractions for some tests.  Humor it.
-(define_insn ""
+(define_insn "*testqi_ext_3"
   [(set (reg:CCNO 17)
         (compare:CCNO (zero_extract:SI
                        (match_operand 0 "nonimmediate_operand" "rm")
@@ -4693,7 +4697,7 @@
   "neg{l}\\t%0"
   [(set_attr "type" "negnot")])
 
-(define_insn ""
+(define_insn "*negsi2_cmpno"
   [(set (reg:CCNO 17)
        (compare:CCNO (neg:SI (match_operand:SI 1 "nonimmediate_operand" "0"))
                 (const_int 0)))
@@ -4703,7 +4707,7 @@
   "neg{l}\\t%0"
   [(set_attr "type" "negnot")])
 
-(define_insn ""
+(define_insn "*negsi2_cmp"
   [(set (reg:CC 17)
        (compare:CC (neg:SI (match_operand:SI 1 "nonimmediate_operand" "0"))
                 (const_int 0)))
@@ -4721,7 +4725,7 @@
   "neg{w}\\t%0"
   [(set_attr "type" "negnot")])
 
-(define_insn ""
+(define_insn "*neghi2_cmpno"
   [(set (reg:CCNO 17)
        (compare:CCNO (neg:HI (match_operand:HI 1 "nonimmediate_operand" "0"))
                 (const_int 0)))
@@ -4731,7 +4735,7 @@
   "neg{w}\\t%0"
   [(set_attr "type" "negnot")])
 
-(define_insn ""
+(define_insn "*neghi2_cmp"
   [(set (reg:CC 17)
        (compare:CC (neg:HI (match_operand:HI 1 "nonimmediate_operand" "0"))
                 (const_int 0)))
@@ -4749,7 +4753,7 @@
   "neg{b}\\t%0"
   [(set_attr "type" "negnot")])
 
-(define_insn ""
+(define_insn "*negqi2_cmpno"
   [(set (reg:CCNO 17)
        (compare:CCNO (neg:QI (match_operand:QI 1 "nonimmediate_operand" "0"))
                 (const_int 0)))
@@ -4759,7 +4763,7 @@
   "neg{b}\\t%0"
   [(set_attr "type" "negnot")])
 
-(define_insn ""
+(define_insn "*negqi2_cmp"
   [(set (reg:CC 17)
        (compare:CC (neg:QI (match_operand:QI 1 "nonimmediate_operand" "0"))
                 (const_int 0)))
@@ -4785,7 +4789,7 @@
   [(set_attr "type" "fsgn")
    (set_attr "ppro_uops" "few")])
 
-(define_insn ""
+(define_insn "*negextendsfdf2"
   [(set (match_operand:DF 0 "register_operand" "=f")
        (neg:DF (float_extend:DF
                  (match_operand:SF 1 "register_operand" "0"))))]
@@ -4802,7 +4806,7 @@
   [(set_attr "type" "fsgn")
    (set_attr "ppro_uops" "few")])
 
-(define_insn ""
+(define_insn "*negextenddfxf2"
   [(set (match_operand:XF 0 "register_operand" "=f")
        (neg:XF (float_extend:XF
                  (match_operand:DF 1 "register_operand" "0"))))]
@@ -4811,7 +4815,7 @@
   [(set_attr "type" "fsgn")
    (set_attr "ppro_uops" "few")])
 
-(define_insn ""
+(define_insn "*negextendsfxf2"
   [(set (match_operand:XF 0 "register_operand" "=f")
        (neg:XF (float_extend:XF
                  (match_operand:SF 1 "register_operand" "0"))))]
@@ -4836,7 +4840,7 @@
   "fabs"
   [(set_attr "type" "fsgn")])
 
-(define_insn ""
+(define_insn "*absextendsfdf2"
   [(set (match_operand:DF 0 "register_operand" "=f")
        (abs:DF (float_extend:DF
                  (match_operand:SF 1 "register_operand" "0"))))]
@@ -4851,7 +4855,7 @@
   "fabs"
   [(set_attr "type" "fsgn")])
 
-(define_insn ""
+(define_insn "*absextenddfxf2"
   [(set (match_operand:XF 0 "register_operand" "=f")
        (abs:XF (float_extend:XF
          (match_operand:DF 1 "register_operand" "0"))))]
@@ -4859,7 +4863,7 @@
   "fabs"
   [(set_attr "type" "fsgn")])
 
-(define_insn ""
+(define_insn "*absextendsfxf2"
   [(set (match_operand:XF 0 "register_operand" "=f")
        (abs:XF (float_extend:XF
          (match_operand:SF 1 "register_operand" "0"))))]
@@ -4876,7 +4880,7 @@
   "not{l}\\t%0"
   [(set_attr "type" "negnot")])
 
-(define_insn ""
+(define_insn "*one_cmplsi2_1"
   [(set (reg:CCNO 17)
        (compare:CCNO (not:SI (match_operand:SI 1 "nonimmediate_operand" "0"))
                    (const_int 0)))
@@ -4917,7 +4921,7 @@
   "operands[0] = gen_lowpart (SImode, operands[0]);
    operands[1] = gen_lowpart (SImode, operands[1]);")
 
-(define_insn ""
+(define_insn "*one_cmplhi2_1"
   [(set (reg:CCNO 17)
        (compare:CCNO (not:HI (match_operand:HI 1 "nonimmediate_operand" "0"))
                      (const_int 0)))
@@ -4951,7 +4955,7 @@
    not{l}\\t%k0"
   [(set_attr "type" "negnot")])
 
-(define_insn ""
+(define_insn "*one_cmplqi2_1"
   [(set (reg:CCNO 17)
        (compare:CCNO (not:QI (match_operand:QI 1 "nonimmediate_operand" "0"))
                    (const_int 0)))
@@ -5156,7 +5160,7 @@
           ]
           (const_string "ishift")))])
 
-(define_insn ""
+(define_insn "*ashlsi3_cmpno"
   [(set (reg:CCNO 17)
        (compare:CCNO
          (ashift:SI (match_operand:SI 1 "nonimmediate_operand" "0")
@@ -5232,7 +5236,7 @@
   "operands[0] = gen_lowpart (SImode, operands[0]);
    operands[1] = gen_lowpart (SImode, operands[1]);")
 
-(define_insn ""
+(define_insn "*ashlhi3_cmpno"
   [(set (reg:CCNO 17)
        (compare:CCNO
          (ashift:HI (match_operand:HI 1 "nonimmediate_operand" "0")
@@ -5311,7 +5315,7 @@
           ]
           (const_string "ishift")))])
 
-(define_insn ""
+(define_insn "*ashlqi3_cmpno"
   [(set (reg:CCNO 17)
        (compare:CCNO
          (ashift:QI (match_operand:QI 1 "nonimmediate_operand" "0")
@@ -5468,7 +5472,7 @@
    sar{l}\\t{%b2, %0|%0, %b2}"
   [(set_attr "type" "ishift")])
 
-(define_insn ""
+(define_insn "*ashrsi3_cmpno"
   [(set (reg:CCNO 17)
        (compare:CCNO
          (ashiftrt:SI (match_operand:SI 1 "nonimmediate_operand" "0,0")
@@ -5493,7 +5497,7 @@
    sar{w}\\t{%b2, %0|%0, %b2}"
   [(set_attr "type" "ishift")])
 
-(define_insn ""
+(define_insn "*ashrhi3_cmpno"
   [(set (reg:CCNO 17)
        (compare:CCNO
          (ashiftrt:HI (match_operand:HI 1 "nonimmediate_operand" "0,0")
@@ -5518,7 +5522,7 @@
    sar{b}\\t{%b2, %0|%0, %b2}"
   [(set_attr "type" "ishift")])
 
-(define_insn ""
+(define_insn "*ashrqi3_cmpno"
   [(set (reg:CCNO 17)
        (compare:CCNO
          (ashiftrt:QI (match_operand:QI 1 "nonimmediate_operand" "0,0")
@@ -5600,7 +5604,7 @@
    shr{l}\\t{%b2, %0|%0, %b2}"
   [(set_attr "type" "ishift")])
 
-(define_insn ""
+(define_insn "*lshrsi3_cmpno"
   [(set (reg:CCNO 17)
        (compare:CCNO
          (lshiftrt:SI (match_operand:SI 1 "nonimmediate_operand" "0,0")
@@ -5625,7 +5629,7 @@
    shr{w}\\t{%b2, %0|%0, %b2}"
   [(set_attr "type" "ishift")])
 
-(define_insn ""
+(define_insn "*lshrhi3_cmpno"
   [(set (reg:CCNO 17)
        (compare:CCNO
          (lshiftrt:HI (match_operand:HI 1 "nonimmediate_operand" "0,0")
@@ -5650,7 +5654,7 @@
    shr{b}\\t{%b2, %0|%0, %b2}"
   [(set_attr "type" "ishift")])
 
-(define_insn ""
+(define_insn "*lshrqi2_cmpno"
   [(set (reg:CCNO 17)
        (compare:CCNO
          (lshiftrt:QI (match_operand:QI 1 "nonimmediate_operand" "0,0")
@@ -5677,7 +5681,7 @@
    rol{l}\\t{%b2, %0|%0, %b2}"
   [(set_attr "type" "ishift")])
 
-(define_insn ""
+(define_insn "*rotlsi3_cmpno"
   [(set (reg:CCNO 17)
        (compare:CCNO
          (rotate:SI (match_operand:SI 1 "nonimmediate_operand" "0,0")
@@ -5702,7 +5706,7 @@
    rol{w}\\t{%b2, %0|%0, %b2}"
   [(set_attr "type" "ishift")])
 
-(define_insn ""
+(define_insn "*rotlhi3_cmpno"
   [(set (reg:CCNO 17)
        (compare:CCNO
          (rotate:HI (match_operand:HI 1 "nonimmediate_operand" "0,0")
@@ -5727,7 +5731,7 @@
    rol{b}\\t{%b2, %0|%0, %b2}"
   [(set_attr "type" "ishift")])
 
-(define_insn ""
+(define_insn "*rotlqi3_cmpno"
   [(set (reg:CCNO 17)
        (compare:CCNO
          (rotate:QI (match_operand:QI 1 "nonimmediate_operand" "0,0")
@@ -5752,7 +5756,7 @@
    ror{l}\\t{%b2, %0|%0, %b2}"
   [(set_attr "type" "ishift")])
 
-(define_insn ""
+(define_insn "*rotrsi3_cmpno"
   [(set (reg:CCNO 17)
        (compare:CCNO
          (rotatert:SI (match_operand:SI 1 "nonimmediate_operand" "0,0")
@@ -5777,7 +5781,7 @@
    ror{w}\\t{%b2, %0|%0, %b2}"
   [(set_attr "type" "ishift")])
 
-(define_insn ""
+(define_insn "*rotrhi3_cmpno"
   [(set (reg:CCNO 17)
        (compare:CCNO
          (rotatert:HI (match_operand:HI 1 "nonimmediate_operand" "0,0")
@@ -5802,7 +5806,7 @@
    ror{b}\\t{%b2, %0|%0, %b2}"
   [(set_attr "type" "ishift")])
 
-(define_insn ""
+(define_insn "*rotrqi3_cmpno"
   [(set (reg:CCNO 17)
        (compare:CCNO
          (rotatert:QI (match_operand:QI 1 "nonimmediate_operand" "0,0")
@@ -6224,7 +6228,7 @@
   current_function_uses_pic_offset_table = 1;
 }")
 
-(define_insn ""
+(define_insn "*tablejump_pic"
   [(set (pc) (match_operand:SI 0 "nonimmediate_operand" "rm"))
    (use (label_ref (match_operand 1 "" "")))]
   ""
@@ -6250,7 +6254,7 @@
   "TARGET_USE_LOOP"
   "")
 
-(define_insn ""
+(define_insn "*dbra_ne"
   [(set (pc)
        (if_then_else (ne (match_operand:SI 1 "register_operand" "c,*r,*r")
                          (const_int 1))
@@ -6282,7 +6286,7 @@
                      (const_int 2)
                      (const_int 16)))])
 
-(define_insn ""
+(define_insn "*dbra_ge"
   [(set (pc)
        (if_then_else (ge (match_operand:SI 1 "register_operand" "c,*r,*r")
                          (const_int 0))
@@ -6448,7 +6452,7 @@
                        copy_to_mode_reg (Pmode, XEXP (operands[0], 0)));
 }")
 
-(define_insn ""
+(define_insn "*call_pop_pic"
   [(call (match_operand:QI 0 "call_insn_operand" "m")
         (match_operand:SI 1 "general_operand" "g"))
    (set (reg:SI 7) (plus:SI (reg:SI 7)
@@ -6464,7 +6468,7 @@
 }"
   [(set_attr "type" "call")])
 
-(define_insn ""
+(define_insn "*call_pop_pic2"
   [(call (match_operand:QI 0 "constant_call_address_operand" "")
          (match_operand:SI 1 "general_operand" "g"))
    (set (reg:SI 7) (plus:SI (reg:SI 7)
@@ -6496,7 +6500,7 @@
                        copy_to_mode_reg (Pmode, XEXP (operands[0], 0)));
 }")
 
-(define_insn ""
+(define_insn "*call_pic"
   [(call (match_operand:QI 0 "call_insn_operand" "m")
         (match_operand:SI 1 "general_operand" "g"))]
   ;; Operand 1 not used on the i386.
@@ -6511,7 +6515,7 @@
 }"
   [(set_attr "type" "call")])
 
-(define_insn ""
+(define_insn "*call_pic2"
   [(call (match_operand:QI 0 "constant_call_address_operand" "")
          (match_operand:SI 1 "general_operand" "g"))]
   "!HALF_PIC_P ()"
@@ -6553,7 +6557,7 @@
                        copy_to_mode_reg (Pmode, XEXP (operands[1], 0)));
 }")
 
-(define_insn ""
+(define_insn "*call_value_pop_pic"
   [(set (match_operand 0 "" "=rf")
        (call (match_operand:QI 1 "call_insn_operand" "m")
              (match_operand:SI 2 "general_operand" "g")))
@@ -6570,7 +6574,7 @@
 }"
   [(set_attr "type" "callv")])
 
-(define_insn ""
+(define_insn "*call_value_pop_pic2"
   [(set (match_operand 0 "" "=rf")
        (call (match_operand:QI 1 "constant_call_address_operand" "")
              (match_operand:SI 2 "general_operand" "g")))
@@ -6604,7 +6608,7 @@
                        copy_to_mode_reg (Pmode, XEXP (operands[1], 0)));
 }")
 
-(define_insn ""
+(define_insn "*call_value_pic"
   [(set (match_operand 0 "" "=rf")
        (call (match_operand:QI 1 "call_insn_operand" "m")
              (match_operand:SI 2 "general_operand" "g")))]
@@ -6620,7 +6624,7 @@
 }"
   [(set_attr "type" "callv")])
 
-(define_insn ""
+(define_insn "*call_value_pic2"
   [(set (match_operand 0 "" "=rf")
        (call (match_operand:QI 1 "constant_call_address_operand" "")
              (match_operand:SI 2 "general_operand" "g")))]
@@ -7158,7 +7162,7 @@
   "fsqrt"
   [(set_attr "type" "fpspc")])
 
-(define_insn ""
+(define_insn "*sqrtextendsfdf2"
   [(set (match_operand:DF 0 "register_operand" "=f")
        (sqrt:DF (float_extend:DF
                  (match_operand:SF 1 "register_operand" "0"))))]
@@ -7174,7 +7178,7 @@
   "fsqrt"
   [(set_attr "type" "fpspc")])
 
-(define_insn ""
+(define_insn "*sqrtextenddfxf2"
   [(set (match_operand:XF 0 "register_operand" "=f")
        (sqrt:XF (float_extend:XF
                  (match_operand:DF 1 "register_operand" "0"))))]
@@ -7182,7 +7186,7 @@
   "fsqrt"
   [(set_attr "type" "fpspc")])
 
-(define_insn ""
+(define_insn "*sqrtextendsfxf2"
   [(set (match_operand:XF 0 "register_operand" "=f")
        (sqrt:XF (float_extend:XF
                  (match_operand:SF 1 "register_operand" "0"))))]
@@ -7204,7 +7208,7 @@
   "fsin"
   [(set_attr "type" "fpspc")])
 
-(define_insn ""
+(define_insn "*sinextendsfdf2"
   [(set (match_operand:DF 0 "register_operand" "=f")
        (unspec:DF [(float_extend:DF
                     (match_operand:SF 1 "register_operand" "0"))] 1))]
@@ -7233,7 +7237,7 @@
   "fcos"
   [(set_attr "type" "fpspc")])
 
-(define_insn ""
+(define_insn "*cosextendsfdf2"
   [(set (match_operand:DF 0 "register_operand" "=f")
        (unspec:DF [(float_extend:DF
                     (match_operand:SF 1 "register_operand" "0"))] 2))]
@@ -7594,7 +7598,7 @@
    (set_attr "imm_disp" "false")
    (set_attr "length" "2")])
 
-(define_insn ""
+(define_insn "*movsicc_noc"
   [(set (match_operand:SI 0 "register_operand" "=r,r")
        (if_then_else:SI (match_operator 1 "no_comparison_operator" 
                                [(reg 17) (const_int 0)])
@@ -7606,7 +7610,7 @@
    cmov%c1\\t{%3, %0|%0, %3}"
   [(set_attr "type" "icmov")])
 
-(define_insn ""
+(define_insn "*movsicc_c"
   [(set (match_operand:SI 0 "register_operand" "=r,r")
        (if_then_else:SI (match_operator 1 "comparison_operator" 
                                [(reg:CC 17) (const_int 0)])
@@ -7626,7 +7630,7 @@
   "TARGET_CMOVE"
   "if (!ix86_expand_int_movcc (operands)) FAIL; DONE;")
 
-(define_insn ""
+(define_insn "*movhicc_noc"
   [(set (match_operand:HI 0 "register_operand" "=r,r")
        (if_then_else:HI (match_operator 1 "no_comparison_operator" 
                                [(reg 17) (const_int 0)])
@@ -7638,7 +7642,7 @@
    cmov%c1\\t{%3, %0|%0, %3}"
   [(set_attr "type" "icmov")])
 
-(define_insn ""
+(define_insn "*movhicc_c"
   [(set (match_operand:HI 0 "register_operand" "=r,r")
        (if_then_else:HI (match_operator 1 "comparison_operator" 
                                [(reg:CC 17) (const_int 0)])
@@ -7671,7 +7675,7 @@
   "TARGET_CMOVE"
   "if (! ix86_expand_fp_movcc (operands)) FAIL; DONE;")
 
-(define_insn ""
+(define_insn "*movsfcc_1"
   [(set (match_operand:SF 0 "register_operand" "=f,f")
        (if_then_else:SF (match_operator 1 "fcmov_comparison_operator" 
                                [(reg 17) (const_int 0)])
@@ -7691,7 +7695,7 @@
   "TARGET_CMOVE"
   "if (! ix86_expand_fp_movcc (operands)) FAIL; DONE;")
 
-(define_insn ""
+(define_insn "*movdfcc_1"
   [(set (match_operand:DF 0 "register_operand" "=f,f")
        (if_then_else:DF (match_operator 1 "fcmov_comparison_operator" 
                                [(reg 17) (const_int 0)])
@@ -7711,7 +7715,7 @@
   "TARGET_CMOVE"
   "if (! ix86_expand_fp_movcc (operands)) FAIL; DONE;")
 
-(define_insn ""
+(define_insn "*movxfcc_1"
   [(set (match_operand:XF 0 "register_operand" "=f,f")
        (if_then_else:XF (match_operator 1 "fcmov_comparison_operator" 
                                [(reg 17) (const_int 0)])

diff --git a/gcc/resource.c b/gcc/resource.c
index 3dce3b1df40b1744c1742570bf12a1f64f572bab..e40619efb950b82a519345dbb4f50179696cb9bd 100644 (file)
--- a/gcc/resource.c
+++ b/gcc/resource.c
@@ -1249,7 +1249,7 @@ mark_end_of_function_resources (trial, include_delayed_effects)
 rtx
 find_free_register (current_insn, last_insn, class_str, mode, reg_set)
      rtx current_insn, last_insn;
-     char *class_str;
+     const char *class_str;
      int mode;
      HARD_REG_SET *reg_set;
 {

diff --git a/gcc/resource.h b/gcc/resource.h
index a867baefce0153fd147cc828f200562536ea5a0b..ea7c4b28c8808ae5e0b2281764d5de4a481b534a 100644 (file)
--- a/gcc/resource.h
+++ b/gcc/resource.h
@@ -42,6 +42,6 @@ extern void incr_ticks_for_insn               PROTO((rtx));
 extern void mark_end_of_function_resources PROTO ((rtx, int));
 extern void init_resource_info         PROTO((rtx));
 extern void free_resource_info         PROTO((void));
-extern rtx find_free_register          PROTO((rtx, rtx, char *, int,
+extern rtx find_free_register          PROTO((rtx, rtx, const char *, int,
                                               HARD_REG_SET *));
 extern int reg_dead_p                  PROTO((rtx, rtx));