i386: Don't optimize vshuf{i,f}{32x4,64x2} and vperm{i,f}128 to vblendps for %ymm16...

The vblendps instruction is only VEX encoded, not EVEX, so can't be used if
there are %ymm16+ or EGPR registers involved.

2023-11-14  Jakub Jelinek  <jakub@redhat.com>
	    Hu, Lin1  <lin1.hu@intel.com>

	PR target/112435
	* config/i386/sse.md (avx512vl_shuf_<shuffletype>32x4_1<mask_name>,
	<mask_codefor>avx512dq_shuf_<shuffletype>64x2_1<mask_name>): Add
	alternative with just x instead of v constraints and xjm instead of
	vm and use vblendps as optimization only with that alternative.

	* gcc.target/i386/avx512vl-pr112435-1.c: New test.
	* gcc.target/i386/avx512vl-pr112435-2.c: New test.
	* gcc.target/i386/avx512vl-pr112435-3.c: New test.

diff --git a/gcc/config/i386/sse.md b/gcc/config/i386/sse.md
index c502582102e0e0a4d52837e43785c737c12734a1..af482f24df4dbad558bd11ff3cfc36a19d4bc1f0 100644 (file)
--- a/gcc/config/i386/sse.md
+++ b/gcc/config/i386/sse.md
@@ -19235,11 +19235,11 @@
 })
 
 (define_insn "<mask_codefor>avx512dq_shuf_<shuffletype>64x2_1<mask_name>"
-  [(set (match_operand:VI8F_256 0 "register_operand" "=v")
+  [(set (match_operand:VI8F_256 0 "register_operand" "=x,v")
        (vec_select:VI8F_256
          (vec_concat:<ssedoublemode>
-           (match_operand:VI8F_256 1 "register_operand" "v")
-           (match_operand:VI8F_256 2 "nonimmediate_operand" "vm"))
+           (match_operand:VI8F_256 1 "register_operand" "x,v")
+           (match_operand:VI8F_256 2 "nonimmediate_operand" "xjm,vm"))
          (parallel [(match_operand 3 "const_0_to_3_operand")
                     (match_operand 4 "const_0_to_3_operand")
                     (match_operand 5 "const_4_to_7_operand")
@@ -19254,7 +19254,7 @@
   mask = INTVAL (operands[3]) / 2;
   mask |= (INTVAL (operands[5]) - 4) / 2 << 1;
   operands[3] = GEN_INT (mask);
-  if (INTVAL (operands[3]) == 2 && !<mask_applied>)
+  if (INTVAL (operands[3]) == 2 && !<mask_applied> && which_alternative == 0)
     return "vblendps\t{$240, %2, %1, %0|%0, %1, %2, 240}";
   return "vshuf<shuffletype>64x2\t{%3, %2, %1, %0<mask_operand7>|%0<mask_operand7>, %1, %2, %3}";
 }
@@ -19386,11 +19386,11 @@
 })
 
 (define_insn "avx512vl_shuf_<shuffletype>32x4_1<mask_name>"
-  [(set (match_operand:VI4F_256 0 "register_operand" "=v")
+  [(set (match_operand:VI4F_256 0 "register_operand" "=x,v")
        (vec_select:VI4F_256
          (vec_concat:<ssedoublemode>
-           (match_operand:VI4F_256 1 "register_operand" "v")
-           (match_operand:VI4F_256 2 "nonimmediate_operand" "vm"))
+           (match_operand:VI4F_256 1 "register_operand" "x,v")
+           (match_operand:VI4F_256 2 "nonimmediate_operand" "xjm,vm"))
          (parallel [(match_operand 3 "const_0_to_7_operand")
                     (match_operand 4 "const_0_to_7_operand")
                     (match_operand 5 "const_0_to_7_operand")
@@ -19414,7 +19414,7 @@
   mask |= (INTVAL (operands[7]) - 8) / 4 << 1;
   operands[3] = GEN_INT (mask);
 
-  if (INTVAL (operands[3]) == 2 && !<mask_applied>)
+  if (INTVAL (operands[3]) == 2 && !<mask_applied> && which_alternative == 0)
     return "vblendps\t{$240, %2, %1, %0|%0, %1, %2, 240}";
 
   return "vshuf<shuffletype>32x4\t{%3, %2, %1, %0<mask_operand11>|%0<mask_operand11>, %1, %2, %3}";

diff --git a/gcc/testsuite/gcc.target/i386/avx512vl-pr112435-1.c b/gcc/testsuite/gcc.target/i386/avx512vl-pr112435-1.c
new file mode 100644 (file)
index 0000000..46aae28
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/avx512vl-pr112435-1.c
@@ -0,0 +1,13 @@
+/* PR target/112435 */
+/* { dg-do assemble { target { avx512vl && { ! ia32 } } } } */
+/* { dg-options "-mavx512vl -O2" } */
+
+#include <x86intrin.h>
+
+__m256i
+foo (__m256i a, __m256i b)
+{
+  register __m256i c __asm__("ymm16") = a;
+  asm ("" : "+v" (c));
+  return _mm256_shuffle_i32x4 (c, b, 2);
+}

diff --git a/gcc/testsuite/gcc.target/i386/avx512vl-pr112435-2.c b/gcc/testsuite/gcc.target/i386/avx512vl-pr112435-2.c
new file mode 100644 (file)
index 0000000..a856fb5
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/avx512vl-pr112435-2.c
@@ -0,0 +1,63 @@
+/* PR target/112435 */
+/* { dg-do assemble { target { avx512vl && { ! ia32 } } } } */
+/* { dg-options "-mavx512vl -O2" } */
+
+#include <x86intrin.h>
+
+/* vpermi128/vpermf128 */
+__m256i
+perm0 (__m256i a, __m256i b)
+{
+  register __m256i c __asm__("ymm17") = a;
+  asm ("":"+v" (c));
+  return _mm256_permute2x128_si256 (c, b, 50);
+}
+
+__m256i
+perm1 (__m256i a, __m256i b)
+{
+  register __m256i c __asm__("ymm17") = a;
+  asm ("":"+v" (c));
+  return _mm256_permute2x128_si256 (c, b, 18);
+}
+
+__m256i
+perm2 (__m256i a, __m256i b)
+{
+  register __m256i c __asm__("ymm17") = a;
+  asm ("":"+v" (c));
+  return _mm256_permute2x128_si256 (c, b, 48);
+}
+
+/* vshuf{i,f}{32x4,64x2} ymm .*/
+__m256i
+shuff0 (__m256i a, __m256i b)
+{
+  register __m256i c __asm__("ymm17") = a;
+  asm ("":"+v" (c));
+  return _mm256_shuffle_i32x4 (c, b, 2);
+}
+
+__m256
+shuff1 (__m256 a, __m256 b)
+{
+  register __m256 c __asm__("ymm17") = a;
+  asm ("":"+v" (c));
+  return _mm256_shuffle_f32x4 (c, b, 2);
+}
+
+__m256i
+shuff2 (__m256i a, __m256i b)
+{
+  register __m256i c __asm__("ymm17") = a;
+  asm ("":"+v" (c));
+  return _mm256_shuffle_i64x2 (c, b, 2);
+}
+
+__m256d
+shuff3 (__m256d a, __m256d b)
+{
+  register __m256d c __asm__("ymm17") = a;
+  asm ("":"+v" (c));
+  return _mm256_shuffle_f64x2 (c, b, 2);
+}

diff --git a/gcc/testsuite/gcc.target/i386/avx512vl-pr112435-3.c b/gcc/testsuite/gcc.target/i386/avx512vl-pr112435-3.c
new file mode 100644 (file)
index 0000000..f7538ff
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/avx512vl-pr112435-3.c
@@ -0,0 +1,78 @@
+/* PR target/112435 */
+/* { dg-do assemble { target { avx512vl && { ! ia32 } } } } */
+/* { dg-options "-mavx512vl -O2" } */
+
+#include <x86intrin.h>
+
+/* vpermf128 */
+__m256
+perm0 (__m256 a, __m256 b)
+{
+  register __m256 c __asm__("ymm17") =a;
+  asm ("":"+v" (c));
+  return _mm256_permute2f128_ps (c, b, 50);
+}
+
+__m256
+perm1 (__m256 a, __m256 b)
+{
+  register __m256 c __asm__("ymm17") =a;
+  asm ("":"+v" (c));
+  return _mm256_permute2f128_ps (c, b, 18);
+}
+
+__m256
+perm2 (__m256 a, __m256 b)
+{
+  register __m256 c __asm__("ymm17") =a;
+  asm ("":"+v" (c));
+  return _mm256_permute2f128_ps (c, b, 48);
+}
+
+__m256i
+perm3 (__m256i a, __m256i b)
+{
+  register __m256i c __asm__("ymm17") =a;
+  asm ("":"+v" (c));
+  return _mm256_permute2f128_si256 (c, b, 50);
+}
+
+__m256i
+perm4 (__m256i a, __m256i b)
+{
+  register __m256i c __asm__("ymm17") =a;
+  asm ("":"+v" (c));
+  return _mm256_permute2f128_si256 (c, b, 18);
+}
+
+__m256i
+perm5 (__m256i a, __m256i b)
+{
+  register __m256i c __asm__("ymm17") =a;
+  asm ("":"+v" (c));
+  return _mm256_permute2f128_si256 (c, b, 48);
+}
+
+__m256d
+perm6 (__m256d a, __m256d b)
+{
+  register __m256d c __asm__("ymm17") =a;
+  asm ("":"+v" (c));
+  return _mm256_permute2f128_pd (c, b, 50);
+}
+
+__m256d
+perm7 (__m256d a, __m256d b)
+{
+  register __m256d c __asm__("ymm17") =a;
+  asm ("":"+v" (c));
+  return _mm256_permute2f128_pd (c, b, 18);
+}
+
+__m256d
+perm8 (__m256d a, __m256d b)
+{
+  register __m256d c __asm__("ymm17") =a;
+  asm ("":"+v" (c));
+  return _mm256_permute2f128_pd (c, b, 48);
+}