+2002-08-15 Eric Christopher <echristo@redhat.com>
+
+ * config.sub: Import from master repository.
+ * config.guess: Ditto.
+
2002-08-19 Alexandre Oliva <aoliva@redhat.com>
* Makefile.in (GCC_FOR_TARGET): Prepend STAGE_CC_WRAPPER.
C++ headers if --enable-version-specific-runtime-libs is used.
2002-07-04 Steve Ellcey <sje@cup.hp.com>
-
+
* ltcf-cxx.sh (hpux*): Modify to support ia64-*-hpux*.
2002-07-03 Nathanael Nerode <neroden@gcc.gnu.org>
2002-06-26 Benjamin Kosnik <bkoz@redhat.com>
* config.if (libstdcxx_incdir): Version C++ headers.
- (cxx_incdir): Remove.
+ (cxx_incdir): Remove.
2002-06-25 Nathanael Nerode <neroden@gcc.gnu.org>
* config.sub: Add support for avr target.
Import from master sources, rev 1.255
-
+
2002-06-19 Phil Edwards <pme@gcc.gnu.org>
* configure, .cvsignore: Revert previous change...
* configure.in (target_libs): Remove target-libchill.
Do not compute CHILL_FOR_TARGET.
* libchill: Remove directory.
-
+
2002-04-11 DJ Delorie <dj@redhat.com>
* Makefile.in, configure.in: Sync with binutils, entries
* gcc/Makefile.in: Removed libstdc++-v3 dependancy for libjava and
boehm-gc
-
+
2002-02-09 Alexandre Oliva <aoliva@redhat.com>
* config.guess: Updated to 2002-01-30's version.
2002-01-26 Jason Thorpe <thorpej@wasabisystems.com>
- * configure.in (*-*-netbsd*): New. Skip target-newlib,
- target-libiberty, and target-libgloss. Skip Java-related
+ * configure.in (*-*-netbsd*): New. Skip target-newlib,
+ target-libiberty, and target-libgloss. Skip Java-related
libraries if not supported for NetBSD on target CPU.
2002-01-25 Douglas B Rupp <rupp@gnat.com>
# Copyright (C) 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
# 2000, 2001, 2002 Free Software Foundation, Inc.
-timestamp='2002-07-09'
+timestamp='2002-08-19'
# This file is free software; you can redistribute it and/or modify it
# under the terms of the GNU General Public License as published by
# A Tn.n version is a released field test version.
# A Xn.n version is an unreleased experimental baselevel.
# 1.2 uses "1.2" for uname -r.
+ eval $set_cc_for_build
cat <<EOF >$dummy.s
.data
\$Lformat:
jsr \$26,exit
.end main
EOF
- eval $set_cc_for_build
$CC_FOR_BUILD $dummy.s -o $dummy 2>/dev/null
if test "$?" = 0 ; then
case `$dummy` in
2-1307)
UNAME_MACHINE="alphaev68"
;;
+ 3-1307)
+ UNAME_MACHINE="alphaev7"
+ ;;
esac
fi
rm -f $dummy.s $dummy && rmdir $tmpdir
;;
a.out-i386-linux)
echo "${UNAME_MACHINE}-pc-linux-gnuaout"
- exit 0 ;;
+ exit 0 ;;
coff-i386)
echo "${UNAME_MACHINE}-pc-linux-gnucoff"
exit 0 ;;
SX-5:SUPER-UX:*:*)
echo sx5-nec-superux${UNAME_RELEASE}
exit 0 ;;
+ SX-6:SUPER-UX:*:*)
+ echo sx6-nec-superux${UNAME_RELEASE}
+ exit 0 ;;
Power*:Rhapsody:*:*)
echo powerpc-apple-rhapsody${UNAME_RELEASE}
exit 0 ;;
# Copyright (C) 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
# 2000, 2001, 2002 Free Software Foundation, Inc.
-timestamp='2002-07-03'
+timestamp='2002-08-20'
# This file is (in principle) common to ALL GNU software.
# The presence of a machine in this file suggests that SOME GNU software
| mips | mipsbe | mipseb | mipsel | mipsle \
| mips16 \
| mips64 | mips64el \
+ | mips64vr | mips64vrel \
| mips64orion | mips64orionel \
| mips64vr4100 | mips64vr4100el \
| mips64vr4300 | mips64vr4300el \
| mipsisa32 | mipsisa32el \
| mipsisa64 | mipsisa64el \
| mipsisa64sb1 | mipsisa64sb1el \
+ | mipsisa64sr71k | mipsisa64sr71kel \
| mipstx39 | mipstx39el \
| mn10200 | mn10300 \
| ns16k | ns32k \
| mips-* | mipsbe-* | mipseb-* | mipsel-* | mipsle-* \
| mips16-* \
| mips64-* | mips64el-* \
+ | mips64vr-* | mips64vrel-* \
| mips64orion-* | mips64orionel-* \
| mips64vr4100-* | mips64vr4100el-* \
| mips64vr4300-* | mips64vr4300el-* \
| mipsisa32-* | mipsisa32el-* \
| mipsisa64-* | mipsisa64el-* \
| mipsisa64sb1-* | mipsisa64sb1el-* \
+ | mipsisa64sr71k-* | mipsisa64sr71kel-* \
| mipstx39 | mipstx39el \
| none-* | np1-* | ns16k-* | ns32k-* \
| orion-* \
pentium | p5 | k5 | k6 | nexgen | viac3)
basic_machine=i586-pc
;;
- pentiumpro | p6 | 6x86 | athlon)
+ pentiumpro | p6 | 6x86 | athlon | athlon_*)
basic_machine=i686-pc
;;
pentiumii | pentium2)
basic_machine=a29k-amd
os=-udi
;;
+ sb1)
+ basic_machine=mipsisa64sb1-unknown
+ ;;
+ sb1el)
+ basic_machine=mipsisa64sb1el-unknown
+ ;;
sequent)
basic_machine=i386-sequent
;;
+2002-08-15 Eric Christopher <echristo@redhat.com>
+ Jeff Knaggs <jknaggs@redhat.com>
+
+ * config.gcc (mipsisa64sr71k-elf): New target.
+ * config/mips/sr71k.md: New file.
+ * config/mips/mips.md: Use it.
+ (rot*): Add sr71k specifics.
+ * config/mips/t-sr71k: New file.
+ * config/mips/mips.h (sr71k): New cpu.
+ (TARGET_SR71K): Use it.
+ (TUNE_SR71K): Ditto.
+ (GENERATE_BRANCHLIKELY): Ditto.
+ (ISA_HAS_MULHI, ISA_HAS_MULS, ISA_HAS_MSAC, ISA_HAS_MACC,
+ ISA_HAS_ROTR_SIISA_HAS_ROTR_DI): Ditto.
+ * config/mips/mips.c (sr71k): New cpu.
+ (mips_use_dfa_pipeline_interface): Use.
+
+2002-08-15 Eric Christopher <echristo@redhat.com>
+ Richard Sandiford <rsandifo@redhat.com>
+ Aldy Hernandez <aldyh@redhat.com>
+ Graham Stott <grahams@redhat.com>
+ Michael Meissner <meissner@redhat.com>
+ Gavin Romig-Koch <gavin@redhat.com>
+ Ken Raeburn <raeburn@cygnus.com>
+ Alexandre Oliva <aoliva@redhat.com>
+
+ * config.gcc (mips64vr-elf): New target.
+ * config/mips/5400.md: New file.
+ * config/mips/5500.md: Ditto.
+ * config/mips/mips.md: Use them.
+ (frsqrt): New.
+ * config/mips/mips.c (vr4111, vr4121, vr4320, vr5400, vr5500): New
+ cpus.
+ (mips_issue_rate): Use them.
+ (mips_use_dfa_pipeline_interface): New function. Use for 5400 and 5500.
+ (TARGET_SCHEDUSE_DFA_PIPELINE_INTERFACE): Define. Use above.
+ * config/mips/mips.h (vr4111, vr4121, vr4320, vr5400, vr5500): New
+ cpus.
+ (TARGET_MIPSx): Use them.
+ (TUNE_MIPSx): Ditto.
+ (GETNATE_MULT3_SI): Ditto.
+ (ISA_HAS_BRANCHLIKELY): Ditto.
+ (ISA_HAS_CONDMOVE): Ditto.
+ (ISA_HAS_NMADD_NMSUB): Ditto.
+ (ISA_HAS_MULHI): New. Ditto.
+ (ISA_HAS_MULS): Ditto.
+ (ISA_HAS_MSAC): Ditto.
+ (ISA_HAS_MACC): Ditto.
+ (ISA_HAS_ROTR_SI): Ditto.
+ (ISA_HAS_ROTR_DI): Ditto.
+ (RTX_COSTS): Use.
+
2002-08-20 John David Anglin <dave@hiauly1.hia.nrc.ca>
* cppinit.c (remove_dup_dir): Add head_ptr argument to handle removal
(build_private_template): Call get_class_ivars instead of
build_ivar_chain.
(start_class): Allocate room for the CLASS_OWN_IVARS slot.
- (continue_class): Call get_class_ivars instead of
+ (continue_class): Call get_class_ivars instead of
build_ivar_chain.
(encode_field_decl): Check for DECL_BIT_FIELD_TYPE instead
of DECL_BIT_FIELD (which may have been cleared).
* config/rs6000/rs6000.c (rs6000_emit_set_const): Inline
multi-instruction SImode constant. Add REG_EQUAL note.
* config/rs6000/rs6000.md (movsi splitter): Use
- rs6000_emit_set_const.
+ rs6000_emit_set_const.
2002-08-19 Kaveh R. Ghazi <ghazi@caip.rutgers.edu>
Fix PR/7566
* c-semantics.c (genrtl_case_label): Don't (mis)use
- warning_with_decl.
+ warning_with_decl.
2002-08-14 Dale Johannesen <dalej@apple.com>
2002-08-14 Ulrich Weigand <uweigand@de.ibm.com>
- * reload.c (find_reloads): Handle constraint letters marked by
+ * reload.c (find_reloads): Handle constraint letters marked by
EXTRA_ADDRESS_CONSTRAINT and EXTRA_MEMORY_CONSTRAINT.
(alternative_allows_memconst): Likewise.
* reload1.c (maybe_fix_stack_asms): Likewise.
- * recog.c (asm_operand_ok, preprocess_constraints,
+ * recog.c (asm_operand_ok, preprocess_constraints,
constrain_operands): Likewise.
* regclass.c (record_operand_costs, record_reg_classes): Likewise.
* local-alloc.c (block_alloc, requires_inout): Likewise.
(__premain, exit, abort, _cleanup, memcpy, memset, ___adddi3,
___subdi3, ___notdi2, __mulhi32, __mulsi3): Use them to use 'rtc'
and declare the symbol far when compiled with -mlong-calls.
- (__far_trampoline): New for 68HC12 trampoline code to invoke a
+ (__far_trampoline): New for 68HC12 trampoline code to invoke a
far handler using jsr/bsr.
* config/m68hc11/m68hc11-crt0.S: Put a mode for ELF ABI flags.
* config/m68hc11/m68hc11.h (CPP_SPEC): Pass -D__USE_RTC__ when
-mlong-calls is specified.
- (ASM_DECLARE_FUNCTION_NAME): Define to generate .far and .interrupt
+ (ASM_DECLARE_FUNCTION_NAME): Define to generate .far and .interrupt
assembler directives.
(TARGET_LONG_CALL, MASK_LONG_CALL): Declare.
(TARGET_SWITCHES): Add -mlong-calls options.
"*tmqi_mem", "*tmhi_full", "*tmqi_full"): ... these new patterns.
("*ltgr", "*cmpdi_ccs_0_64", "*cmpdi_ccs_0_31", "*ltr", "*icm15",
- "*icm15_cconly", "*cmpsi_ccs_0", "*icm3", "*cmphi_ccs_0", "*icm1",
+ "*icm15_cconly", "*cmpsi_ccs_0", "*icm3", "*cmphi_ccs_0", "*icm1",
"*cmpqi_ccs_0"): Remove, replace by ...
("*tstdi_sign", "*tstdi", "*tstdi_cconly", "*tstdi_cconly_31",
- "*tstsi", "*tstsi_cconly", "*tstsi_cconly2", "*tsthi", "*tsthi_cconly",
+ "*tstsi", "*tstsi_cconly", "*tstsi_cconly2", "*tsthi", "*tsthi_cconly",
"*tstqi", "*tstqi_cconly"): ... these new patterns.
("*cmpsidi_ccs"): Remove, replace by ...
("adddi3"): Adapt expander.
("*addsi3_cc"): Allow "general_operand" for operand 2.
- ("*addsi3_carry1_cc", "*addsi3_carry1_cconly",
+ ("*addsi3_carry1_cc", "*addsi3_carry1_cconly",
"*addsi3_carry2_cc", "*addsi3_carry2_cconly"): New patterns.
("addhi3", "addqi3"): Remove, replace by ...
(ip2k_set_compare): Don't use lookup_const_double.
(asm_file_start): Initialization of commands_in_file removed.
(asm_file_end): Output of commands_in_file removed.
-
+
* config/ip2k/ip2k.c (CPP_PREDEFINES): Remove definition of
__INT_MAX__.
2002-08-12 Gabriel Dos Reis <gdr@nerim.net>
* diagnostic.h (output_formatted_scalar): Rename from
- output_formatted_integer.
+ output_formatted_integer.
* diagnostic.def: Add DK_DEBUG.
* diagnostic.c (output_decimal): Adjust.
(output_long_decimal): Likewise.
target_cpu_default="MASK_64BIT|MASK_FLOAT64|MASK_GAS"
tm_defines="MIPS_ISA_DEFAULT=64 MIPS_ABI_DEFAULT=ABI_MEABI"
;;
+mipsisa64sr71k-*-elf*)
+ tm_file="${tm_file} mips/elf.h"
+ tmake_file=mips/t-sr71k
+ target_cpu_default="MASK_64BIT|MASK_FLOAT64|MASK_GAS"
+ tm_defines="MIPS_ISA_DEFAULT=64 MIPS_CPU_STRING_DEFAULT=\\\"sr71000\\\" MIPS_ABI_DEFAULT=ABI_MEABI"
+ ;;
mipsisa64sb1-*-elf* | mipsisa64sb1el-*-elf*)
tm_file="${tm_file} mips/elf.h"
tmake_file=mips/t-elf
target_cpu_default="MASK_64BIT|MASK_FLOAT64|MASK_GAS"
tm_defines="MIPS_ISA_DEFAULT=3 MIPS_ABI_DEFAULT=ABI_O64"
;;
+mips64vr-*-elf* | mips64vrel-*-elf*)
+ tm_file="mips/vr.h ${tm_file} mips/elf64.h"
+ tm_defines="MIPS_ABI_DEFAULT=ABI_O64"
+ tmake_file=mips/t-vr
+ ;;
mips64orion-*-elf* | mips64orionel-*-elf*)
tm_file="${tm_file} mips/elforion.h mips/elf64.h"
tmake_file=mips/t-elf
--- /dev/null
+;; DFA-based pipeline description for 5400
+(define_automaton "vr54")
+(define_cpu_unit "vr54_dp0" "vr54")
+(define_cpu_unit "vr54_dp1" "vr54")
+(define_cpu_unit "vr54_mem" "vr54")
+(define_cpu_unit "vr54_mac" "vr54")
+
+;;
+;; The ordering of the instruction-execution-path/resource-usage
+;; descriptions (also known as reservation RTL) is roughly ordered
+;; based on the define attribute RTL for the "type" classification.
+;; When modifying, remember that the first test that matches is the
+;; reservation used!
+;;
+
+(define_insn_reservation "ir_vr54_unknown" 1
+ (and (eq_attr "cpu" "r5400")
+ (eq_attr "type" "unknown"))
+ "vr54_dp0+vr54_dp1+vr54_mem+vr54_mac")
+
+;; Assume prediction fails.
+(define_insn_reservation "ir_vr54_branch" 3
+ (and (eq_attr "cpu" "r5400")
+ (eq_attr "type" "branch,jump,call"))
+ "vr54_dp0|vr54_dp1")
+
+(define_insn_reservation "ir_vr54_load" 2
+ (and (eq_attr "cpu" "r5400")
+ (and (eq_attr "type" "load")
+ (eq_attr "mode" "!SF,DF,FPSW")))
+ "vr54_mem")
+
+(define_insn_reservation "ir_vr54_store" 1
+ (and (eq_attr "cpu" "r5400")
+ (and (eq_attr "type" "store")
+ (eq_attr "mode" "!SF,DF,FPSW")))
+ "vr54_mem")
+
+(define_insn_reservation "ir_vr54_fstore" 1
+ (and (eq_attr "cpu" "r5400")
+ (and (eq_attr "type" "store")
+ (eq_attr "mode" "SF,DF")))
+ "vr54_mem")
+
+
+;; This reservation is for conditional move based on integer
+;; or floating point CC. This could probably use some refinement
+;; as "move" type attr seems to be overloaded in rtl.
+(define_insn_reservation "ir_vr54_move" 4
+ (and (eq_attr "cpu" "r5400")
+ (eq_attr "type" "move"))
+ "vr54_dp0|vr54_dp1")
+
+;; Move to/from FPU registers
+(define_insn_reservation "ir_vr54_xfer" 2
+ (and (eq_attr "cpu" "r5400")
+ (eq_attr "type" "xfer"))
+ "vr54_dp0|vr54_dp1")
+
+(define_insn_reservation "ir_vr54_hilo" 1
+ (and (eq_attr "cpu" "r5400")
+ (eq_attr "type" "hilo"))
+ "vr54_dp0|vr54_dp1")
+
+(define_insn_reservation "ir_vr54_arith" 1
+ (and (eq_attr "cpu" "r5400")
+ (eq_attr "type" "arith,darith,icmp,nop"))
+ "vr54_dp0|vr54_dp1")
+
+(define_insn_reservation "ir_vr54_imul_si" 3
+ (and (eq_attr "cpu" "r5400")
+ (and (eq_attr "type" "imul")
+ (eq_attr "mode" "SI")))
+ "vr54_dp0|vr54_dp1")
+
+(define_insn_reservation "ir_vr54_imul_di" 4
+ (and (eq_attr "cpu" "r5400")
+ (and (eq_attr "type" "imul")
+ (eq_attr "mode" "DI")))
+ "vr54_dp0|vr54_dp1")
+
+(define_insn_reservation "ir_vr54_imadd_si" 3
+ (and (eq_attr "cpu" "r5400")
+ (eq_attr "type" "imul"))
+ "vr54_mac")
+
+(define_insn_reservation "ir_vr54_idiv_si" 42
+ (and (eq_attr "cpu" "r5400")
+ (and (eq_attr "type" "idiv")
+ (eq_attr "mode" "SI")))
+ "vr54_dp0|vr54_dp1")
+
+(define_insn_reservation "ir_vr54_idiv_di" 74
+ (and (eq_attr "cpu" "r5400")
+ (and (eq_attr "type" "idiv")
+ (eq_attr "mode" "DI")))
+ "vr54_dp0|vr54_dp1")
+
+(define_insn_reservation "ir_vr54_fadd" 4
+ (and (eq_attr "cpu" "r5400")
+ (eq_attr "type" "fadd"))
+ "vr54_dp0|vr54_dp1")
+
+(define_insn_reservation "ir_vr54_fmul_sf" 5
+ (and (eq_attr "cpu" "r5400")
+ (and (eq_attr "type" "fmul")
+ (eq_attr "mode" "SF")))
+ "vr54_dp0|vr54_dp1")
+
+(define_insn_reservation "ir_vr54_fmul_df" 6
+ (and (eq_attr "cpu" "r5400")
+ (and (eq_attr "type" "fmul")
+ (eq_attr "mode" "DF")))
+ "vr54_dp0|vr54_dp1")
+
+(define_insn_reservation "ir_vr54_fmadd_sf" 9
+ (and (eq_attr "cpu" "r5400")
+ (and (eq_attr "type" "fmadd")
+ (eq_attr "mode" "SF")))
+ "vr54_dp0|vr54_dp1")
+
+(define_insn_reservation "ir_vr54_fmadd_df" 10
+ (and (eq_attr "cpu" "r5400")
+ (and (eq_attr "type" "fmadd")
+ (eq_attr "mode" "DF")))
+ "vr54_dp0|vr54_dp1")
+
+(define_insn_reservation "ir_vr54_fdiv_sf" 42
+ (and (eq_attr "cpu" "r5400")
+ (and (eq_attr "type" "fdiv,fsqrt")
+ (eq_attr "mode" "SF")))
+ "vr54_dp0|vr54_dp1")
+
+(define_insn_reservation "ir_vr54_fdiv_df" 72
+ (and (eq_attr "cpu" "r5400")
+ (and (eq_attr "type" "fdiv,fsqrt")
+ (eq_attr "mode" "DF")))
+ "vr54_dp0|vr54_dp1")
+
+(define_insn_reservation "ir_vr54_fabs" 2
+ (and (eq_attr "cpu" "r5400")
+ (eq_attr "type" "fabs,fneg"))
+ "vr54_dp0|vr54_dp1")
+
+(define_insn_reservation "ir_vr54_fcmp" 2
+ (and (eq_attr "cpu" "r5400")
+ (eq_attr "type" "fcmp"))
+ "vr54_dp0|vr54_dp1")
+
+(define_insn_reservation "ir_vr54_fcvt" 6
+ (and (eq_attr "cpu" "r5400")
+ (eq_attr "type" "fcvt"))
+ "vr54_dp0|vr54_dp1")
+
+(define_insn_reservation "ir_vr54_frsqrt_sf" 61
+ (and (eq_attr "cpu" "r5400")
+ (and (eq_attr "type" "frsqrt")
+ (eq_attr "mode" "SF")))
+ "vr54_dp0|vr54_dp1")
+
+(define_insn_reservation "ir_vr54_frsqrt_df" 121
+ (and (eq_attr "cpu" "r5400")
+ (and (eq_attr "type" "frsqrt")
+ (eq_attr "mode" "DF")))
+ "vr54_dp0|vr54_dp1")
+
+(define_insn_reservation "ir_vr54_multi" 1
+ (and (eq_attr "cpu" "r5400")
+ (eq_attr "type" "multi"))
+ "vr54_dp0+vr54_dp1+vr54_mem+vr54_mac")
--- /dev/null
+;; DFA-based pipeline description for 5500
+(define_automaton "vr55")
+(define_cpu_unit "vr55_dp0" "vr55")
+(define_cpu_unit "vr55_dp1" "vr55")
+(define_cpu_unit "vr55_mem" "vr55")
+(define_cpu_unit "vr55_mac" "vr55")
+(define_cpu_unit "vr55_fp" "vr55")
+(define_cpu_unit "vr55_bru" "vr55")
+
+;;
+;; The ordering of the instruction-execution-path/resource-usage
+;; descriptions (also known as reservation RTL) is roughly ordered
+;; based on the define attribute RTL for the "type" classification.
+;; When modifying, remember that the first test that matches is the
+;; reservation used!
+;;
+
+(define_insn_reservation "ir_vr55_unknown" 1
+ (and (eq_attr "cpu" "r5500")
+ (eq_attr "type" "unknown"))
+ "vr55_dp0+vr55_dp1+vr55_mem+vr55_mac+vr55_fp+vr55_bru")
+
+;; Assume prediction fails.
+(define_insn_reservation "ir_vr55_branch" 2
+ (and (eq_attr "cpu" "r5500")
+ (eq_attr "type" "branch,jump,call"))
+ "vr55_bru")
+
+(define_insn_reservation "ir_vr55_load" 3
+ (and (eq_attr "cpu" "r5500")
+ (eq_attr "type" "load"))
+ "vr55_mem")
+
+(define_insn_reservation "ir_vr55_store" 1
+ (and (eq_attr "cpu" "r5500")
+ (eq_attr "type" "store"))
+ "vr55_mem")
+
+;; This reservation is for conditional move based on integer
+;; or floating point CC. This could probably use some refinement
+;; as "move" type attr seems to be overloaded in rtl.
+(define_insn_reservation "ir_vr55_move" 2
+ (and (eq_attr "cpu" "r5500")
+ (eq_attr "type" "move"))
+ "vr55_dp0|vr55_dp1")
+
+;; Move to/from FPU registers
+(define_insn_reservation "ir_vr55_xfer" 2
+ (and (eq_attr "cpu" "r5500")
+ (eq_attr "type" "xfer"))
+ "vr55_dp0|vr55_dp1")
+
+(define_insn_reservation "ir_vr55_hilo" 2
+ (and (eq_attr "cpu" "r5500")
+ (eq_attr "type" "hilo"))
+ "vr55_dp0|vr55_dp1")
+
+(define_insn_reservation "ir_vr55_arith" 1
+ (and (eq_attr "cpu" "r5500")
+ (eq_attr "type" "arith,darith,icmp,nop"))
+ "vr55_dp0|vr55_dp1")
+
+(define_insn_reservation "ir_vr55_imul_si" 3
+ (and (eq_attr "cpu" "r5500")
+ (and (eq_attr "type" "imul")
+ (eq_attr "mode" "SI")))
+ "vr55_mac")
+
+(define_insn_reservation "ir_vr55_imul_di" 4
+ (and (eq_attr "cpu" "r5500")
+ (and (eq_attr "type" "imul")
+ (eq_attr "mode" "DI")))
+ "vr55_mac")
+
+(define_insn_reservation "ir_vr55_imadd_si" 3
+ (and (eq_attr "cpu" "r5500")
+ (eq_attr "type" "imul"))
+ "vr55_mac")
+
+;; Divide algorithm is early out with best latency of 7 pcycles.
+;; Use worst case for scheduling purposes.
+(define_insn_reservation "ir_vr55_idiv_si" 42
+ (and (eq_attr "cpu" "r5500")
+ (and (eq_attr "type" "idiv")
+ (eq_attr "mode" "SI")))
+ "vr55_mac")
+
+(define_insn_reservation "ir_vr55_idiv_di" 74
+ (and (eq_attr "cpu" "r5500")
+ (and (eq_attr "type" "idiv")
+ (eq_attr "mode" "DI")))
+ "vr55_mac")
+
+(define_insn_reservation "ir_vr55_fadd" 4
+ (and (eq_attr "cpu" "r5500")
+ (eq_attr "type" "fadd"))
+ "vr55_fp")
+
+(define_insn_reservation "ir_vr55_fmul_sf" 5
+ (and (eq_attr "cpu" "r5500")
+ (and (eq_attr "type" "fmul")
+ (eq_attr "mode" "SF")))
+ "vr55_mac")
+
+(define_insn_reservation "ir_vr55_fmul_df" 6
+ (and (eq_attr "cpu" "r5500")
+ (and (eq_attr "type" "fmul")
+ (eq_attr "mode" "DF")))
+ "vr55_mac")
+
+(define_insn_reservation "ir_vr55_fmadd_sf" 9
+ (and (eq_attr "cpu" "r5500")
+ (and (eq_attr "type" "fmadd")
+ (eq_attr "mode" "SF")))
+ "vr55_mac")
+
+(define_insn_reservation "ir_vr55_fmadd_df" 10
+ (and (eq_attr "cpu" "r5500")
+ (and (eq_attr "type" "fmadd")
+ (eq_attr "mode" "DF")))
+ "vr55_mac")
+
+(define_insn_reservation "ir_vr55_fdiv_sf" 30
+ (and (eq_attr "cpu" "r5500")
+ (and (eq_attr "type" "fdiv,fsqrt")
+ (eq_attr "mode" "SF")))
+ "vr55_mac")
+
+(define_insn_reservation "ir_vr55_fdiv_df" 59
+ (and (eq_attr "cpu" "r5500")
+ (and (eq_attr "type" "fdiv,fsqrt")
+ (eq_attr "mode" "DF")))
+ "vr55_mac")
+
+(define_insn_reservation "ir_vr55_fabs" 2
+ (and (eq_attr "cpu" "r5500")
+ (eq_attr "type" "fabs,fneg"))
+ "vr55_fp")
+
+(define_insn_reservation "ir_vr55_fcmp" 2
+ (and (eq_attr "cpu" "r5500")
+ (eq_attr "type" "fcmp"))
+ "vr55_fp")
+
+(define_insn_reservation "ir_vr55_fcvt_sf" 4
+ (and (eq_attr "cpu" "r5500")
+ (and (eq_attr "type" "fcvt")
+ (eq_attr "mode" "SF")))
+ "vr55_fp")
+
+(define_insn_reservation "ir_vr55_fcvt_df" 6
+ (and (eq_attr "cpu" "r5500")
+ (and (eq_attr "type" "fcvt")
+ (eq_attr "mode" "DF")))
+ "vr55_fp")
+
+(define_insn_reservation "ir_vr55_frsqrt_sf" 60
+ (and (eq_attr "cpu" "r5500")
+ (and (eq_attr "type" "frsqrt")
+ (eq_attr "mode" "SF")))
+ "vr55_mac")
+
+(define_insn_reservation "ir_vr55_frsqrt_df" 118
+ (and (eq_attr "cpu" "r5500")
+ (and (eq_attr "type" "frsqrt")
+ (eq_attr "mode" "DF")))
+ "vr55_mac")
+
+(define_insn_reservation "ir_vr55_multi" 1
+ (and (eq_attr "cpu" "r5500")
+ (eq_attr "type" "multi"))
+ "vr55_dp0+vr55_dp1+vr55_mem+vr55_mac+vr55_fp+vr55_bru")
ATTRIBUTE_UNUSED;
static void mips_select_rtx_section PARAMS ((enum machine_mode, rtx,
unsigned HOST_WIDE_INT));
+static int mips_use_dfa_pipeline_interface PARAMS ((void));
static void mips_encode_section_info PARAMS ((tree, int));
/* Structure to be filled in by compute_frame_size with register
/* MIPS III */
{ "r4000", PROCESSOR_R4000, 3 },
{ "vr4100", PROCESSOR_R4100, 3 },
+ { "vr4111", PROCESSOR_R4111, 3 },
+ { "vr4121", PROCESSOR_R4121, 3 },
{ "vr4300", PROCESSOR_R4300, 3 },
+ { "vr4320", PROCESSOR_R4320, 3 },
{ "r4400", PROCESSOR_R4000, 3 }, /* = r4000 */
{ "r4600", PROCESSOR_R4600, 3 },
{ "orion", PROCESSOR_R4600, 3 }, /* = r4600 */
/* MIPS IV */
{ "r8000", PROCESSOR_R8000, 4 },
{ "vr5000", PROCESSOR_R5000, 4 },
+ { "vr5400", PROCESSOR_R5400, 4 },
+ { "vr5500", PROCESSOR_R5500, 4 },
+
/* MIPS 32 */
{ "4kc", PROCESSOR_R4KC, 32 },
/* MIPS 64 */
{ "5kc", PROCESSOR_R5KC, 64 },
{ "20kc", PROCESSOR_R20KC, 64 },
+ { "sr71000", PROCESSOR_SR71000, 64 },
/* Broadcom SB-1 CPU core */
{ "sb1", PROCESSOR_SB1, 64 },
#define TARGET_SCHED_ADJUST_COST mips_adjust_cost
#undef TARGET_SCHED_ISSUE_RATE
#define TARGET_SCHED_ISSUE_RATE mips_issue_rate
+#undef TARGET_SCHED_USE_DFA_PIPELINE_INTERFACE
+#define TARGET_SCHED_USE_DFA_PIPELINE_INTERFACE mips_use_dfa_pipeline_interface
#undef TARGET_ENCODE_SECTION_INFO
#define TARGET_ENCODE_SECTION_INFO mips_encode_section_info
}
/* ??? Fails because of a MIPS assembler bug? */
- else if (TARGET_64BIT && bytes >= 8 && ! TARGET_MIPS16)
+ else if (TARGET_64BIT && bytes >= 8
+ && ! TARGET_SR71K
+ && ! TARGET_MIPS16)
{
if (BYTES_BIG_ENDIAN)
{
bytes -= 4;
}
- else if (bytes >= 4 && ! TARGET_MIPS16)
+ else if (bytes >= 4
+ && ! TARGET_SR71K
+ && ! TARGET_MIPS16)
{
if (BYTES_BIG_ENDIAN)
{
{
switch (mips_tune)
{
- case PROCESSOR_R3000:
- return 1;
+ case PROCESSOR_R3000: return 1;
+ case PROCESSOR_R5400: return 2;
+ case PROCESSOR_R5500: return 2;
default:
return 1;
}
+/* Implements TARGET_SCHED_USE_DFA_PIPELINE_INTERFACE. Return true for
+ processors that have a DFA pipeline description. */
+
+static int
+mips_use_dfa_pipeline_interface ()
+{
+ switch (mips_tune)
+ {
+ case PROCESSOR_R5400:
+ case PROCESSOR_R5500:
+ case PROCESSOR_SR71000:
+ return true;
+
+ default:
+ return false;
+ }
+}
+
+
const char *
mips_emit_prefetch (operands)
rtx operands[];
PROCESSOR_R6000,
PROCESSOR_R4000,
PROCESSOR_R4100,
+ PROCESSOR_R4111,
+ PROCESSOR_R4121,
PROCESSOR_R4300,
+ PROCESSOR_R4320,
PROCESSOR_R4600,
PROCESSOR_R4650,
PROCESSOR_R5000,
+ PROCESSOR_R5400,
+ PROCESSOR_R5500,
PROCESSOR_R8000,
PROCESSOR_R4KC,
PROCESSOR_R5KC,
PROCESSOR_R20KC,
+ PROCESSOR_SR71000,
PROCESSOR_SB1
};
/* Architecture target defines. */
#define TARGET_MIPS3900 (mips_arch == PROCESSOR_R3900)
#define TARGET_MIPS4000 (mips_arch == PROCESSOR_R4000)
-#define TARGET_MIPS4100 (mips_arch == PROCESSOR_R4100)
+#define TARGET_MIPS4100 (mips_arch == PROCESSOR_R4100
+#define TARGET_MIPS4121 (mips_arch == PROCESSOR_R4121)
#define TARGET_MIPS4300 (mips_arch == PROCESSOR_R4300)
+#define TARGET_MIPS4320 (mips_arch == PROCESSOR_R4320)
#define TARGET_MIPS4KC (mips_arch == PROCESSOR_R4KC)
#define TARGET_MIPS5KC (mips_arch == PROCESSOR_R5KC)
+#define TARGET_MIPS5400 (mips_arch == PROCESSOR_R5400)
+#define TARGET_MIPS5500 (mips_arch == PROCESSOR_R5500)
#define TARGET_SB1 (mips_arch == PROCESSOR_SB1)
+#define TARGET_SR71K (mips_arch == PROCESSOR_SR71000)
/* Scheduling target defines. */
#define TUNE_MIPS3000 (mips_tune == PROCESSOR_R3000)
#define TUNE_MIPS3900 (mips_tune == PROCESSOR_R3900)
#define TUNE_MIPS4000 (mips_tune == PROCESSOR_R4000)
#define TUNE_MIPS5000 (mips_tune == PROCESSOR_R5000)
+#define TUNE_MIPS5400 (mips_tune == PROCESSOR_R5400)
+#define TUNE_MIPS5500 (mips_tune == PROCESSOR_R5500)
#define TUNE_MIPS6000 (mips_tune == PROCESSOR_R6000)
#define TUNE_SB1 (mips_tune == PROCESSOR_SB1)
+#define TUNE_SR71K (mips_tune == PROCESSOR_SR71000)
/* Define preprocessor macros for the -march and -mtune options.
PREFIX is either _MIPS_ARCH or _MIPS_TUNE, INFO is the selected
/* This is meant to be redefined in the host dependent files. */
#define SUBTARGET_TARGET_OPTIONS
-#define GENERATE_BRANCHLIKELY (TARGET_BRANCHLIKELY && !TARGET_MIPS16)
+#define GENERATE_BRANCHLIKELY (TARGET_BRANCHLIKELY \
+ && !TARGET_SR71K \
+ && !TARGET_MIPS16)
/* Generate three-operand multiply instructions for SImode. */
#define GENERATE_MULT3_SI ((TARGET_MIPS3900 \
+ || TARGET_MIPS4320 \
+ || TARGET_MIPS5400 \
+ || TARGET_MIPS5500 \
|| ISA_MIPS32 \
|| ISA_MIPS64) \
&& !TARGET_MIPS16)
/* ISA has branch likely instructions (eg. mips2). */
/* Disable branchlikely for tx39 until compare rewrite. They haven't
been generated up to this point. */
-#define ISA_HAS_BRANCHLIKELY (!ISA_MIPS1)
+#define ISA_HAS_BRANCHLIKELY (!ISA_MIPS1 \
+ && !TARGET_MIPS5500)
/* ISA has the conditional move instructions introduced in mips4. */
#define ISA_HAS_CONDMOVE ((ISA_MIPS4 \
|| ISA_MIPS32 \
|| ISA_MIPS64) \
+ && !TARGET_MIPS5500 \
&& !TARGET_MIPS16)
/* ISA has just the integer condition move instructions (movn,movz) */
/* ISA has floating-point nmadd and nmsub instructions. */
#define ISA_HAS_NMADD_NMSUB ((ISA_MIPS4 \
|| ISA_MIPS64) \
+ && (!TARGET_MIPS5400 || TARGET_MAD) \
&& ! TARGET_MIPS16)
/* ISA has count leading zeroes/ones instruction (not implemented). */
#define ISA_HAS_DCLZ_DCLO (ISA_MIPS64 \
&& !TARGET_MIPS16)
+/* ISA has three operand multiply instructions that put
+ the high part in an accumulator: mulhi or mulhiu. */
+#define ISA_HAS_MULHI (TARGET_MIPS5400 \
+ || TARGET_MIPS5500 \
+ || TARGET_SR71K \
+ )
+
+/* ISA has three operand multiply instructions that
+ negates the result and puts the result in an accumulator. */
+#define ISA_HAS_MULS (TARGET_MIPS5400 \
+ || TARGET_MIPS5500 \
+ || TARGET_SR71K \
+ )
+
+/* ISA has three operand multiply instructions that subtracts the
+ result from a 4th operand and puts the result in an accumulator. */
+#define ISA_HAS_MSAC (TARGET_MIPS5400 \
+ || TARGET_MIPS5500 \
+ || TARGET_SR71K \
+ )
+/* ISA has three operand multiply instructions that the result
+ from a 4th operand and puts the result in an accumulator. */
+#define ISA_HAS_MACC (TARGET_MIPS5400 \
+ || TARGET_MIPS5500 \
+ || TARGET_SR71K \
+ )
+
+/* ISA has 32-bit rotate right instruction. */
+#define ISA_HAS_ROTR_SI (TARGET_MIPS5400 \
+ || TARGET_MIPS5500 \
+ || TARGET_SR71K \
+ )
+
+/* ISA has 32-bit rotate right instruction. */
+#define ISA_HAS_ROTR_DI (TARGET_64BIT \
+ && (TARGET_MIPS5400 \
+ || TARGET_MIPS5500 \
+ || TARGET_SR71K \
+ ))
+
+
/* ISA has data prefetch instruction. */
#define ISA_HAS_PREFETCH ((ISA_MIPS4 \
|| ISA_MIPS32 \
|| TUNE_MIPS3900 \
|| TUNE_MIPS5000) \
return COSTS_N_INSNS (4); \
- else if (TUNE_MIPS6000) \
+ else if (TUNE_MIPS6000 \
+ || TUNE_MIPS5400 \
+ || TUNE_MIPS5500) \
return COSTS_N_INSNS (5); \
else \
return COSTS_N_INSNS (7); \
|| TUNE_MIPS3900 \
|| TUNE_MIPS5000) \
return COSTS_N_INSNS (5); \
- else if (TUNE_MIPS6000) \
+ else if (TUNE_MIPS6000 \
+ || TUNE_MIPS5400 \
+ || TUNE_MIPS5500) \
return COSTS_N_INSNS (6); \
else \
return COSTS_N_INSNS (8); \
return COSTS_N_INSNS (12); \
else if (TUNE_MIPS3900) \
return COSTS_N_INSNS (2); \
+ else if (TUNE_MIPS5400 || TUNE_MIPS5500) \
+ return COSTS_N_INSNS ((xmode == DImode) ? 4 : 3); \
else if (TUNE_MIPS6000) \
return COSTS_N_INSNS (17); \
else if (TUNE_MIPS5000) \
return COSTS_N_INSNS (12); \
else if (TUNE_MIPS6000) \
return COSTS_N_INSNS (15); \
+ else if (TUNE_MIPS5400 || TUNE_MIPS5500) \
+ return COSTS_N_INSNS (30); \
else \
return COSTS_N_INSNS (23); \
} \
if (TUNE_MIPS3000 \
|| TUNE_MIPS3900) \
return COSTS_N_INSNS (19); \
+ else if (TUNE_MIPS5400 || TUNE_MIPS5500) \
+ return COSTS_N_INSNS (59); \
else if (TUNE_MIPS6000) \
return COSTS_N_INSNS (16); \
else \
return COSTS_N_INSNS (38); \
else if (TUNE_MIPS5000) \
return COSTS_N_INSNS (36); \
+ else if (TUNE_MIPS5400 || TUNE_MIPS5500) \
+ return COSTS_N_INSNS ((GET_MODE (X) == SImode) ? 42 : 74); \
else \
return COSTS_N_INSNS (69); \
\
;; fcmp floating point compare
;; fcvt floating point convert
;; fsqrt floating point square root
+;; frsqrt floating point reciprocal square root
;; multi multiword sequence (or user asm statements)
;; nop no operation
(define_attr "type"
- "unknown,branch,jump,call,load,store,move,xfer,hilo,arith,darith,imul,imadd,idiv,icmp,fadd,fmul,fmadd,fdiv,fabs,fneg,fcmp,fcvt,fsqrt,multi,nop"
+ "unknown,branch,jump,call,load,store,move,xfer,hilo,arith,darith,imul,imadd,idiv,icmp,fadd,fmul,fmadd,fdiv,fabs,fneg,fcmp,fcvt,fsqrt,frsqrt,multi,nop"
(const_string "unknown"))
;; Main data type used by the insn
;; ??? Fix everything that tests this attribute.
(define_attr "cpu"
- "default,r3000,r3900,r6000,r4000,r4100,r4300,r4600,r4650,r5000,r8000,r4kc,r5kc,r20kc"
+ "default,r3000,r3900,r6000,r4000,r4100,r4121,r4300,r4320,r4600,r4650,r5000,r5400,r5500,r8000,sr71000,r4kc,r5kc,r20kc"
(const (symbol_ref "mips_cpu_attr")))
;; Does the instruction have a mandatory delay slot?
(define_function_unit "memory" 1 0
(and (eq_attr "type" "load")
- (eq_attr "cpu" "!r3000,r3900,r4600,r4650,r4100,r4300,r5000"))
+ (eq_attr "cpu" "!r3000,r3900,r4600,r4650,r4100,r4121,r4300,r4320,r5000"))
3 0)
(define_function_unit "memory" 1 0
(and (eq_attr "type" "load")
- (eq_attr "cpu" "r3000,r3900,r4600,r4650,r4100,r4300,r5000"))
+ (eq_attr "cpu" "r3000,r3900,r4600,r4650,r4100,r4121,r4300,r4320,r5000"))
2 0)
(define_function_unit "memory" 1 0 (eq_attr "type" "store") 1 0)
(define_function_unit "imuldiv" 1 0
(and (eq_attr "type" "imul,imadd")
- (eq_attr "cpu" "!r3000,r3900,r4000,r4600,r4650,r4100,r4300,r5000"))
+ (eq_attr "cpu" "!r3000,r3900,r4000,r4600,r4650,r4100,r4121,r4300,r4320,r5000"))
17 17)
;; On them mips16, we want to stronly discourage a mult from appearing
(define_function_unit "imuldiv" 1 0
(and (eq_attr "type" "imul,imadd")
- (and (eq_attr "mode" "SI") (eq_attr "cpu" "r4100")))
+ (and (eq_attr "mode" "SI") (eq_attr "cpu" "r4100,r4121")))
1 1)
(define_function_unit "imuldiv" 1 0
(and (eq_attr "type" "imul,imadd")
- (and (eq_attr "mode" "DI") (eq_attr "cpu" "r4100")))
+ (and (eq_attr "mode" "DI") (eq_attr "cpu" "r4100,r4121")))
4 4)
(define_function_unit "imuldiv" 1 0
(and (eq_attr "type" "imul,imadd")
- (and (eq_attr "mode" "SI") (eq_attr "cpu" "r4300,r5000")))
+ (and (eq_attr "mode" "SI") (eq_attr "cpu" "r4300,r4320,r5000")))
5 5)
(define_function_unit "imuldiv" 1 0
(and (eq_attr "type" "imul,imadd")
- (and (eq_attr "mode" "DI") (eq_attr "cpu" "r4300")))
+ (and (eq_attr "mode" "DI") (eq_attr "cpu" "r4300,r4320")))
8 8)
(define_function_unit "imuldiv" 1 0
(define_function_unit "imuldiv" 1 0
(and (eq_attr "type" "idiv")
- (eq_attr "cpu" "!r3000,r3900,r4000,r4600,r4650,r4100,r4300,r5000"))
+ (eq_attr "cpu" "!r3000,r3900,r4000,r4600,r4650,r4100,r4121,r4300,r4320,r5000"))
38 38)
(define_function_unit "imuldiv" 1 0
(define_function_unit "imuldiv" 1 0
(and (eq_attr "type" "idiv")
- (and (eq_attr "mode" "SI") (eq_attr "cpu" "r4100")))
+ (and (eq_attr "mode" "SI") (eq_attr "cpu" "r4100,r4121")))
35 35)
(define_function_unit "imuldiv" 1 0
(and (eq_attr "type" "idiv")
- (and (eq_attr "mode" "DI") (eq_attr "cpu" "r4100")))
+ (and (eq_attr "mode" "DI") (eq_attr "cpu" "r4100,r4121")))
67 67)
(define_function_unit "imuldiv" 1 0
(and (eq_attr "type" "idiv")
- (and (eq_attr "mode" "SI") (eq_attr "cpu" "r4300")))
+ (and (eq_attr "mode" "SI") (eq_attr "cpu" "r4300,r4320")))
37 37)
(define_function_unit "imuldiv" 1 0
(and (eq_attr "type" "idiv")
- (and (eq_attr "mode" "DI") (eq_attr "cpu" "r4300")))
+ (and (eq_attr "mode" "DI") (eq_attr "cpu" "r4300,r4320")))
69 69)
(define_function_unit "imuldiv" 1 0
;; instructions to be processed in the "imuldiv" unit.
(define_function_unit "adder" 1 1
- (and (eq_attr "type" "fcmp") (eq_attr "cpu" "!r3000,r3900,r6000,r4300,r5000"))
+ (and (eq_attr "type" "fcmp") (eq_attr "cpu" "!r3000,r3900,r6000,r4300,r4320,r5000"))
3 0)
(define_function_unit "adder" 1 1
1 0)
(define_function_unit "adder" 1 1
- (and (eq_attr "type" "fadd") (eq_attr "cpu" "!r3000,r3900,r6000,r4300"))
+ (and (eq_attr "type" "fadd") (eq_attr "cpu" "!r3000,r3900,r6000,r4300,r4320"))
4 0)
(define_function_unit "adder" 1 1
(define_function_unit "adder" 1 1
(and (eq_attr "type" "fabs,fneg")
- (eq_attr "cpu" "!r3000,r3900,r4600,r4650,r4300,r5000"))
+ (eq_attr "cpu" "!r3000,r3900,r4600,r4650,r4300,r4320,r5000"))
2 0)
(define_function_unit "adder" 1 1
(define_function_unit "mult" 1 1
(and (eq_attr "type" "fmul")
(and (eq_attr "mode" "SF")
- (eq_attr "cpu" "!r3000,r3900,r6000,r4600,r4650,r4300,r5000")))
+ (eq_attr "cpu" "!r3000,r3900,r6000,r4600,r4650,r4300,r4320,r5000")))
7 0)
(define_function_unit "mult" 1 1
(define_function_unit "mult" 1 1
(and (eq_attr "type" "fmul")
- (and (eq_attr "mode" "DF") (eq_attr "cpu" "!r3000,r3900,r6000,r4300,r5000")))
+ (and (eq_attr "mode" "DF") (eq_attr "cpu" "!r3000,r3900,r6000,r4300,r4320,r5000")))
8 0)
(define_function_unit "mult" 1 1
(define_function_unit "divide" 1 1
(and (eq_attr "type" "fdiv")
(and (eq_attr "mode" "SF")
- (eq_attr "cpu" "!r3000,r3900,r6000,r4600,r4650,r4300,r5000")))
+ (eq_attr "cpu" "!r3000,r3900,r6000,r4600,r4650,r4300,r4320,r5000")))
23 0)
(define_function_unit "divide" 1 1
(define_function_unit "divide" 1 1
(and (eq_attr "type" "fdiv")
(and (eq_attr "mode" "DF")
- (eq_attr "cpu" "!r3000,r3900,r6000,r4600,r4650,r4300")))
+ (eq_attr "cpu" "!r3000,r3900,r6000,r4600,r4650,r4300,r4320")))
36 0)
(define_function_unit "divide" 1 1
;;; ??? Is this number right?
(define_function_unit "divide" 1 1
- (and (eq_attr "type" "fsqrt")
- (and (eq_attr "mode" "SF") (eq_attr "cpu" "!r4600,r4650,r4300,r5000")))
+ (and (eq_attr "type" "fsqrt,frsqrt")
+ (and (eq_attr "mode" "SF") (eq_attr "cpu" "!r4600,r4650,r4300,r4320,r5000")))
54 0)
(define_function_unit "divide" 1 1
- (and (eq_attr "type" "fsqrt")
+ (and (eq_attr "type" "fsqrt,frsqrt")
(and (eq_attr "mode" "SF") (eq_attr "cpu" "r4600,r4650")))
31 0)
(define_function_unit "divide" 1 1
- (and (eq_attr "type" "fsqrt")
+ (and (eq_attr "type" "fsqrt,frsqrt")
(and (eq_attr "mode" "SF") (eq_attr "cpu" "r5000")))
21 0)
;;; ??? Is this number right?
(define_function_unit "divide" 1 1
- (and (eq_attr "type" "fsqrt")
- (and (eq_attr "mode" "DF") (eq_attr "cpu" "!r4600,r4650,r4300,r5000")))
+ (and (eq_attr "type" "fsqrt,frsqrt")
+ (and (eq_attr "mode" "DF") (eq_attr "cpu" "!r4600,r4650,r4300,r4320,r5000")))
112 0)
(define_function_unit "divide" 1 1
- (and (eq_attr "type" "fsqrt")
+ (and (eq_attr "type" "fsqrt,frsqrt")
(and (eq_attr "mode" "DF") (eq_attr "cpu" "r4600,r4650")))
60 0)
(define_function_unit "divide" 1 1
- (and (eq_attr "type" "fsqrt")
+ (and (eq_attr "type" "fsqrt,frsqrt")
(and (eq_attr "mode" "DF") (eq_attr "cpu" "r5000")))
36 0)
;; functional unit:
(define_function_unit "imuldiv" 1 0
- (and (eq_attr "type" "fadd") (eq_attr "cpu" "r4300"))
+ (and (eq_attr "type" "fadd") (eq_attr "cpu" "r4300,r4320"))
3 3)
(define_function_unit "imuldiv" 1 0
- (and (eq_attr "type" "fcmp,fabs,fneg") (eq_attr "cpu" "r4300"))
+ (and (eq_attr "type" "fcmp,fabs,fneg") (eq_attr "cpu" "r4300,r4320"))
1 1)
(define_function_unit "imuldiv" 1 0
- (and (eq_attr "type" "fmul") (and (eq_attr "mode" "SF") (eq_attr "cpu" "r4300")))
+ (and (eq_attr "type" "fmul") (and (eq_attr "mode" "SF") (eq_attr "cpu" "r4300,r4320")))
5 5)
(define_function_unit "imuldiv" 1 0
- (and (eq_attr "type" "fmul") (and (eq_attr "mode" "DF") (eq_attr "cpu" "r4300")))
+ (and (eq_attr "type" "fmul") (and (eq_attr "mode" "DF") (eq_attr "cpu" "r4300,r4320")))
8 8)
(define_function_unit "imuldiv" 1 0
- (and (and (eq_attr "type" "fdiv") (eq_attr "type" "fsqrt"))
- (and (eq_attr "mode" "SF") (eq_attr "cpu" "r4300")))
+ (and (and (eq_attr "type" "fdiv") (eq_attr "type" "fsqrt,frsqrt"))
+ (and (eq_attr "mode" "SF") (eq_attr "cpu" "r4300,r4320")))
29 29)
(define_function_unit "imuldiv" 1 0
- (and (and (eq_attr "type" "fdiv") (eq_attr "type" "fsqrt"))
- (and (eq_attr "mode" "DF") (eq_attr "cpu" "r4300")))
+ (and (and (eq_attr "type" "fdiv") (eq_attr "type" "fsqrt,frsqrt"))
+ (and (eq_attr "mode" "DF") (eq_attr "cpu" "r4300,r4320")))
58 58)
\f
;; The following functional units do not use the cpu type, and use
;; (define_function_unit "sqrt" 1 1 (and (eq_attr "type" "fsqrt") (eq_attr "mode" "SF")) 54 0)
;; (define_function_unit "sqrt" 1 1 (and (eq_attr "type" "fsqrt") (eq_attr "mode" "DF")) 112 0)
\f
+;; Include scheduling descriptions.
+
+(include "5400.md")
+(include "5500.md")
+(include "sr71k.md")
+
+
;;
;; ....................
;;
"TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
"
{
- if (!TARGET_MIPS4300)
+ if (!TARGET_MIPS4300
+ && !TARGET_MIPS4320)
emit_insn (gen_muldf3_internal (operands[0], operands[1], operands[2]));
else
emit_insn (gen_muldf3_r4300 (operands[0], operands[1], operands[2]));
[(set (match_operand:DF 0 "register_operand" "=f")
(mult:DF (match_operand:DF 1 "register_operand" "f")
(match_operand:DF 2 "register_operand" "f")))]
- "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT && !TARGET_MIPS4300"
+ "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT
+ && !TARGET_MIPS4300 &&!TARGET_MIPS4320"
"mul.d\\t%0,%1,%2"
[(set_attr "type" "fmul")
(set_attr "mode" "DF")])
[(set (match_operand:DF 0 "register_operand" "=f")
(mult:DF (match_operand:DF 1 "register_operand" "f")
(match_operand:DF 2 "register_operand" "f")))]
- "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT && TARGET_MIPS4300"
+ "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT
+ && (TARGET_MIPS4300 || TARGET_MIPS4320)"
"*
{
output_asm_insn (\"mul.d\\t%0,%1,%2\", operands);
"TARGET_HARD_FLOAT"
"
{
- if (!TARGET_MIPS4300)
+ if (!TARGET_MIPS4300 && !TARGET_MIPS4320)
emit_insn( gen_mulsf3_internal (operands[0], operands[1], operands[2]));
else
emit_insn( gen_mulsf3_r4300 (operands[0], operands[1], operands[2]));
[(set (match_operand:SF 0 "register_operand" "=f")
(mult:SF (match_operand:SF 1 "register_operand" "f")
(match_operand:SF 2 "register_operand" "f")))]
- "TARGET_HARD_FLOAT && !TARGET_MIPS4300"
+ "TARGET_HARD_FLOAT
+ && !TARGET_MIPS4300 && !TARGET_MIPS4320"
"mul.s\\t%0,%1,%2"
[(set_attr "type" "fmul")
(set_attr "mode" "SF")])
[(set (match_operand:SF 0 "register_operand" "=f")
(mult:SF (match_operand:SF 1 "register_operand" "f")
(match_operand:SF 2 "register_operand" "f")))]
- "TARGET_HARD_FLOAT && TARGET_MIPS4300"
+ "TARGET_HARD_FLOAT
+ && (TARGET_MIPS4300 || TARGET_MIPS4320)"
"*
{
output_asm_insn (\"mul.s\\t%0,%1,%2\", operands);
if (which_alternative == 1)
return \"mult\\t%1,%2\";
if (TARGET_MAD
+ || TARGET_MIPS5400
+ || TARGET_MIPS5500
+ || TARGET_MIPS4320
|| ISA_MIPS32
|| ISA_MIPS64)
return \"mul\\t%0,%1,%2\";
(clobber (match_scratch:SI 6 "=a,a,a"))
(clobber (match_scratch:SI 7 "=X,X,d"))]
"(TARGET_MIPS3900
+ || TARGET_MIPS4320
+ || TARGET_MIPS5400
+ || TARGET_MIPS5500
|| ISA_HAS_MADD_MSUB)
&& !TARGET_MIPS16"
"*
{
static const char *const madd[] = { \"madd\\t%1,%2\", \"madd\\t%0,%1,%2\" };
+ static const char *const macc[] = { \"macc\\t$0,%1,%2\", \"macc\\t%0,%1,%2\" };
if (which_alternative == 2)
return \"#\";
if (ISA_HAS_MADD_MSUB && which_alternative != 0)
return \"#\";
+
+ if (TARGET_MIPS5400)
+ return macc[which_alternative];
+
+ if (TARGET_MIPS5500)
+ {
+ if (which_alternative == 0)
+ return madd[0];
+ else
+ return macc[which_alternative];
+ }
+
+ if (TARGET_MIPS4320)
+ return macc[which_alternative];
+
return madd[which_alternative];
}"
[(set_attr "type" "imadd,imadd,multi")
(set (match_dup 0) (match_dup 1))]
"")
+(define_insn "*muls"
+ [(set (match_operand:SI 0 "register_operand" "=l,d")
+ (neg:SI (mult:SI (match_operand:SI 1 "register_operand" "d,d")
+ (match_operand:SI 2 "register_operand" "d,d"))))
+ (clobber (match_scratch:SI 3 "=h,h"))
+ (clobber (match_scratch:SI 4 "=a,a"))
+ (clobber (match_scratch:SI 5 "=X,l"))]
+ "ISA_HAS_MULS && TARGET_64BIT"
+ "@
+ muls\\t$0,%1,%2
+ muls\\t%0,%1,%2"
+ [(set_attr "type" "imul")
+ (set_attr "mode" "SI")])
+
+;; See comments above for mul_acc_si.
+(define_insn "*msac"
+ [(set (match_operand:SI 0 "register_operand" "=l,*d,*d")
+ (minus:SI (match_operand:SI 1 "register_operand" "0,l,*d")
+ (mult:SI (match_operand:SI 2 "register_operand" "d,d,d")
+ (match_operand:SI 3 "register_operand" "d,d,d"))))
+ (clobber (match_scratch:SI 4 "=h,h,h"))
+ (clobber (match_scratch:SI 5 "=X,1,l"))
+ (clobber (match_scratch:SI 6 "=a,a,a"))
+ (clobber (match_scratch:SI 7 "=X,X,d"))]
+ "ISA_HAS_MSAC && TARGET_64BIT"
+ "@
+ msac\\t$0,%2,%3
+ msac\\t%0,%2,%3
+ #"
+ [(set_attr "type" "imadd,imadd,multi")
+ (set_attr "mode" "SI")
+ (set_attr "length" "4,4,8")])
(define_split
[(set (match_operand:SI 0 "register_operand" "")
[(set_attr "type" "imul")
(set_attr "mode" "SI")])
+;; widening multiply with accumulator and/or negation
+;; These don't match yet for zero-extending; too complex for combine?
+;; Possible additions we should have:
+;; "=x" variants for when !TARGET_64BIT ?
+;; all-d alternatives with splits like pure SImode versions
+(define_insn "*muls_di"
+ [(set (match_operand:DI 0 "register_operand" "=a")
+ (neg:DI
+ (mult:DI (match_operator:DI 3 "extend_operator"
+ [(match_operand:SI 1 "register_operand" "d")])
+ (match_operator:DI 4 "extend_operator"
+ [(match_operand:SI 2 "register_operand" "d")]))))
+ (clobber (match_scratch:SI 5 "=h"))
+ (clobber (match_scratch:SI 6 "=l"))]
+ "TARGET_64BIT
+ && ISA_HAS_MULS
+ && GET_CODE (operands[3]) == GET_CODE (operands[4])"
+ "*
+{
+ if (GET_CODE (operands[3]) == SIGN_EXTEND)
+ return \"muls\\t$0,%1,%2\";
+ else
+ return \"mulsu\\t$0,%1,%2\";
+}"
+ [(set_attr "type" "imul")
+ (set_attr "length" "4")
+ (set_attr "mode" "SI")])
+
+(define_insn "*msac_di"
+ [(set (match_operand:DI 0 "register_operand" "=a")
+ (minus:DI (match_operand:DI 3 "register_operand" "0")
+ (mult:DI (match_operator:DI 4 "extend_operator"
+ [(match_operand:SI 1 "register_operand" "d")])
+ (match_operator:DI 5 "extend_operator"
+ [(match_operand:SI 2 "register_operand" "d")]))))
+ (clobber (match_scratch:SI 6 "=h"))
+ (clobber (match_scratch:SI 7 "=l"))]
+ "TARGET_64BIT
+ && ISA_HAS_MSAC
+ && GET_CODE (operands[4]) == GET_CODE (operands[5])"
+ "*
+{
+ if (GET_CODE (operands[4]) == SIGN_EXTEND)
+ {
+ if (TARGET_MIPS5500)
+ return \"msub\\t%1,%2\";
+ else
+ return \"msac\\t$0,%1,%2\";
+ }
+ else
+ {
+ if (TARGET_MIPS5500)
+ return \"msubu\\t%1,%2\";
+ else
+ return \"msacu\\t$0,%1,%2\";
+ }
+}"
+ [(set_attr "type" "imadd")
+ (set_attr "length" "4")
+ (set_attr "mode" "SI")])
+
;; _highpart patterns
(define_expand "smulsi3_highpart"
[(set (match_operand:SI 0 "register_operand" "=h")
#else
rtx (*genfn) ();
#endif
- genfn = gen_xmulsi3_highpart_internal;
+ if (ISA_HAS_MULHI && TARGET_64BIT)
+ genfn = gen_xmulsi3_highpart_mulhi;
+ else
+ genfn = gen_xmulsi3_highpart_internal;
emit_insn ((*genfn) (operands[0], operands[1], operands[2], dummy,
dummy, dummy2));
DONE;
#else
rtx (*genfn) ();
#endif
- genfn = gen_xmulsi3_highpart_internal;
+ if (ISA_HAS_MULHI && TARGET_64BIT)
+ genfn = gen_xmulsi3_highpart_mulhi;
+ else
+ genfn = gen_xmulsi3_highpart_internal;
emit_insn ((*genfn) (operands[0], operands[1], operands[2], dummy,
dummy, dummy2));
DONE;
[(set_attr "type" "imul")
(set_attr "mode" "SI")])
+(define_insn "xmulsi3_highpart_mulhi"
+ [(set (match_operand:SI 0 "register_operand" "=h,d")
+ (truncate:SI
+ (match_operator:DI 5 "highpart_shift_operator"
+ [(mult:DI (match_operator:DI 3 "extend_operator"
+ [(match_operand:SI 1 "register_operand" "d,d")])
+ (match_operator:DI 4 "extend_operator"
+ [(match_operand:SI 2 "register_operand" "d,d")]))
+ (const_int 32)])))
+ (clobber (match_scratch:SI 6 "=l,l"))
+ (clobber (match_scratch:SI 7 "=a,a"))
+ (clobber (match_scratch:SI 8 "=X,h"))]
+ "ISA_HAS_MULHI
+ && TARGET_64BIT
+ && GET_CODE (operands[3]) == GET_CODE (operands[4])"
+ "*
+{
+ static char const *const sign[] = { \"mult\\t%1,%2\", \"mulhi\\t%0,%1,%2\" };
+ static char const *const zero[] = { \"multu\\t%1,%2\", \"mulhiu\\t%0,%1,%2\" };
+ if (GET_CODE (operands[3]) == SIGN_EXTEND)
+ return sign[which_alternative];
+ else
+ return zero[which_alternative];
+}"
+ [(set_attr "type" "imul")
+ (set_attr "mode" "SI")
+ (set_attr "length" "4")])
+
+(define_insn "*xmulsi3_neg_highpart_mulhi"
+ [(set (match_operand:SI 0 "register_operand" "=h,d")
+ (truncate:SI
+ (match_operator:DI 5 "highpart_shift_operator"
+ [(neg:DI
+ (mult:DI (match_operator:DI 3 "extend_operator"
+ [(match_operand:SI 1 "register_operand" "d,d")])
+ (match_operator:DI 4 "extend_operator"
+ [(match_operand:SI 2 "register_operand" "d,d")])))
+ (const_int 32)])))
+ (clobber (match_scratch:SI 6 "=l,l"))
+ (clobber (match_scratch:SI 7 "=a,a"))
+ (clobber (match_scratch:SI 8 "=X,h"))]
+ "ISA_HAS_MULHI
+ && TARGET_64BIT
+ && GET_CODE (operands[3]) == GET_CODE (operands[4])"
+ "*
+{
+ static char const *const sign[] = { \"mulshi\\t$0,%1,%2\", \"mulshi\\t%0,%1,%2\" };
+ static char const *const zero[] = { \"mulshiu\\t$0,%1,%2\", \"mulshiu\\t%0,%1,%2\" };
+ if (GET_CODE (operands[3]) == SIGN_EXTEND)
+ return sign[which_alternative];
+ else
+ return zero[which_alternative];
+}"
+ [(set_attr "type" "imul")
+ (set_attr "mode" "SI")
+ (set_attr "length" "4")])
+
+
(define_insn "smuldi3_highpart"
[(set (match_operand:DI 0 "register_operand" "=h")
(truncate:DI
&& GET_CODE (operands[3]) == GET_CODE (operands[4])"
"*
{
- if (GET_CODE (operands[3]) == SIGN_EXTEND)
- return \"mad\\t%1,%2\";
+ if (TARGET_MAD)
+ {
+ if (GET_CODE (operands[3]) == SIGN_EXTEND)
+ return \"mad\\t%1,%2\";
+ else
+ return \"madu\\t%1,%2\";
+ }
+ else if (ISA_HAS_MACC)
+ {
+ if (GET_CODE (operands[3]) == SIGN_EXTEND)
+ {
+ if (TARGET_MIPS5500)
+ return \"madd\\t%1,%2\";
+ else
+ return \"macc\\t$0,%1,%2\";
+ }
+ else
+ {
+ if (TARGET_MIPS5500)
+ return \"maddu\\t%1,%2\";
+ else
+ return \"maccu\\t$0,%1,%2\";
+ }
+ }
else
- return \"madu\\t%1,%2\";
+ abort ();
+
}"
[(set_attr "type" "imadd")
(set_attr "mode" "SI")])
(sqrt:DF (match_operand:DF 2 "register_operand" "f"))))]
"ISA_HAS_FP4 && TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT && flag_unsafe_math_optimizations"
"rsqrt.d\\t%0,%2"
- [(set_attr "type" "fsqrt")
+ [(set_attr "type" "frsqrt")
(set_attr "mode" "DF")])
(define_insn ""
(sqrt:SF (match_operand:SF 2 "register_operand" "f"))))]
"ISA_HAS_FP4 && TARGET_HARD_FLOAT && flag_unsafe_math_optimizations"
"rsqrt.s\\t%0,%2"
- [(set_attr "type" "fsqrt")
+ [(set_attr "type" "frsqrt")
(set_attr "mode" "SF")])
\f
(const_int 4)
(const_int 8))])])
+(define_insn "rotrsi3"
+ [(set (match_operand:SI 0 "register_operand" "=d")
+ (rotatert:SI (match_operand:SI 1 "register_operand" "d")
+ (match_operand:SI 2 "arith_operand" "dn")))]
+ "ISA_HAS_ROTR_SI"
+ "*
+{
+ if (TARGET_SR71K && GET_CODE (operands[2]) != CONST_INT)
+ return \"rorv\\t%0,%1,%2\";
+
+ if ((GET_CODE (operands[2]) == CONST_INT)
+ && (INTVAL (operands[2]) < 0 || INTVAL (operands[2]) >= 32))
+ abort ();
+
+ return \"ror\\t%0,%1,%2\";
+}"
+ [(set_attr "type" "arith")
+ (set_attr "mode" "SI")])
+
+(define_insn "rotrdi3"
+ [(set (match_operand:DI 0 "register_operand" "=d")
+ (rotatert:DI (match_operand:DI 1 "register_operand" "d")
+ (match_operand:DI 2 "arith_operand" "dn")))]
+ "ISA_HAS_ROTR_DI"
+ "*
+{
+ if (TARGET_SR71K)
+ {
+ if (GET_CODE (operands[2]) != CONST_INT)
+ return \"drorv\\t%0,%1,%2\";
+
+ if (INTVAL (operands[2]) >= 32 && INTVAL (operands[2]) <= 63)
+ return \"dror32\\t%0,%1,%2\";
+ }
+
+ if ((GET_CODE (operands[2]) == CONST_INT)
+ && (INTVAL (operands[2]) < 0 || INTVAL (operands[2]) >= 64))
+ abort ();
+
+ return \"dror\\t%0,%1,%2\";
+}"
+ [(set_attr "type" "arith")
+ (set_attr "mode" "DI")])
+
+
;; On the mips16, we can split a 4 byte shift into 2 2 byte shifts.
(define_split
--- /dev/null
+;; .........................
+;;
+;; DFA-based pipeline description for Sandcraft SR3 (MIPS64 based)
+;;
+;; The SR3 is describeds as:
+;; - nine-stage pipeline, insn buffering with out-of-order issue to
+;; multiple function units, with a average dispatch rate of 2
+;; insn.s per cycle (max 6 insns: 2 fpu, 4 cpu).
+;;
+;; The details on this are scant except for a diagram in
+;; Chap. 6 of Rev. 1.0 SR3 Spec.
+;;
+;; The model employed below is designed to closely approximate the
+;; published latencies. Emulation of out-of-order issue and the insn
+;; buffering is done via a VLIW dispatch style (with a packing of 6 insns);
+;; the function unit reservations restrictions (define_*_set) are
+;; contrived to support published timings.
+;;
+;; Reference:
+;; "SR3 Microporocessor Specification, System development information,"
+;; Revision 1.0, 13 December 2000.
+;;
+;;
+;; Reservation model is based on:
+;; 1) Figure 6-1, from the 1.0 specicification.
+;; 2) Chapter 19, from the 1.0 specificication.
+;; 3) following questions(Red Hat)/answers(Sandcraft):
+;; RH> From Section 19.1
+;; RH> 1) In terms of figure 6-1, are all the instructions in
+;; RH> table 19-1 restricted
+;; RH> to ALUx? When ALUx is not in use for an instruction in table;; RH> 19-1 is
+;; RH> it fully compatible with all insns that issue to ALUy?
+;;
+;; Yes, all the instructions in Table 19-1 only go to ALUX, and all the
+;; instructions that can be issued to ALUY can also be issued to ALUX.
+;;
+;;
+;; RH> From Section 19.2
+;; RH> 2) Explain conditional moves execution path (in terms of
+;; RH> figure 6-1)
+;;
+;; Conditional move of integer registers (based on floating point condition
+;; codes or integer register value) go to ALUX or ALUY.
+;;
+;; RH> 3) Explain floating point store execution path (in terms of
+;; RH> figure 6-1)
+;;
+;; Floating point stores go to Ld/St and go to MOV in the floating point
+;; pipeline.
+;;
+;; Floating point loads go to Ld/St and go to LOAD in the floating point
+;; pipeline.
+;;
+;; RH> 4) Explain branch on floating condition (in terms of figure 6-1);;
+;; Branch on floating condition go to BRU.
+;;
+;; RH> 5) Is the column for single RECIP instruction latency correct?
+;; RH> What about for RSQRT single and double?
+;;
+;; The latency/repeat for RECIP and RSQRT are correct.
+;;
+
+;;
+;; Use four automata to isolate long latency operations, and to
+;; reduce the complexity of cpu+fpu, reducing space.
+;;
+(define_automaton "sr71_cpu, sr71_cpu1, sr71_cp1, sr71_cp2, sr71_fextra, sr71_imacc")
+
+;; feeders for CPU function units and feeders for fpu (CP1 interface)
+(define_cpu_unit "sr_iss0,sr_iss1,sr_iss2,sr_iss3,sr_iss4,sr_iss5" "sr71_cpu")
+
+;; CPU function units
+(define_cpu_unit "ipu_bru" "sr71_cpu1")
+(define_cpu_unit "ipu_alux" "sr71_cpu1")
+(define_cpu_unit "ipu_aluy" "sr71_cpu1")
+(define_cpu_unit "ipu_ldst" "sr71_cpu1")
+(define_cpu_unit "ipu_macc_iter" "sr71_imacc")
+
+
+;; Floating-point unit (Co-processor interface 1).
+(define_cpu_unit "fpu_mov" "sr71_cp1")
+(define_cpu_unit "fpu_load" "sr71_cp1")
+(define_cpu_unit "fpu_fpu" "sr71_cp2")
+
+;; fictitous unit to track long float insns with separate automaton
+(define_cpu_unit "fpu_iter" "sr71_fextra")
+
+
+;;
+;; Define common execution path (reservation) combinations
+;;
+
+;;
+(define_reservation "cpu_iss" "sr_iss0|sr_iss1|sr_iss2|sr_iss3")
+
+;; two cycles are used for instruction using the fpu as it runs
+;; at half the clock speed of the cpu. By adding an extra cycle
+;; to the issue units, the default/minimum "repeat" dispatch delay is
+;; accounted for all insn.s
+(define_reservation "cp1_iss" "(sr_iss4*2)|(sr_iss5*2)")
+
+(define_reservation "serial_dispatch" "sr_iss0+sr_iss1+sr_iss2+sr_iss3+sr_iss4+sr_iss5")
+
+;; Simulate a 6 insn VLIW dispatch, 1 cycle in dispatch followed by
+;; reservation of function unit.
+(define_reservation "ri_insns" "cpu_iss,(ipu_alux|ipu_aluy)")
+(define_reservation "ri_mem" "cpu_iss,ipu_ldst")
+(define_reservation "ri_alux" "cpu_iss,ipu_alux")
+(define_reservation "ri_branch" "cpu_iss,ipu_bru")
+
+(define_reservation "rf_insn" "cp1_iss,fpu_fpu")
+(define_reservation "rf_ldmem" "cp1_iss,fpu_load")
+
+; simultaneous reservation of pseudo-unit keeps cp1 fpu tied
+; up until long cycle insn is finished...
+(define_reservation "rf_multi1" "rf_insn+fpu_iter")
+
+;;
+;; The ordering of the instruction-execution-path/resource-usage
+;; descriptions (also known as reservation RTL) is roughly ordered
+;; based on the define attribute RTL for the "type" classification.
+;; When modifying, remember that the first test that matches is the
+;; reservation used!
+;;
+
+
+(define_insn_reservation "ir_sr70_unknown"
+ 1
+ (and (eq_attr "cpu" "sr71000")
+ (eq_attr "type" "unknown"))
+ "serial_dispatch")
+
+
+;; Assume prediction fails.
+(define_insn_reservation "ir_sr70_branch"
+ 6
+ (and (eq_attr "cpu" "sr71000")
+ (eq_attr "type" "branch,jump,call"))
+ "ri_branch")
+
+(define_insn_reservation "ir_sr70_load"
+ 2
+ (and (eq_attr "cpu" "sr71000")
+ (and (eq_attr "type" "load")
+ (eq_attr "mode" "!SF,DF,FPSW")))
+ "ri_mem")
+
+(define_insn_reservation "ir_sr70_store"
+ 1
+ (and (eq_attr "cpu" "sr71000")
+ (and (eq_attr "type" "store")
+ (eq_attr "mode" "!SF,DF,FPSW")))
+ "ri_mem")
+
+
+;;
+;; float loads/stores flow through both cpu and cp1...
+;;
+(define_insn_reservation "ir_sr70_fload"
+ 9
+ (and (eq_attr "cpu" "sr71000")
+ (and (eq_attr "type" "load")
+ (eq_attr "mode" "SF,DF")))
+ "(cpu_iss+cp1_iss),(ri_mem+rf_ldmem)")
+
+(define_insn_reservation "ir_sr70_fstore"
+ 1
+ (and (eq_attr "cpu" "sr71000")
+ (and (eq_attr "type" "store")
+ (eq_attr "mode" "SF,DF")))
+ "(cpu_iss+cp1_iss),(fpu_mov+ri_mem)")
+
+
+;; This reservation is for conditional move based on integer
+;; or floating point CC. This could probably use some refinement
+;; as "move" type attr seems to be overloaded in rtl.
+(define_insn_reservation "ir_sr70_move"
+ 4
+ (and (eq_attr "cpu" "sr71000")
+ (eq_attr "type" "move"))
+ "ri_insns")
+
+;; Try to discriminate move-from-cp1 versus move-to-cp1 as latencies
+;; are different. Like float load/store, these insns use multiple
+;; resources simultaneously
+(define_insn_reservation "ir_sr70_xfer_from"
+ 6
+ (and (eq_attr "cpu" "sr71000")
+ (and (eq_attr "type" "xfer")
+ (eq_attr "mode" "!SF,DF,FPSW")))
+ "(cpu_iss+cp1_iss),(fpu_mov+ri_mem)")
+
+(define_insn_reservation "ir_sr70_xfer_to"
+ 9
+ (and (eq_attr "cpu" "sr71000")
+ (and (eq_attr "type" "xfer")
+ (eq_attr "mode" "SF,DF")))
+ "(cpu_iss+cp1_iss),(ri_mem+rf_ldmem)")
+
+(define_insn_reservation "ir_sr70_hilo"
+ 1
+ (and (eq_attr "cpu" "sr71000")
+ (eq_attr "type" "hilo"))
+ "ri_insns")
+
+(define_insn_reservation "ir_sr70_arith"
+ 1
+ (and (eq_attr "cpu" "sr71000")
+ (eq_attr "type" "arith,darith"))
+ "ri_insns")
+
+;; emulate repeat (dispatch stall) by spending extra cycle(s) in
+;; in iter unit
+(define_insn_reservation "ir_sr70_imul_si"
+ 4
+ (and (eq_attr "cpu" "sr71000")
+ (and (eq_attr "type" "imul,imadd")
+ (eq_attr "mode" "SI")))
+ "ri_alux,ipu_alux,ipu_macc_iter")
+
+(define_insn_reservation "ir_sr70_imul_di"
+ 6
+ (and (eq_attr "cpu" "sr71000")
+ (and (eq_attr "type" "imul,imadd")
+ (eq_attr "mode" "DI")))
+ "ri_alux,ipu_alux,(ipu_macc_iter*3)")
+
+;; Divide algorithm is early out with best latency of 7 pcycles.
+;; Use worst case for scheduling purposes.
+(define_insn_reservation "ir_sr70_idiv_si"
+ 41
+ (and (eq_attr "cpu" "sr71000")
+ (and (eq_attr "type" "idiv")
+ (eq_attr "mode" "SI")))
+ "ri_alux,ipu_alux,(ipu_macc_iter*38)")
+
+(define_insn_reservation "ir_sr70_idiv_di"
+ 73
+ (and (eq_attr "cpu" "sr71000")
+ (and (eq_attr "type" "idiv")
+ (eq_attr "mode" "DI")))
+ "ri_alux,ipu_alux,(ipu_macc_iter*70)")
+
+(define_insn_reservation "ir_sr70_icmp"
+ 1
+ (and (eq_attr "cpu" "sr71000")
+ (eq_attr "type" "icmp"))
+ "ri_insns")
+
+;; extra reservations of fpu_fpu are for repeat latency
+(define_insn_reservation "ir_sr70_fadd_sf"
+ 8
+ (and (eq_attr "cpu" "sr71000")
+ (and (eq_attr "type" "fadd")
+ (eq_attr "mode" "SF")))
+ "rf_insn,fpu_fpu")
+
+(define_insn_reservation "ir_sr70_fadd_df"
+ 10
+ (and (eq_attr "cpu" "sr71000")
+ (and (eq_attr "type" "fadd")
+ (eq_attr "mode" "DF")))
+ "rf_insn,fpu_fpu")
+
+;; Latencies for MADD,MSUB, NMADD, NMSUB assume the Multiply is fused
+;; with the sub or add.
+(define_insn_reservation "ir_sr70_fmul_sf"
+ 8
+ (and (eq_attr "cpu" "sr71000")
+ (and (eq_attr "type" "fmul,fmadd")
+ (eq_attr "mode" "SF")))
+ "rf_insn,fpu_fpu")
+
+;; tie up the fpu unit to emulate the balance for the "repeat
+;; rate" of 8 (2 are spent in the iss unit)
+(define_insn_reservation "ir_sr70_fmul_df"
+ 16
+ (and (eq_attr "cpu" "sr71000")
+ (and (eq_attr "type" "fmul,fmadd")
+ (eq_attr "mode" "DF")))
+ "rf_insn,fpu_fpu*6")
+
+
+;; RECIP insn uses same type attr as div, and for SR3, has same
+;; timings for double. However, single RECIP has a latency of
+;; 28 -- only way to fix this is to introduce new insn attrs.
+;; cycles spent in iter unit are designed to satisfy balance
+;; of "repeat" latency after insn uses up rf_multi1 reservation
+(define_insn_reservation "ir_sr70_fdiv_sf"
+ 60
+ (and (eq_attr "cpu" "sr71000")
+ (and (eq_attr "type" "fdiv")
+ (eq_attr "mode" "SF")))
+ "rf_multi1+(fpu_iter*51)")
+
+(define_insn_reservation "ir_sr70_fdiv_df"
+ 120
+ (and (eq_attr "cpu" "sr71000")
+ (and (eq_attr "type" "fdiv")
+ (eq_attr "mode" "DF")))
+ "rf_multi1+(fpu_iter*109)")
+
+(define_insn_reservation "ir_sr70_fabs"
+ 4
+ (and (eq_attr "cpu" "sr71000")
+ (eq_attr "type" "fabs,fneg"))
+ "rf_insn,fpu_fpu")
+
+(define_insn_reservation "ir_sr70_fcmp"
+ 10
+ (and (eq_attr "cpu" "sr71000")
+ (eq_attr "type" "fcmp"))
+ "rf_insn,fpu_fpu")
+
+;; "fcvt" type attribute covers a number of diff insns, most have the same
+;; latency descriptions, a few vary. We use the
+;; most common timing (which is also worst case).
+(define_insn_reservation "ir_sr70_fcvt"
+ 12
+ (and (eq_attr "cpu" "sr71000")
+ (eq_attr "type" "fcvt"))
+ "rf_insn,fpu_fpu*4")
+
+(define_insn_reservation "ir_sr70_fsqrt_sf"
+ 62
+ (and (eq_attr "cpu" "sr71000")
+ (and (eq_attr "type" "fsqrt")
+ (eq_attr "mode" "SF")))
+ "rf_multi1+(fpu_iter*53)")
+
+(define_insn_reservation "ir_sr70_fsqrt_df"
+ 122
+ (and (eq_attr "cpu" "sr71000")
+ (and (eq_attr "type" "fsqrt")
+ (eq_attr "mode" "DF")))
+ "rf_multi1+(fpu_iter*111)")
+
+(define_insn_reservation "ir_sr70_frsqrt_sf"
+ 48
+ (and (eq_attr "cpu" "sr71000")
+ (and (eq_attr "type" "frsqrt")
+ (eq_attr "mode" "SF")))
+ "rf_multi1+(fpu_iter*39)")
+
+(define_insn_reservation "ir_sr70_frsqrt_df"
+ 240
+ (and (eq_attr "cpu" "sr71000")
+ (and (eq_attr "type" "frsqrt")
+ (eq_attr "mode" "DF")))
+ "rf_multi1+(fpu_iter*229)")
+
+(define_insn_reservation "ir_sr70_multi"
+ 1
+ (and (eq_attr "cpu" "sr71000")
+ (eq_attr "type" "multi"))
+ "serial_dispatch")
+
+(define_insn_reservation "ir_sr70_nop"
+ 1
+ (and (eq_attr "cpu" "sr71000")
+ (eq_attr "type" "nop"))
+ "ri_insns")
--- /dev/null
+CONFIG2_H = $(srcdir)/config/mips/elf.h $(srcdir)/config/mips/mips.h
+
+# Suppress building libgcc1.a, since the MIPS compiler port is complete
+# and does not need anything from libgcc1.a.
+LIBGCC1 =
+CROSS_LIBGCC1 =
+
+EXTRA_MULTILIB_PARTS = crtbegin.o crtend.o crti.o crtn.o
+# Don't let CTOR_LIST end up in sdata section.
+CRTSTUFF_T_CFLAGS = -G 0
+
+# Assemble startup files.
+$(T)crti.o: $(srcdir)/config/mips/crti.asm $(GCC_PASSES)
+ $(GCC_FOR_TARGET) $(GCC_CFLAGS) $(MULTILIB_CFLAGS) $(INCLUDES) \
+ -c -o $(T)crti.o -x assembler-with-cpp $(srcdir)/config/mips/crti.asm
+
+$(T)crtn.o: $(srcdir)/config/mips/crtn.asm $(GCC_PASSES)
+ $(GCC_FOR_TARGET) $(GCC_CFLAGS) $(MULTILIB_CFLAGS) $(INCLUDES) \
+ -c -o $(T)crtn.o -x assembler-with-cpp $(srcdir)/config/mips/crtn.asm
+
+# We must build libgcc2.a with -G 0, in case the user wants to link
+# without the $gp register.
+TARGET_LIBGCC2_CFLAGS = -G 0
+
+# fp-bit and dp-bit are really part of libgcc1, but this will cause
+# them to be built correctly, so... [taken from t-sparclite]
+# We want fine grained libraries, so use the new code to build the
+# floating point emulation libraries.
+FPBIT = fp-bit.c
+DPBIT = dp-bit.c
+
+dp-bit.c: $(srcdir)/config/fp-bit.c
+ echo '#ifdef __MIPSEL__' > dp-bit.c
+ echo '#define FLOAT_BIT_ORDER_MISMATCH' >> dp-bit.c
+ echo '#endif' >> dp-bit.c
+ echo '#define US_SOFTWARE_GOFAST' >> dp-bit.c
+ cat $(srcdir)/config/fp-bit.c >> dp-bit.c
+
+fp-bit.c: $(srcdir)/config/fp-bit.c
+ echo '#define FLOAT' > fp-bit.c
+ echo '#ifdef __MIPSEL__' >> fp-bit.c
+ echo '#define FLOAT_BIT_ORDER_MISMATCH' >> fp-bit.c
+ echo '#endif' >> fp-bit.c
+ echo '#define US_SOFTWARE_GOFAST' >> fp-bit.c
+ cat $(srcdir)/config/fp-bit.c >> fp-bit.c
+
+# Build the libraries for both hard and soft floating point
+
+MULTILIB_OPTIONS = EL/EB msoft-float mips2
+MULTILIB_DIRNAMES = el eb soft-float mips2
+
+LIBGCC = stmp-multilib
+INSTALL_LIBGCC = install-multilib
+
+# Add additional dependencies to recompile selected modules whenever the
+# tm.h file changes. The files compiled are:
+#
+# gcc.c (*_SPEC changes)
+# toplev.c (new switches + assembly output changes)
+# sdbout.c (debug format changes)
+# dbxout.c (debug format changes)
+# dwarfout.c (debug format changes)
+# final.c (assembly output changes)
+# varasm.c (assembly output changes)
+# cse.c (cost functions)
+# insn-output.c (possible ifdef changes in tm.h)
+# regclass.c (fixed/call used register changes)
+# cccp.c (new preprocessor macros, -v version #)
+# explow.c (GO_IF_LEGITIMATE_ADDRESS)
+# recog.c (GO_IF_LEGITIMATE_ADDRESS)
+# reload.c (GO_IF_LEGITIMATE_ADDRESS)
+
+gcc.o: $(CONFIG2_H)
+toplev.o: $(CONFIG2_H)
+sdbout.o: $(CONFIG2_H)
+dbxout.o: $(CONFIG2_H)
+dwarfout.o: $(CONFIG2_H)
+final.o: $(CONFIG2_H)
+varasm.o: $(CONFIG2_H)
+cse.o: $(CONFIG2_H)
+insn-output.o: $(CONFIG2_H)
+regclass.o: $(CONFIG2_H)
+cccp.o: $(CONFIG2_H)
+explow.o: $(CONFIG2_H)
+recog.o: $(CONFIG2_H)
+reload.o: $(CONFIG2_H)
--- /dev/null
+# BEGIN boiler-plate MIPS stuff
+
+# Don't let CTOR_LIST end up in sdata section.
+CRTSTUFF_T_CFLAGS = -G 0
+
+# We must build libgcc2.a with -G 0, in case the user wants to link
+# without the $gp register.
+TARGET_LIBGCC2_CFLAGS = -G 0
+
+LIB2FUNCS_EXTRA = $(srcdir)/config/mips/mips16.S
+EXTRA_MULTILIB_PARTS = crtbegin.o crtend.o crti.o crtn.o
+
+# Assemble startup files.
+$(T)crti.o: $(srcdir)/config/mips/crti.asm $(GCC_PASSES)
+ $(GCC_FOR_TARGET) $(GCC_CFLAGS) $(MULTILIB_CFLAGS) $(INCLUDES) \
+ -c -o $(T)crti.o -x assembler-with-cpp $(srcdir)/config/mips/crti.asm
+
+$(T)crtn.o: $(srcdir)/config/mips/crtn.asm $(GCC_PASSES)
+ $(GCC_FOR_TARGET) $(GCC_CFLAGS) $(MULTILIB_CFLAGS) $(INCLUDES) \
+ -c -o $(T)crtn.o -x assembler-with-cpp $(srcdir)/config/mips/crtn.asm
+
+# END boiler-plate
+
+# Endianness: EB or EL
+#
+# ABIs: mabi=32
+# mabi=o64
+# mabi=eabi
+# meabi=eabi/mlong32
+# mabi=eabi/mgp32
+# mabi=eabi/mgp32/mlong64
+#
+# Architecture: march=vr5400
+# march=vr4100
+# march=vr4100/mips16
+#
+# Total: 2 * 6 * 3 = 36 multilibs.
+MULTILIB_OPTIONS = \
+ EL/EB \
+ mabi=32/mabi=o64/mabi=eabi \
+ mgp32 \
+ mlong32/mlong64 \
+ mips16 \
+ march=vr5400/march=vr4100
+
+MULTILIB_DIRNAMES = \
+ el eb \
+ o32 o64 eabi \
+ gp32 \
+ long32 long64 \
+ mips16 \
+ vr5400 vr4100
+
+MULTILIB_MATCHES = EL=mel EB=meb
+
+# Assume a 4000-series is the default: we'd need a *mips16 entry if
+# the default processor didn't support mips16. Also assume o64,
+# which means we need to extend the o64 exceptions to combinations
+# without a -mabi flag.
+MULTILIB_EXCEPTIONS = \
+ *mabi=32/mlong64* \
+ *mabi=32/mgp32/mlong64* \
+ *mabi=o64/mgp32* \
+ *mabi=o64/mlong64* \
+ mgp32* E[LB]/mgp32* \
+ mlong64* E[LB]/mlong64* \
+ *mips16/march=vr5*
+
+# The real value of this macro is very long, so generate it using a
+# shell fragment. The idea is to tell the GCC driver how -mabi,
+# -mgp32, -mlong32 and -mlong64 interact, so that it choses the right
+# library when some options are specified redundantly (for example,
+# -mabi=32 -mgp32).
+
+# The core equalities are listed after "for changes in ". The first
+# entry assumes o64 is the default ABI.
+MULTILIB_REDUNDANT_DIRS=` \
+ for endian in '' 'el' 'eb'; do \
+ for arch in '' 'vr5400' 'vr4100' \
+ 'mips16' 'mips16/vr100'; do \
+ for changes in long32= \
+ o32/gp32=o32 \
+ o32/gp32/long32=o32 \
+ o32/long32=o32 \
+ o64/long32=o64 \
+ eabi/gp32/long32=eabi/gp32 \
+ eabi/long64=eabi; do \
+ from=\`echo \$${changes} | sed 's/=.*//'\`; \
+ to=\`echo \$${changes} | sed 's/.*=//'\`; \
+ echo \$$endian \$$from \$$arch=\$$endian \$$to \$$arch \
+ | sed -e 's: *= *:=:' \
+ -e 's: *:/:g' \
+ -e 's:=$$:=.:'; \
+ done; \
+ done; \
+ done`
--- /dev/null
+/* Definitions of target machine for GNU compiler.
+ NEC VR Series Processors
+ Copyright (c) 2002 Free Software Foundation, Inc.
+ Contributed by Red Hat, Inc.
+
+This file is part of GNU CC.
+
+GNU CC is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2, or (at your option)
+any later version.
+
+GNU CC is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License
+along with GNU CC; see the file COPYING. If not, write to
+the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. */
+
+#define MIPS_CPU_STRING_DEFAULT "vr4100"
+#define MULTILIB_DEFAULTS \
+ { MULTILIB_ENDIAN_DEFAULT, MULTILIB_ABI_DEFAULT, "march=vr4100" }
git://gcc.gnu.org / gcc.git / commitdiff