re PR target/34900 (target mips64vrel-elf. Internal compiler error (in reload_cse_sim...

gcc/
	PR target/34900
	* config/mips/mips.c (gen_load_const_gp): New function, taking a
	comment from...
	(mips16_gp_pseudo_reg): ...here.
	* config/mips/mips.md (load_const_gp): Replace with...
	(load_const_gp_<mode>): ...this :P-based insn.

From-SVN: r131983

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 768dacd38987636f43b3dc1954da3fc7da417ee1..007d67b5f0ebe2cfc6a724d9b12979b3df3c8d41 100644 (file)
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,12 @@
+2008-01-31  Richard Sandiford  <rsandifo@nildram.co.uk>
+
+       PR target/34900
+       * config/mips/mips.c (gen_load_const_gp): New function, taking a
+       comment from...
+       (mips16_gp_pseudo_reg): ...here.
+       * config/mips/mips.md (load_const_gp): Replace with...
+       (load_const_gp_<mode>): ...this :P-based insn.
+
 2008-01-31  Manuel Lopez-Ibanez  <manu@gcc.gnu.org>
 
        * doc/invoke.texi (-ansi): Mention explicitly corresponding -std=

diff --git a/gcc/config/mips/mips.c b/gcc/config/mips/mips.c
index c2d4765efb6a377c644849caf34ba18b62ed10b3..da8b4aa4c961a0161bc2a505ca7adb7007e73305 100644 (file)
--- a/gcc/config/mips/mips.c
+++ b/gcc/config/mips/mips.c
@@ -2161,6 +2161,18 @@ mips_emit_call_insn (rtx pattern, bool lazy_p)
   return insn;
 }
 \f
+/* Return an instruction that copies $gp into register REG.  We want
+   GCC to treat the register's value as constant, so that its value
+   can be rematerialized on demand.  */
+
+static rtx
+gen_load_const_gp (rtx reg)
+{
+  return (Pmode == SImode
+         ? gen_load_const_gp_si (reg)
+         : gen_load_const_gp_di (reg));
+}
+
 /* Return a pseudo register that contains the value of $gp throughout
    the current function.  Such registers are needed by MIPS16 functions,
    for which $gp itself is not a valid base register or addition operand.  */
@@ -2179,8 +2191,6 @@ mips16_gp_pseudo_reg (void)
     {
       rtx insn, scan, after;
 
-      /* We want GCC to treat the register's value as constant, so that
-        it can be rematerialized on demand.  */
       insn = gen_load_const_gp (cfun->machine->mips16_gp_pseudo_rtx);
 
       push_topmost_sequence ();

diff --git a/gcc/config/mips/mips.md b/gcc/config/mips/mips.md
index 8b7e612f386d71f0ae285076b6c8b6bf11f1d4ab..a6ddb8c967f46dadc6a0e4964d82072ba794b0b8 100644 (file)
--- a/gcc/config/mips/mips.md
+++ b/gcc/config/mips/mips.md
@@ -4265,9 +4265,9 @@
    (set_attr "mode" "<HALFMODE>")])
 
 ;; Move a constant that satisfies CONST_GP_P into operand 0.
-(define_expand "load_const_gp"
-  [(set (match_operand 0 "register_operand" "=d")
-       (const (unspec [(const_int 0)] UNSPEC_GP)))])
+(define_expand "load_const_gp_<mode>"
+  [(set (match_operand:P 0 "register_operand" "=d")
+       (const:P (unspec:P [(const_int 0)] UNSPEC_GP)))])
 
 ;; Insn to initialize $gp for n32/n64 abicalls.  Operand 0 is the offset
 ;; of _gp from the start of this function.  Operand 1 is the incoming