[(set (reg FLAGS_REG)
(compare
(and:QI
- (match_operand:QI 0 "nonimmediate_operand" "%qm,*a,qm,r")
- (match_operand:QI 1 "nonmemory_operand" "q,n,n,n"))
+ (match_operand:QI 0 "nonimmediate_operand" "%qm,qm,r")
+ (match_operand:QI 1 "nonmemory_operand" "q,n,n"))
(const_int 0)))]
"ix86_match_ccmode (insn,
CONST_INT_P (operands[1])
&& INTVAL (operands[1]) >= 0 ? CCNOmode : CCZmode)"
{
- if (which_alternative == 3)
+ if (get_attr_mode (insn) == MODE_SI)
{
if (CONST_INT_P (operands[1]) && INTVAL (operands[1]) < 0)
operands[1] = GEN_INT (INTVAL (operands[1]) & 0xff);
return "test{b}\t{%1, %0|%0, %1}";
}
[(set_attr "type" "test")
- (set_attr "mode" "QI,QI,QI,SI")
- (set_attr "pent_pair" "uv,uv,np,np")])
+ (set (attr "mode")
+ (cond [(eq_attr "alternative" "2")
+ (const_string "SI")
+ (and (match_test "optimize_insn_for_size_p ()")
+ (and (match_operand 0 "ext_QIreg_operand")
+ (match_operand 1 "const_0_to_127_operand")))
+ (const_string "SI")
+ ]
+ (const_string "QI")))
+ (set_attr "pent_pair" "uv,np,np")])
(define_insn "*test<mode>_1"
[(set (reg FLAGS_REG)
CONST_INT_P (operands[2])
&& INTVAL (operands[2]) >= 0 ? CCNOmode : CCZmode)"
{
- if (which_alternative == 2)
+ if (get_attr_mode (insn) == MODE_SI)
{
if (CONST_INT_P (operands[2]) && INTVAL (operands[2]) < 0)
operands[2] = GEN_INT (INTVAL (operands[2]) & 0xff);
return "and{b}\t{%2, %0|%0, %2}";
}
[(set_attr "type" "alu")
- (set_attr "mode" "QI,QI,SI")
+ (set (attr "mode")
+ (cond [(eq_attr "alternative" "2")
+ (const_string "SI")
+ (and (match_test "optimize_insn_for_size_p ()")
+ (and (match_operand 0 "ext_QIreg_operand")
+ (match_operand 2 "const_0_to_127_operand")))
+ (const_string "SI")
+ ]
+ (const_string "QI")))
;; Potential partial reg stall on alternative 2.
(set (attr "preferred_for_speed")
(cond [(eq_attr "alternative" "2")