[AArch64 1/3] Don't disparage add/sub in SIMD registers

        * config/aarch64/aarch64.md (subdi3, adddi3_aarch64): Don't penalize
        SIMD reg variant.

From-SVN: r218958

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 19b33e719cc4f041616e248380151eefb5de2cf5..f27d69869614667bcf7b4694d69cbd043058ad6b 100644 (file)
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,8 @@
+2014-12-19  Alan Lawrence  <alan.lawrence@arm.com>
+
+       * config/aarch64/aarch64.md (subdi3, adddi3_aarch64): Don't penalize
+       SIMD reg variant.
+
 2014-12-19  Martin Liska  <mliska@suse.cz>
 
        PR ipa/63569

diff --git a/gcc/config/aarch64/aarch64.md b/gcc/config/aarch64/aarch64.md
index 12532c1675fa6e6a1e335be127ed3a8902e44b52..3e8434602b99527a41875ebeb319787ab875a887 100644 (file)
--- a/gcc/config/aarch64/aarch64.md
+++ b/gcc/config/aarch64/aarch64.md
@@ -1434,10 +1434,10 @@
 
 (define_insn "*adddi3_aarch64"
   [(set
-    (match_operand:DI 0 "register_operand" "=rk,rk,rk,!w")
+    (match_operand:DI 0 "register_operand" "=rk,rk,rk,w")
     (plus:DI
-     (match_operand:DI 1 "register_operand" "%rk,rk,rk,!w")
-     (match_operand:DI 2 "aarch64_plus_operand" "I,r,J,!w")))]
+     (match_operand:DI 1 "register_operand" "%rk,rk,rk,w")
+     (match_operand:DI 2 "aarch64_plus_operand" "I,r,J,w")))]
   ""
   "@
   add\\t%x0, %x1, %2
@@ -1908,9 +1908,9 @@
 )
 
 (define_insn "subdi3"
-  [(set (match_operand:DI 0 "register_operand" "=rk,!w")
-       (minus:DI (match_operand:DI 1 "register_operand" "r,!w")
-                  (match_operand:DI 2 "register_operand" "r,!w")))]
+  [(set (match_operand:DI 0 "register_operand" "=rk,w")
+       (minus:DI (match_operand:DI 1 "register_operand" "r,w")
+                  (match_operand:DI 2 "register_operand" "r,w")))]
   ""
   "@
    sub\\t%x0, %x1, %x2