;; the mode is MODE_FLOAT
;; 2 `push multiple' operation: operand 0 is the first register. Subsequent
;; registers are in parallel (use...) expressions.
+;; 3 A symbol that has been treated properly for pic usage, that is, we
+;; will add the pic_register value to it before trying to dereference it.
\f
;; Attributes
-; condition codes: this one is used by final_prescan_insn to speed up
-; conditionalizing instructions. It saves having to scan the rtl to see if
-; it uses or alters the condition codes.
-
-; USE means that the condition codes are used by the insn in the process of
-; outputting code, this means (at present) that we can't use the insn in
-; inlined branches
-
-; SET means that the purpose of the insn is to set the condition codes in a
-; well defined manner.
-
-; CLOB means that the condition codes are altered in an undefined manner, if
-; they are altered at all
-
-; JUMP_CLOB is used when the conditions are not defined if a branch is taken,
-; but are if the branch wasn't taken; the effect is to limit the branch
-; elimination scanning.
-
-; NOCOND means that the condition codes are neither altered nor affect the
-; output of this insn
-
-(define_attr "conds" "use,set,clob,jump_clob,nocond"
- (const_string "nocond"))
+; PROG_MODE attribute is used to determine whether condition codes are
+; clobbered by a call insn: they are if in prog32 mode. This is controlled
+; by the -mapcs-{32,26} flag, and possibly the -mcpu=... option.
+(define_attr "prog_mode" "prog26,prog32" (const (symbol_ref "arm_prog_mode")))
; CPU attribute is used to determine whether condition codes are clobbered
; by a call insn: on the arm6 they are if in 32-bit addressing mode; on the
; arm2 and arm3 the condition codes are restored by the return.
-(define_attr "cpu" "arm2,arm3,arm6" (const (symbol_ref "arm_cpu_attr")))
+(define_attr "cpu" "arm2,arm3,arm6,arm7"
+ (const (symbol_ref "arm_cpu_attr")))
; Floating Point Unit. If we only have floating point emulation, then there
; is no point in scheduling the floating point insns. (Well, for best
; performance we should try and group them together).
-(define_attr "fpu" "fpa,fpe" (const (symbol_ref "arm_fpu_attr")))
+(define_attr "fpu" "fpa,fpe2,fpe3" (const (symbol_ref "arm_fpu_attr")))
; LENGTH of an instruction (in bytes)
(define_attr "length" "" (const_int 4))
; Classification of each insn
; normal any data instruction that doesn't hit memory or fp regs
+; mult a multiply instruction
; block blockage insn, this blocks all functional units
; float a floating point arithmetic operation (subject to expansion)
; fdivx XFmode floating point division
; store4 store 4 words
;
(define_attr "type"
- "normal,block,float,fdivx,fdivd,fdivs,fmul,ffmul,farith,ffarith,float_em,f_load,f_store,f_mem_r,r_mem_f,f_2_r,r_2_f,call,load,store1,store2,store3,store4"
+ "normal,mult,block,float,fdivx,fdivd,fdivs,fmul,ffmul,farith,ffarith,float_em,f_load,f_store,f_mem_r,r_mem_f,f_2_r,r_2_f,call,load,store1,store2,store3,store4"
(const_string "normal"))
+; condition codes: this one is used by final_prescan_insn to speed up
+; conditionalizing instructions. It saves having to scan the rtl to see if
+; it uses or alters the condition codes.
+
+; USE means that the condition codes are used by the insn in the process of
+; outputting code, this means (at present) that we can't use the insn in
+; inlined branches
+
+; SET means that the purpose of the insn is to set the condition codes in a
+; well defined manner.
+
+; CLOB means that the condition codes are altered in an undefined manner, if
+; they are altered at all
+
+; JUMP_CLOB is used when the conditions are not defined if a branch is taken,
+; but are if the branch wasn't taken; the effect is to limit the branch
+; elimination scanning.
+
+; NOCOND means that the condition codes are neither altered nor affect the
+; output of this insn
+
+(define_attr "conds" "use,set,clob,jump_clob,nocond"
+ (if_then_else (eq_attr "type" "call")
+ (if_then_else (eq_attr "prog_mode" "prog32")
+ (const_string "clob") (const_string "nocond"))
+ (const_string "nocond")))
+
(define_attr "write_conflict" "no,yes"
(if_then_else (eq_attr "type"
"block,float_em,f_load,f_store,f_mem_r,r_mem_f,call,load")
(const_string "yes")
(const_string "no")))
+(define_attr "core_cycles" "single,multi"
+ (if_then_else (eq_attr "type"
+ "normal,float,fdivx,fdivd,fdivs,fmul,ffmul,farith,ffarith")
+ (const_string "single")
+ (const_string "multi")))
+
; The write buffer on some of the arm6 processors is hard to model exactly.
; There is room in the buffer for up to two addresses and up to eight words
; of memory, but the two needn't be split evenly. When writing the two
(define_function_unit "fpa_mem" 1 0 (and (eq_attr "fpu" "fpa")
(eq_attr "type" "f_load")) 3 1)
-(define_function_unit "write_buf" 1 2 (eq_attr "type" "store1") 3 3
+(define_function_unit "write_buf" 1 2 (eq_attr "type" "store1") 5 3)
+(define_function_unit "write_buf" 1 2 (eq_attr "type" "store2") 7 4)
+(define_function_unit "write_buf" 1 2 (eq_attr "type" "store3") 9 5)
+(define_function_unit "write_buf" 1 2 (eq_attr "type" "store4") 11 6)
+(define_function_unit "write_buf" 1 2 (eq_attr "type" "r_mem_f") 5 3)
+
+;; The write_blockage unit models (partially), the fact that writes will stall
+;; until the write buffer empties.
+
+(define_function_unit "write_blockage" 1 0 (eq_attr "type" "store1") 5 5
[(eq_attr "write_conflict" "yes")])
-(define_function_unit "write_buf" 1 2 (eq_attr "type" "store2") 5 5
+(define_function_unit "write_blockage" 1 0 (eq_attr "type" "store2") 7 7
[(eq_attr "write_conflict" "yes")])
-(define_function_unit "write_buf" 1 2 (eq_attr "type" "store3") 7 7
+(define_function_unit "write_blockage" 1 0 (eq_attr "type" "store3") 9 9
[(eq_attr "write_conflict" "yes")])
-(define_function_unit "write_buf" 1 2 (eq_attr "type" "store4") 9 9
+(define_function_unit "write_blockage" 1 0 (eq_attr "type" "store4") 11 11
[(eq_attr "write_conflict" "yes")])
-(define_function_unit "write_buf" 1 2 (eq_attr "type" "r_mem_f") 3 3
+(define_function_unit "write_blockage" 1 0 (eq_attr "type" "r_mem_f") 5 5
[(eq_attr "write_conflict" "yes")])
+(define_function_unit "write_blockage" 1 0
+ (eq_attr "write_conflict" "yes") 1 1)
+
+(define_function_unit "core" 1 1 (eq_attr "core_cycles" "single") 1 1)
+
+(define_function_unit "core" 1 1 (eq_attr "type" "load") 2 2)
+
+(define_function_unit "core" 1 1 (eq_attr "type" "mult") 16 16)
+
+(define_function_unit "core" 1 1 (eq_attr "type" "store1") 2 2)
+
+(define_function_unit "core" 1 1 (eq_attr "type" "store2") 3 3)
+
+(define_function_unit "core" 1 1 (eq_attr "type" "store3") 4 4)
+
+(define_function_unit "core" 1 1 (eq_attr "type" "store4") 5 5)
+
+(define_function_unit "core" 1 1
+ (and (eq_attr "core_cycles" "multi")
+ (eq_attr "type" "!mult,load,store2,store3,store4")) 32 32)
+
\f
;; Note: For DImode insns, there is normally no reason why operands should
;; not be in the same register, what we don't want is for something being
[(set_attr "conds" "clob")
(set_attr "length" "8")])
-(define_insn ""
+(define_insn "*adddi_sesidi_di"
[(set (match_operand:DI 0 "s_register_operand" "=&r,&r")
(plus:DI (sign_extend:DI
(match_operand:SI 1 "s_register_operand" "r,r"))
[(set_attr "conds" "clob")
(set_attr "length" "8")])
-(define_insn ""
+(define_insn "*adddi_zesidi_di"
[(set (match_operand:DI 0 "s_register_operand" "=&r,&r")
(plus:DI (zero_extend:DI
(match_operand:SI 1 "s_register_operand" "r,r"))
DONE;
")
-(define_insn ""
+(define_insn "*addsi3_insn"
[(set (match_operand:SI 0 "s_register_operand" "=r,r,r")
(plus:SI (match_operand:SI 1 "s_register_operand" "r,r,r")
(match_operand:SI 2 "reg_or_int_operand" "rI,L,?n")))]
#"
[(set_attr "length" "4,4,16")])
-(define_insn ""
+(define_insn "*addsi3_compare0"
[(set (reg:CC_NOOV 24)
(compare:CC_NOOV
(plus:SI (match_operand:SI 1 "s_register_operand" "r,r")
sub%?s\\t%0, %1, #%n2"
[(set_attr "conds" "set")])
-(define_insn ""
+(define_insn "*addsi3_compareneg"
[(set (reg:CC 24)
(compare:CC (match_operand:SI 1 "s_register_operand" "r,r")
(neg:SI (match_operand:SI 2 "arm_add_operand" "rI,L"))))
suf%?d\\t%0, %1, #%N2"
[(set_attr "type" "farith")])
-(define_insn ""
+(define_insn "*adddf_df_esfdf"
[(set (match_operand:DF 0 "s_register_operand" "=f,f")
(plus:DF (float_extend:DF
(match_operand:SF 1 "s_register_operand" "f,f"))
suf%?d\\t%0, %1, #%N2"
[(set_attr "type" "farith")])
-(define_insn ""
+(define_insn "*adddf_df_esfdf"
[(set (match_operand:DF 0 "s_register_operand" "=f")
(plus:DF (match_operand:DF 1 "s_register_operand" "f")
(float_extend:DF
"adf%?d\\t%0, %1, %2"
[(set_attr "type" "farith")])
-(define_insn ""
+(define_insn "*adddf_esfdf_esfdf"
[(set (match_operand:DF 0 "s_register_operand" "=f")
(plus:DF (float_extend:DF
(match_operand:SF 1 "s_register_operand" "f"))
[(set_attr "conds" "clob")
(set_attr "length" "8")])
-(define_insn ""
+(define_insn "*subdi_di_zesidi"
[(set (match_operand:DI 0 "s_register_operand" "=&r,&r")
(minus:DI (match_operand:DI 1 "s_register_operand" "?r,0")
(zero_extend:DI
[(set_attr "conds" "clob")
(set_attr "length" "8")])
-(define_insn ""
+(define_insn "*subdi_di_sesidi"
[(set (match_operand:DI 0 "s_register_operand" "=&r,&r")
(minus:DI (match_operand:DI 1 "s_register_operand" "r,0")
(sign_extend:DI
[(set_attr "conds" "clob")
(set_attr "length" "8")])
-(define_insn ""
+(define_insn "*subdi_zesidi_di"
[(set (match_operand:DI 0 "s_register_operand" "=&r,&r")
(minus:DI (zero_extend:DI
(match_operand:SI 2 "s_register_operand" "r,r"))
[(set_attr "conds" "clob")
(set_attr "length" "8")])
-(define_insn ""
+(define_insn "*subdi_sesidi_di"
[(set (match_operand:DI 0 "s_register_operand" "=&r,&r")
(minus:DI (sign_extend:DI
(match_operand:SI 2 "s_register_operand" "r,r"))
[(set_attr "conds" "clob")
(set_attr "length" "8")])
-(define_insn ""
+(define_insn "*subdi_zesidi_zesidi"
[(set (match_operand:DI 0 "s_register_operand" "=r")
(minus:DI (zero_extend:DI
(match_operand:SI 1 "s_register_operand" "r"))
}
")
-(define_insn ""
+(define_insn "*subsi3_insn"
[(set (match_operand:SI 0 "s_register_operand" "=r,r")
(minus:SI (match_operand:SI 1 "reg_or_int_operand" "rI,?n")
(match_operand:SI 2 "s_register_operand" "r,r")))]
DONE;
")
-(define_insn ""
+(define_insn "*subsi3_compare0"
[(set (reg:CC_NOOV 24)
(compare:CC_NOOV (minus:SI (match_operand:SI 1 "arm_rhs_operand" "r,I")
(match_operand:SI 2 "arm_rhs_operand" "rI,r"))
rsf%?d\\t%0, %2, %1"
[(set_attr "type" "farith")])
-(define_insn ""
+(define_insn "*subdf_esfdf_df"
[(set (match_operand:DF 0 "s_register_operand" "=f")
(minus:DF (float_extend:DF
(match_operand:SF 1 "s_register_operand" "f"))
"suf%?d\\t%0, %1, %2"
[(set_attr "type" "farith")])
-(define_insn ""
+(define_insn "*subdf_df_esfdf"
[(set (match_operand:DF 0 "s_register_operand" "=f,f")
(minus:DF (match_operand:DF 1 "fpu_rhs_operand" "f,G")
(float_extend:DF
rsf%?d\\t%0, %2, %1"
[(set_attr "type" "farith")])
-(define_insn ""
+(define_insn "*subdf_esfdf_esfdf"
[(set (match_operand:DF 0 "s_register_operand" "=f")
(minus:DF (float_extend:DF
(match_operand:SF 1 "s_register_operand" "f"))
(mult:SI (match_operand:SI 2 "s_register_operand" "r,r")
(match_operand:SI 1 "s_register_operand" "%?r,0")))]
""
- "mul%?\\t%0, %2, %1")
+ "mul%?\\t%0, %2, %1"
+[(set_attr "type" "mult")])
-(define_insn ""
+(define_insn "*mulsi3_compare0"
[(set (reg:CC_NOOV 24)
(compare:CC_NOOV (mult:SI
(match_operand:SI 2 "s_register_operand" "r,r")
(mult:SI (match_dup 2) (match_dup 1)))]
""
"mul%?s\\t%0, %2, %1"
-[(set_attr "conds" "set")])
+[(set_attr "conds" "set")
+ (set_attr "type" "mult")])
-(define_insn ""
+(define_insn "*mulsi_compare0_scratch"
[(set (reg:CC_NOOV 24)
(compare:CC_NOOV (mult:SI
(match_operand:SI 2 "s_register_operand" "r,r")
(clobber (match_scratch:SI 0 "=&r,&r"))]
""
"mul%?s\\t%0, %2, %1"
-[(set_attr "conds" "set")])
+[(set_attr "conds" "set")
+ (set_attr "type" "mult")])
;; Unnamed templates to match MLA instruction.
-(define_insn ""
+(define_insn "*mulsi3addsi"
[(set (match_operand:SI 0 "s_register_operand" "=&r,&r,&r,&r")
(plus:SI
(mult:SI (match_operand:SI 2 "s_register_operand" "r,r,r,r")
(match_operand:SI 1 "s_register_operand" "%r,0,r,0"))
(match_operand:SI 3 "s_register_operand" "?r,r,0,0")))]
""
- "mla%?\\t%0, %2, %1, %3")
+ "mla%?\\t%0, %2, %1, %3"
+[(set_attr "type" "mult")])
-(define_insn ""
+(define_insn "*mulsi3addsi_compare0"
[(set (reg:CC_NOOV 24)
(compare:CC_NOOV (plus:SI
(mult:SI
(match_dup 3)))]
""
"mla%?s\\t%0, %2, %1, %3"
-[(set_attr "conds" "set")])
+[(set_attr "conds" "set")
+ (set_attr "type" "mult")])
-(define_insn ""
+(define_insn "*mulsi3addsi_compare0_scratch"
[(set (reg:CC_NOOV 24)
(compare:CC_NOOV (plus:SI
(mult:SI
(clobber (match_scratch:SI 0 "=&r,&r,&r,&r"))]
""
"mla%?s\\t%0, %2, %1, %3"
-[(set_attr "conds" "set")])
+[(set_attr "conds" "set")
+ (set_attr "type" "mult")])
+
+(define_insn "mulsidi3"
+ [(set (match_operand:DI 0 "s_register_operand" "=&r")
+ (mult:DI (sign_extend:DI
+ (match_operand:SI 1 "s_register_operand" "%r"))
+ (sign_extend:DI
+ (match_operand:SI 2 "s_register_operand" "r"))))]
+ "arm_fast_multiply"
+ "smull%?\\t%0, %R0, %1, %2"
+[(set_attr "type" "mult")])
+
+(define_insn "umulsidi3"
+ [(set (match_operand:DI 0 "s_register_operand" "=&r")
+ (mult:DI (zero_extend:DI
+ (match_operand:SI 1 "s_register_operand" "%r"))
+ (zero_extend:DI
+ (match_operand:SI 2 "s_register_operand" "r"))))]
+ "arm_fast_multiply"
+ "umull%?\\t%0, %R0, %1, %2"
+[(set_attr "type" "mult")])
(define_insn "mulsf3"
[(set (match_operand:SF 0 "s_register_operand" "=f")
"muf%?d\\t%0, %1, %2"
[(set_attr "type" "fmul")])
-(define_insn ""
+(define_insn "*muldf_esfdf_df"
[(set (match_operand:DF 0 "s_register_operand" "=f")
(mult:DF (float_extend:DF
(match_operand:SF 1 "s_register_operand" "f"))
"muf%?d\\t%0, %1, %2"
[(set_attr "type" "fmul")])
-(define_insn ""
+(define_insn "*muldf_df_esfdf"
[(set (match_operand:DF 0 "s_register_operand" "=f")
(mult:DF (match_operand:DF 1 "s_register_operand" "f")
(float_extend:DF
"muf%?d\\t%0, %1, %2"
[(set_attr "type" "fmul")])
-(define_insn ""
+(define_insn "*muldf_esfdf_esfdf"
[(set (match_operand:DF 0 "s_register_operand" "=f")
(mult:DF (float_extend:DF
(match_operand:SF 1 "s_register_operand" "f"))
rdf%?d\\t%0, %2, %1"
[(set_attr "type" "fdivd")])
-(define_insn ""
+(define_insn "*divdf_esfdf_df"
[(set (match_operand:DF 0 "s_register_operand" "=f")
(div:DF (float_extend:DF
(match_operand:SF 1 "s_register_operand" "f"))
"dvf%?d\\t%0, %1, %2"
[(set_attr "type" "fdivd")])
-(define_insn ""
+(define_insn "*divdf_df_esfdf"
[(set (match_operand:DF 0 "s_register_operand" "=f")
(div:DF (match_operand:DF 1 "fpu_rhs_operand" "fG")
(float_extend:DF
"rdf%?d\\t%0, %2, %1"
[(set_attr "type" "fdivd")])
-(define_insn ""
+(define_insn "*divdf_esfdf_esfdf"
[(set (match_operand:DF 0 "s_register_operand" "=f")
(div:DF (float_extend:DF
(match_operand:SF 1 "s_register_operand" "f"))
"rmf%?d\\t%0, %1, %2"
[(set_attr "type" "fdivd")])
-(define_insn ""
+(define_insn "*moddf_esfdf_df"
[(set (match_operand:DF 0 "s_register_operand" "=f")
(mod:DF (float_extend:DF
(match_operand:SF 1 "s_register_operand" "f"))
"rmf%?d\\t%0, %1, %2"
[(set_attr "type" "fdivd")])
-(define_insn ""
+(define_insn "*moddf_df_esfdf"
[(set (match_operand:DF 0 "s_register_operand" "=f")
(mod:DF (match_operand:DF 1 "s_register_operand" "f")
(float_extend:DF
"rmf%?d\\t%0, %1, %2"
[(set_attr "type" "fdivd")])
-(define_insn ""
+(define_insn "*moddf_esfdf_esfdf"
[(set (match_operand:DF 0 "s_register_operand" "=f")
(mod:DF (float_extend:DF
(match_operand:SF 1 "s_register_operand" "f"))
"and%?\\t%0, %1, %2\;and%?\\t%R0, %R1, %R2"
[(set_attr "length" "8")])
-(define_insn ""
+(define_insn "*anddi_zesidi_di"
[(set (match_operand:DI 0 "s_register_operand" "=&r,&r")
(and:DI (zero_extend:DI
(match_operand:SI 2 "s_register_operand" "r,r"))
"and%?\\t%0, %1, %2\;mov%?\\t%R0, #0"
[(set_attr "length" "8")])
-(define_insn ""
+(define_insn "*anddi_sesdi_di"
[(set (match_operand:DI 0 "s_register_operand" "=&r,&r")
(and:DI (sign_extend:DI
(match_operand:SI 2 "s_register_operand" "r,r"))
}
")
-(define_insn ""
+(define_insn "*andsi3_insn"
[(set (match_operand:SI 0 "s_register_operand" "=r,r,r")
(and:SI (match_operand:SI 1 "s_register_operand" "r,r,r")
(match_operand:SI 2 "reg_or_int_operand" "rI,K,?n")))]
DONE;
")
-(define_insn ""
+(define_insn "*andsi3_compare0"
[(set (reg:CC_NOOV 24)
(compare:CC_NOOV
(and:SI (match_operand:SI 1 "s_register_operand" "r,r")
bic%?s\\t%0, %1, #%B2"
[(set_attr "conds" "set")])
-(define_insn ""
+(define_insn "*andsi3_compare0_scratch"
[(set (reg:CC_NOOV 24)
(compare:CC_NOOV
(and:SI (match_operand:SI 0 "s_register_operand" "r,r")
bic%?s\\t%3, %0, #%B1"
[(set_attr "conds" "set")])
-(define_insn ""
+(define_insn "*zeroextractsi_compare0_scratch"
[(set (reg:CC_NOOV 24)
(compare:CC_NOOV (zero_extract:SI
(match_operand:SI 0 "s_register_operand" "r")
"
[(set_attr "conds" "set")])
-(define_insn ""
+(define_insn "*zeroextractqi_compare0_scratch"
[(set (reg:CC_NOOV 24)
(compare:CC_NOOV (zero_extract:SI
(match_operand:QI 0 "memory_operand" "m")
(set_attr "length" "8")])
;; constants for op 2 will never be given to these patterns.
-(define_insn ""
+(define_insn "*anddi_notdi_di"
[(set (match_operand:DI 0 "s_register_operand" "=&r,&r")
(and:DI (not:DI (match_operand:DI 2 "s_register_operand" "r,0"))
(match_operand:DI 1 "s_register_operand" "0,r")))]
"bic%?\\t%0, %1, %2\;bic%?\\t%R0, %R1, %R2"
[(set_attr "length" "8")])
-(define_insn ""
+(define_insn "*anddi_notzesidi_di"
[(set (match_operand:DI 0 "s_register_operand" "=&r,&r")
(and:DI (not:DI (zero_extend:DI
(match_operand:SI 2 "s_register_operand" "r,r")))
bic%?\\t%0, %1, %2\;mov%?\\t%R0, %R1"
[(set_attr "length" "4,8")])
-(define_insn ""
+(define_insn "*anddi_notsesidi_di"
[(set (match_operand:DI 0 "s_register_operand" "=&r,&r")
(and:DI (not:DI (sign_extend:DI
(match_operand:SI 2 "s_register_operand" "r,r")))
"bic%?\\t%0, %1, %2\;bic%?\\t%R0, %R1, %2, asr #31"
[(set_attr "length" "8")])
-(define_insn ""
+(define_insn "*andsi_notsi_si"
[(set (match_operand:SI 0 "s_register_operand" "=r")
(and:SI (not:SI (match_operand:SI 2 "s_register_operand" "r"))
(match_operand:SI 1 "s_register_operand" "r")))]
""
"bic%?\\t%0, %1, %2")
-(define_insn ""
+(define_insn "*andsi_notsi_si_compare0"
[(set (reg:CC_NOOV 24)
(compare:CC_NOOV
(and:SI (not:SI (match_operand:SI 2 "s_register_operand" "r"))
"bic%?s\\t%0, %1, %2"
[(set_attr "conds" "set")])
-(define_insn ""
+(define_insn "*andsi_notsi_si_compare0_scratch"
[(set (reg:CC_NOOV 24)
(compare:CC_NOOV
(and:SI (not:SI (match_operand:SI 2 "s_register_operand" "r"))
"orr%?\\t%0, %1, %2\;orr%?\\t%R0, %R1, %R2"
[(set_attr "length" "8")])
-(define_insn ""
+(define_insn "*iordi_zesidi_di"
[(set (match_operand:DI 0 "s_register_operand" "=&r,&r")
(ior:DI (zero_extend:DI
(match_operand:SI 2 "s_register_operand" "r,r"))
orr%?\\t%0, %1, %2\;mov%?\\t%R0, %R1"
[(set_attr "length" "4,8")])
-(define_insn ""
+(define_insn "*iordi_sesidi_di"
[(set (match_operand:DI 0 "s_register_operand" "=&r,&r")
(ior:DI (sign_extend:DI
(match_operand:SI 2 "s_register_operand" "r,r"))
}
")
-(define_insn ""
+(define_insn "*iorsi3_insn"
[(set (match_operand:SI 0 "s_register_operand" "=r,r")
(ior:SI (match_operand:SI 1 "s_register_operand" "r,r")
(match_operand:SI 2 "reg_or_int_operand" "rI,?n")))]
DONE;
")
-(define_insn ""
+(define_insn "*iorsi3_compare0"
[(set (reg:CC_NOOV 24)
(compare:CC_NOOV (ior:SI (match_operand:SI 1 "s_register_operand" "%r")
(match_operand:SI 2 "arm_rhs_operand" "rI"))
"orr%?s\\t%0, %1, %2"
[(set_attr "conds" "set")])
-(define_insn ""
+(define_insn "*iorsi3_compare0_scratch"
[(set (reg:CC_NOOV 24)
(compare:CC_NOOV (ior:SI (match_operand:SI 1 "s_register_operand" "%r")
(match_operand:SI 2 "arm_rhs_operand" "rI"))
"eor%?\\t%0, %1, %2\;eor%?\\t%R0, %R1, %R2"
[(set_attr "length" "8")])
-(define_insn ""
+(define_insn "*xordi_zesidi_di"
[(set (match_operand:DI 0 "s_register_operand" "=&r,&r")
(xor:DI (zero_extend:DI
(match_operand:SI 2 "s_register_operand" "r,r"))
eor%?\\t%0, %1, %2\;mov%?\\t%R0, %R1"
[(set_attr "length" "4,8")])
-(define_insn ""
+(define_insn "*xordi_sesidi_di"
[(set (match_operand:DI 0 "s_register_operand" "=&r,&r")
(xor:DI (sign_extend:DI
(match_operand:SI 2 "s_register_operand" "r,r"))
""
"eor%?\\t%0, %1, %2")
-(define_insn ""
+(define_insn "*xorsi3_compare0"
[(set (reg:CC_NOOV 24)
(compare:CC_NOOV (xor:SI (match_operand:SI 1 "s_register_operand" "r")
(match_operand:SI 2 "arm_rhs_operand" "rI"))
"eor%?s\\t%0, %1, %2"
[(set_attr "conds" "set")])
-(define_insn ""
+(define_insn "*xorsi3_compare0_scratch"
[(set (reg:CC_NOOV 24)
(compare:CC_NOOV (xor:SI (match_operand:SI 0 "s_register_operand" "r")
(match_operand:SI 1 "arm_rhs_operand" "rI"))
""
)
-(define_insn ""
+(define_insn "*andsi_iorsi3_notsi"
[(set (match_operand:SI 0 "s_register_operand" "=&r,&r,&r")
(and:SI (ior:SI (match_operand:SI 1 "s_register_operand" "r,r,0")
(match_operand:SI 2 "arm_rhs_operand" "rI,0,rI"))
[(set_attr "conds" "clob")
(set_attr "length" "8,8,12")])
-(define_insn ""
+(define_insn "*store_minmansi"
[(set (match_operand:SI 0 "memory_operand" "=m")
(match_operator:SI 3 "minmax_operator"
[(match_operand:SI 1 "s_register_operand" "r")
(set_attr "length" "12")
(set_attr "type" "store1")])
-(define_insn ""
+(define_insn "*minmax_arithsi"
[(set (match_operand:SI 0 "s_register_operand" "=r,r")
(match_operator:SI 4 "shiftable_operator"
[(match_operator:SI 5 "minmax_operator"
operands[2] = GEN_INT (INTVAL (operands[2]) % 32);
")
-(define_insn ""
+(define_insn "*shiftsi3"
[(set (match_operand:SI 0 "s_register_operand" "=r")
(match_operator:SI 3 "shift_operator"
[(match_operand:SI 1 "s_register_operand" "r")
""
"mov%?\\t%0, %1%S3")
-(define_insn ""
+(define_insn "*shiftsi3_compare0"
[(set (reg:CC_NOOV 24)
(compare:CC_NOOV (match_operator:SI 3 "shift_operator"
[(match_operand:SI 1 "s_register_operand" "r")
"mov%?s\\t%0, %1%S3"
[(set_attr "conds" "set")])
-(define_insn ""
+(define_insn "*shiftsi3_compare0_scratch"
[(set (reg:CC_NOOV 24)
(compare:CC_NOOV (match_operator:SI 3 "shift_operator"
[(match_operand:SI 1 "s_register_operand" "r")
"mov%?s\\t%0, %1%S3"
[(set_attr "conds" "set")])
-(define_insn ""
+(define_insn "*notsi_shiftsi"
[(set (match_operand:SI 0 "s_register_operand" "=r")
(not:SI (match_operator:SI 3 "shift_operator"
[(match_operand:SI 1 "s_register_operand" "r")
""
"mvn%?\\t%0, %1%S3")
-(define_insn ""
+(define_insn "*notsi_shiftsi_compare0"
[(set (reg:CC_NOOV 24)
(compare:CC_NOOV (not:SI (match_operator:SI 3 "shift_operator"
[(match_operand:SI 1 "s_register_operand" "r")
"mvn%?s\\t%0, %1%S3"
[(set_attr "conds" "set")])
-(define_insn ""
+(define_insn "*not_shiftsi_compare0_scratch"
[(set (reg:CC_NOOV 24)
(compare:CC_NOOV (not:SI (match_operator:SI 3 "shift_operator"
[(match_operand:SI 1 "s_register_operand" "r")
"mnf%?d\\t%0, %1"
[(set_attr "type" "ffarith")])
-(define_insn ""
+(define_insn "*negdf_esfdf"
[(set (match_operand:DF 0 "s_register_operand" "=f")
(neg:DF (float_extend:DF
(match_operand:SF 1 "s_register_operand" "f"))))]
[(set_attr "conds" "clob,*")
(set_attr "length" "8")])
-(define_insn ""
+(define_insn "*neg_abssi2"
[(set (match_operand:SI 0 "s_register_operand" "=r,&r")
(neg:SI (abs:SI (match_operand:SI 1 "s_register_operand" "0,r"))))
(clobber (reg 24))]
"abs%?d\\t%0, %1"
[(set_attr "type" "ffarith")])
-(define_insn ""
+(define_insn "*absdf_esfdf"
[(set (match_operand:DF 0 "s_register_operand" "=f")
(abs:DF (float_extend:DF
(match_operand:SF 1 "s_register_operand" "f"))))]
"sqt%?d\\t%0, %1"
[(set_attr "type" "float_em")])
-(define_insn ""
+(define_insn "*sqrtdf_esfdf"
[(set (match_operand:DF 0 "s_register_operand" "=f")
(sqrt:DF (float_extend:DF
(match_operand:SF 1 "s_register_operand" "f"))))]
"sin%?d\\t%0, %1"
[(set_attr "type" "float_em")])
-(define_insn ""
+(define_insn "*sindf_esfdf"
[(set (match_operand:DF 0 "s_register_operand" "=f")
(unspec:DF [(float_extend:DF
(match_operand:SF 1 "s_register_operand" "f"))] 0))]
"cos%?d\\t%0, %1"
[(set_attr "type" "float_em")])
-(define_insn ""
+(define_insn "*cosdf_esfdf"
[(set (match_operand:DF 0 "s_register_operand" "=f")
(unspec:DF [(float_extend:DF
(match_operand:SF 1 "s_register_operand" "f"))] 1))]
""
"mvn%?\\t%0, %1")
-(define_insn ""
+(define_insn "*notsi_compare0"
[(set (reg:CC_NOOV 24)
(compare:CC_NOOV (not:SI (match_operand:SI 1 "s_register_operand" "r"))
(const_int 0)))
"mvn%?s\\t%0, %1"
[(set_attr "conds" "set")])
-(define_insn ""
+(define_insn "*notsi_compare0_scratch"
[(set (reg:CC_NOOV 24)
(compare:CC_NOOV (not:SI (match_operand:SI 1 "s_register_operand" "r"))
(const_int 0)))
""
"
{
+ if (arm_arch4 && GET_CODE (operands[1]) == MEM)
+ {
+ emit_insn (gen_rtx (SET, VOIDmode, operands[0],
+ gen_rtx (ZERO_EXTEND, SImode, operands[1])));
+ DONE;
+ }
if (TARGET_SHORT_BY_BYTES && GET_CODE (operands[1]) == MEM)
{
emit_insn (gen_movhi_bytes (operands[0], operands[1]));
operands[2] = gen_reg_rtx (SImode);
}")
+(define_insn "*zero_extendhisi_insn"
+ [(set (match_operand:SI 0 "s_register_operand" "=r")
+ (zero_extend:SI (match_operand:HI 1 "memory_operand" "m")))]
+ "arm_arch4"
+ "ldr%?h\\t%0, %1"
+[(set_attr "type" "load")])
+
(define_expand "zero_extendqisi2"
[(set (match_operand:SI 0 "s_register_operand" "=r,r")
(zero_extend:SI
}
")
-(define_insn ""
+(define_insn "*load_extendqisi"
[(set (match_operand:SI 0 "s_register_operand" "=r")
(zero_extend:SI (match_operand:QI 1 "memory_operand" "m")))]
""
(set (match_dup 0) (and:SI (match_dup 2) (const_int 255)))]
"")
-(define_insn ""
+(define_insn "*compareqi_eq0"
[(set (reg:CC_NOOV 24)
(compare:CC_NOOV (match_operand:QI 0 "s_register_operand" "r")
(const_int 0)))]
""
"
{
+ if (arm_arch4 && GET_CODE (operands[1]) == MEM)
+ {
+ emit_insn (gen_rtx (SET, VOIDmode, operands[0],
+ gen_rtx (SIGN_EXTEND, SImode, operands[1])));
+ DONE;
+ }
+
if (TARGET_SHORT_BY_BYTES && GET_CODE (operands[1]) == MEM)
{
emit_insn (gen_extendhisi2_mem (operands[0], operands[1]));
}
")
+(define_insn "*extendhisi_insn"
+ [(set (match_operand:SI 0 "s_register_operand" "=r")
+ (sign_extend:SI (match_operand:HI 1 "memory_operand" "m")))]
+ "arm_arch4"
+ "ldr%?sh\\t%0, %1"
+[(set_attr "type" "load")])
+
(define_expand "extendqihi2"
[(set (match_dup 2)
- (ashift:SI (match_operand:QI 1 "s_register_operand" "")
+ (ashift:SI (match_operand:QI 1 "general_operand" "")
(const_int 24)))
(set (match_operand:HI 0 "s_register_operand" "")
(ashiftrt:SI (match_dup 2)
(const_int 24)))]
""
"
-{ operands[0] = gen_lowpart (SImode, operands[0]);
+{
+ if (arm_arch4 && GET_CODE (operands[1]) == MEM)
+ {
+ emit_insn (gen_rtx (SET, VOIDmode, operands[0],
+ gen_rtx (SIGN_EXTEND, HImode, operands[1])));
+ DONE;
+ }
+ if (! s_register_operand (operands[1], QImode))
+ operands[1] = copy_to_mode_reg (QImode, operands[1]);
+ operands[0] = gen_lowpart (SImode, operands[0]);
operands[1] = gen_lowpart (SImode, operands[1]);
- operands[2] = gen_reg_rtx (SImode); }")
+ operands[2] = gen_reg_rtx (SImode);
+}")
+
+(define_insn "*extendqihi_insn"
+ [(set (match_operand:HI 0 "s_register_operand" "=r")
+ (sign_extend:HI (match_operand:QI 1 "memory_operand" "o<>")))]
+ "arm_arch4"
+ "ldr%?sb\\t%0, %1"
+[(set_attr "type" "load")])
(define_expand "extendqisi2"
[(set (match_dup 2)
(const_int 24)))]
""
"
-{ operands[1] = gen_lowpart (SImode, operands[1]);
- operands[2] = gen_reg_rtx (SImode); }")
+{
+ if (arm_arch4 && GET_CODE (operands[1]) == MEM)
+ {
+ emit_insn (gen_rtx (SET, VOIDmode, operands[0],
+ gen_rtx (SIGN_EXTEND, SImode, operands[1])));
+ DONE;
+ }
+ if (! s_register_operand (operands[1], QImode))
+ operands[1] = copy_to_mode_reg (QImode, operands[1]);
+ operands[1] = gen_lowpart (SImode, operands[1]);
+ operands[2] = gen_reg_rtx (SImode);
+}")
+
+(define_insn "*extendqisi_insn"
+ [(set (match_operand:SI 0 "s_register_operand" "=r")
+ (sign_extend:SI (match_operand:QI 1 "memory_operand" "o<>")))]
+ "arm_arch4"
+ "ldr%?sb\\t%0, %1"
+[(set_attr "type" "load")])
(define_insn "extendsfdf2"
[(set (match_operand:DF 0 "s_register_operand" "=f")
(define_insn "movdi"
- [(set (match_operand:DI 0 "di_operand" "=r,r,r,o<>,r")
- (match_operand:DI 1 "di_operand" "rIK,n,o<>,r,F"))]
+ [(set (match_operand:DI 0 "di_operand" "=r,r,o<>")
+ (match_operand:DI 1 "di_operand" "rIK,mi,r"))]
""
"*
return (output_move_double (operands));
"
-[(set_attr "length" "8,32,8,8,32")
- (set_attr "type" "*,*,load,store2,*")])
+[(set_attr "length" "8,8,8")
+ (set_attr "type" "*,load,store2")])
(define_expand "movsi"
[(set (match_operand:SI 0 "general_operand" "")
}
")
-(define_insn ""
- [(set (match_operand:SI 0 "general_operand" "=r,r,r,r,m,r,r")
- (match_operand:SI 1 "general_operand" "R,m,K,rI,r,S,?n"))]
- "(register_operand (operands[0], SImode)
- && (GET_CODE (operands[1]) != SYMBOL_REF
- || CONSTANT_ADDRESS_P (operands[1])))
+(define_insn "*movsi_insn"
+ [(set (match_operand:SI 0 "general_operand" "=r,r,r,m")
+ (match_operand:SI 1 "general_operand" "rI,K,mi,r"))]
+ "register_operand (operands[0], SImode)
|| register_operand (operands[1], SImode)"
- "*
- switch (which_alternative)
- {
- case 0:
- /* NB Calling get_attr_length may cause the insn to be re-extracted... */
- if (get_attr_length (insn) == 8)
- {
- /* ... so modify the operands here. */
- operands[1] = XEXP (operands[1], 0);
- output_asm_insn (\"sub%?\\t%0, %|pc, #(8 + . - %a1) & ~4095\",
- operands);
- output_asm_insn (\"ldr%?\\t%0, [%0, #- ((4 + . - %a1) & 4095)]\",
- operands);
- }
- else
- {
- /* ... and here. */
- operands[1] = XEXP (operands[1], 0);
- output_asm_insn (\"ldr%?\\t%0, [%|pc, %1 - . - 8]\", operands);
- }
- return \"\";
-
- case 1:
- if (GET_CODE (XEXP (operands[1], 0)) == SYMBOL_REF
- && CONSTANT_POOL_ADDRESS_P (XEXP (operands[1], 0)))
- abort ();
- return \"ldr%?\\t%0, %1\";
-
- case 3:
- return \"mov%?\\t%0, %1\";
- case 2:
- return \"mvn%?\\t%0, #%B1\";
- case 4:
- return \"str%?\\t%1, %0\";
- case 5:
- return output_load_symbol (insn, operands);
- case 6:
- return \"#\";
- }
-"
-[(set (attr "length")
- (cond [(eq_attr "alternative" "0")
- (if_then_else
- (gt (minus
- (pc)
- (symbol_ref "const_pool_offset (XEXP (operands[1], 0))"))
- (const_int 4087))
- (const_int 8)
- (const_int 4))
- (ior (eq_attr "alternative" "5")
- (eq_attr "alternative" "6")) (const_int 16)]
- (const_int 4)))
- (set_attr "type" "load,load,*,*,store1,*,*")])
+ "@
+ mov%?\\t%0, %1
+ mvn%?\\t%0, #%B1
+ ldr%?\\t%0, %1
+ str%?\\t%1, %0"
+[(set_attr "type" "*,*,load,store1")])
(define_split
[(set (match_operand:SI 0 "s_register_operand" "")
DONE;
")
+(define_expand "movaddr"
+ [(set (match_operand:SI 0 "s_register_operand" "")
+ (match_operand:DI 1 "address_operand" ""))]
+ ""
+ "")
+
+(define_insn "*movaddr_insn"
+ [(set (match_operand:SI 0 "s_register_operand" "=r")
+ (match_operand:DI 1 "address_operand" "p"))]
+ "reload_completed
+ && (GET_CODE (operands[1]) == LABEL_REF
+ || (GET_CODE (operands[1]) == CONST
+ && GET_CODE (XEXP (operands[1], 0)) == PLUS
+ && GET_CODE (XEXP (XEXP (operands[1], 0), 0)) == LABEL_REF
+ && GET_CODE (XEXP (XEXP (operands[1], 0), 1)) == CONST_INT))"
+ "adr%?\\t%0, %a1")
+
;; If copying one reg to another we can set the condition codes according to
;; its value. Such a move is common after a return from subroutine and the
;; result is being tested against zero.
-(define_insn ""
+(define_insn "*movsi_compare0"
[(set (reg:CC 24) (compare (match_operand:SI 1 "s_register_operand" "0,r")
(const_int 0)))
(set (match_operand:SI 0 "s_register_operand" "=r,r") (match_dup 1))]
}
")
+(define_expand "storehi_single_op"
+ [(set (match_operand:HI 0 "memory_operand" "")
+ (match_operand:HI 1 "general_operand" ""))]
+ "arm_arch4"
+ "
+ if (! s_register_operand (operands[1], HImode))
+ operands[1] = copy_to_mode_reg (HImode, operands[1]);
+")
+
(define_expand "movhi"
[(set (match_operand:HI 0 "general_operand" "")
(match_operand:HI 1 "general_operand" ""))]
{
if (GET_CODE (operands[0]) == MEM)
{
+ if (arm_arch4)
+ {
+ emit_insn (gen_storehi_single_op (operands[0], operands[1]));
+ DONE;
+ }
if (GET_CODE (operands[1]) == CONST_INT)
emit_insn (gen_storeinthi (XEXP (operands[0], 0), operands[1]));
else
emit_insn (gen_movsi (reg, GEN_INT (val)));
operands[1] = gen_rtx (SUBREG, HImode, reg, 0);
}
- else if (TARGET_SHORT_BY_BYTES && GET_CODE (operands[1]) == MEM)
- {
- rtx reg = gen_reg_rtx (SImode);
- emit_insn (gen_movhi_bytes (reg, operands[1]));
- operands[1] = gen_lowpart (HImode, reg);
- }
- else if (BYTES_BIG_ENDIAN && GET_CODE (operands[1]) == MEM)
+ else if (! arm_arch4)
{
- emit_insn (gen_movhi_bigend (operands[0], operands[1]));
- DONE;
+ if (TARGET_SHORT_BY_BYTES && GET_CODE (operands[1]) == MEM)
+ {
+ rtx reg = gen_reg_rtx (SImode);
+ emit_insn (gen_movhi_bytes (reg, operands[1]));
+ operands[1] = gen_lowpart (HImode, reg);
+ }
+ else if (BYTES_BIG_ENDIAN && GET_CODE (operands[1]) == MEM)
+ {
+ emit_insn (gen_movhi_bigend (operands[0], operands[1]));
+ DONE;
+ }
}
}
}
;; Pattern to recognise insn generated default case above
-(define_insn ""
+(define_insn "*movhi_insn_arch4"
+ [(set (match_operand:HI 0 "general_operand" "=r,r,r,m")
+ (match_operand:HI 1 "general_operand" "rI,K,m,r"))]
+ "arm_arch4
+ && (GET_CODE (operands[1]) != CONST_INT
+ || const_ok_for_arm (INTVAL (operands[1]))
+ || const_ok_for_arm (~INTVAL (operands[1])))"
+ "@
+ mov%?\\t%0, %1\\t%@ movhi
+ mvn%?\\t%0, #%B1\\t%@ movhi
+ ldr%?h\\t%0, %1\\t%@ movhi
+ str%?h\\t%1, %0\\t%@ movhi"
+[(set_attr "type" "*,*,load,store1")])
+
+(define_insn "*movhi_insn_littleend"
[(set (match_operand:HI 0 "general_operand" "=r,r,r")
(match_operand:HI 1 "general_operand" "rI,K,m"))]
- "! BYTES_BIG_ENDIAN
+ "! arm_arch4
+ && ! BYTES_BIG_ENDIAN
&& ! TARGET_SHORT_BY_BYTES
&& (GET_CODE (operands[1]) != CONST_INT
|| const_ok_for_arm (INTVAL (operands[1]))
ldr%?\\t%0, %1\\t%@ movhi"
[(set_attr "type" "*,*,load")])
-(define_insn ""
+(define_insn "*movhi_insn_bigend"
[(set (match_operand:HI 0 "s_register_operand" "=r,r,r")
(match_operand:HI 1 "general_operand" "rI,K,m"))]
- "BYTES_BIG_ENDIAN
+ "! arm_arch4
+ && BYTES_BIG_ENDIAN
&& ! TARGET_SHORT_BY_BYTES
&& (GET_CODE (operands[1]) != CONST_INT
|| const_ok_for_arm (INTVAL (operands[1]))
[(set_attr "type" "*,*,load")
(set_attr "length" "4,4,8")])
-(define_insn ""
+(define_insn "*loadhi_si_bigend"
[(set (match_operand:SI 0 "s_register_operand" "=r")
(rotate:SI (subreg:SI (match_operand:HI 1 "memory_operand" "m") 0)
(const_int 16)))]
"ldr%?\\t%0, %1\\t%@ movhi_bigend"
[(set_attr "type" "load")])
-(define_insn ""
+(define_insn "*movhi_bytes"
[(set (match_operand:HI 0 "s_register_operand" "=r,r")
(match_operand:HI 1 "arm_rhs_operand" "rI,K"))]
"TARGET_SHORT_BY_BYTES"
")
-(define_insn ""
+(define_insn "*movqi_insn"
[(set (match_operand:QI 0 "general_operand" "=r,r,r,m")
(match_operand:QI 1 "general_operand" "rI,K,m,r"))]
"register_operand (operands[0], QImode)
(match_operand:SF 1 "general_operand" ""))]
""
"
- if (GET_CODE (operands[1]) == CONST_DOUBLE
- && (TARGET_SOFT_FLOAT
- || (GET_CODE (operands[0]) == REG
- && REGNO (operands[0]) < 16)
- || ! (const_double_rtx_ok_for_fpu (operands[1])
- || neg_const_double_rtx_ok_for_fpu (operands[1]))))
- {
- extern int optimize;
- rtx mem = force_const_mem (SFmode, operands[1]);
- rtx addr;
-
- if (reload_in_progress || reload_completed)
- addr = gen_rtx (REG, SImode, REGNO (operands[0]));
- else
- addr = gen_reg_rtx (SImode);
- if (optimize == 0)
- {
- rtx ptr = force_const_mem (SImode, XEXP (mem, 0));
- emit_insn (gen_movsi (addr, ptr));
- }
- else
- emit_insn (gen_movsi (addr, XEXP (mem, 0)));
- operands[1] = gen_rtx (MEM, SFmode, addr);
- }
if (GET_CODE (operands[0]) == MEM)
operands[1] = force_reg (SFmode, operands[1]);
")
-(define_insn ""
+(define_insn "*movsf_hard_insn"
[(set (match_operand:SF 0 "general_operand" "=f,f,f,m,f,r,r,r,m")
- (match_operand:SF 1 "general_operand" "fG,H,m,f,r,f,r,m,r"))]
+ (match_operand:SF 1 "general_operand" "fG,H,mE,f,r,f,r,mE,r"))]
"TARGET_HARD_FLOAT
&& (GET_CODE (operands[0]) != MEM || register_operand (operands[1], SFmode))"
"@
(define_insn "*movsf_soft_insn"
[(set (match_operand:SF 0 "general_operand" "=r,r,m")
- (match_operand:SF 1 "general_operand" "r,m,r"))]
+ (match_operand:SF 1 "general_operand" "r,mE,r"))]
"TARGET_SOFT_FLOAT
&& (GET_CODE (operands[0]) != MEM || register_operand (operands[1], SFmode))"
"@
(match_operand:DF 1 "general_operand" ""))]
""
"
- if (GET_CODE (operands[1]) == CONST_DOUBLE
- && (TARGET_SOFT_FLOAT
- || (GET_CODE (operands[0]) == REG
- && REGNO (operands[0]) < 16)
- || ! (const_double_rtx_ok_for_fpu (operands[1])
- || neg_const_double_rtx_ok_for_fpu (operands[1]))))
- {
- extern int optimize;
- rtx mem = force_const_mem (DFmode, operands[1]);
- rtx addr;
-
- if (reload_in_progress || reload_completed)
- addr = gen_rtx (REG, SImode, REGNO (operands[0]));
- else
- addr = gen_reg_rtx (SImode);
- if (optimize == 0)
- {
- rtx ptr = force_const_mem (SImode, XEXP (mem, 0));
- emit_insn (gen_movsi (addr, ptr));
- }
- else
- emit_insn (gen_movsi (addr, XEXP (mem, 0)));
- operands[1] = gen_rtx (MEM, DFmode, addr);
- }
if (GET_CODE (operands[0]) == MEM)
operands[1] = force_reg (DFmode, operands[1]);
")
(match_operand:SI 2 "s_register_operand" "=&r")]
""
"
- if (GET_CODE (XEXP (operands[0], 0)) == REG)
+{
+ enum rtx_code code = GET_CODE (XEXP (operands[0], 0));
+
+ if (code == REG)
operands[2] = XEXP (operands[0], 0);
+ else if (code == POST_INC || code == PRE_DEC)
+ {
+ operands[0] = gen_rtx (SUBREG, DImode, operands[0], 0);
+ operands[1] = gen_rtx (SUBREG, DImode, operands[1], 0);
+ emit_insn (gen_movdi (operands[0], operands[1]));
+ DONE;
+ }
+ else if (code == PRE_INC)
+ {
+ rtx reg = XEXP (XEXP (operands[0], 0), 0);
+ emit_insn (gen_addsi3 (reg, reg, GEN_INT (8)));
+ operands[2] = reg;
+ }
+ else if (code == POST_DEC)
+ operands[2] = XEXP (XEXP (operands[0], 0), 0);
else
emit_insn (gen_addsi3 (operands[2], XEXP (XEXP (operands[0], 0), 0),
XEXP (XEXP (operands[0], 0), 1)));
+
emit_insn (gen_rtx (SET, VOIDmode, gen_rtx (MEM, DFmode, operands[2]),
operands[1]));
+
+ if (code == POST_DEC)
+ emit_insn (gen_addsi3 (operands[2], operands[2], GEN_INT (-8)));
+
DONE;
+}
")
-(define_insn ""
- [(set (match_operand:DF 0 "general_operand" "=r,Q#m,r,f,f,f,f,m,!f,!r,r")
- (match_operand:DF 1 "general_operand"
- "Q,r,?o,?f,!G,!H,m,f,r,f,??r"))]
+(define_insn "*movdf_hard_insn"
+ [(set (match_operand:DF 0 "general_operand" "=r,Q,r,m,r,f,f,f,m,!f,!r")
+ (match_operand:DF 1 "general_operand" "Q,r,r,r,mF,fG,H,mF,f,r,f"))]
"TARGET_HARD_FLOAT
- && (GET_CODE (operands[0]) != MEM || register_operand (operands[1], DFmode))"
+ && (GET_CODE (operands[0]) != MEM
+ || register_operand (operands[1], DFmode))"
"*
{
rtx ops[3];
switch (which_alternative)
{
- case 0:
- return \"ldm%?ia\\t%m1, {%0, %R0}\\t%@ double\";
-
- case 1:
- return \"stm%?ia\\t%m0, {%1, %R1}\\t%@ double\";
-
- case 2:
- ops[0] = operands[0];
- ops[1] = XEXP (XEXP (operands[1], 0), 0);
- ops[2] = XEXP (XEXP (operands[1], 0), 1);
- if (!INTVAL (ops[2]) || const_ok_for_arm (INTVAL (ops[2])))
- output_asm_insn (\"add%?\\t%0, %1, %2\", ops);
- else
- output_asm_insn (\"sub%?\\t%0, %1, #%n2\", ops);
- return \"ldm%?ia\\t%0, {%0, %R0}\\t%@ double\";
-
- case 3:
- case 4:
- return \"mvf%?d\\t%0, %1\";
-
- case 5: return \"mnf%?d\\t%0, #%N1\";
- case 6: return \"ldf%?d\\t%0, %1\";
- case 7: return \"stf%?d\\t%1, %0\";
- case 8: return output_mov_double_fpu_from_arm (operands);
- case 9: return output_mov_double_arm_from_fpu (operands);
- case 10: return output_move_double (operands);
+ case 0: return \"ldm%?ia\\t%m1, {%0, %R0}\\t%@ double\";
+ case 1: return \"stm%?ia\\t%m0, {%1, %R1}\\t%@ double\";
+ case 2: case 3: case 4: return output_move_double (operands);
+ case 5: return \"mvf%?d\\t%0, %1\";
+ case 6: return \"mnf%?d\\t%0, #%N1\";
+ case 7: return \"ldf%?d\\t%0, %1\";
+ case 8: return \"stf%?d\\t%1, %0\";
+ case 9: return output_mov_double_fpu_from_arm (operands);
+ case 10: return output_mov_double_arm_from_fpu (operands);
}
}
"
-[(set_attr "length" "4,4,8,4,4,4,4,4,8,8,8")
- (set_attr "type"
-"load,store2,load,ffarith,ffarith,ffarith,f_load,f_store,r_mem_f,f_mem_r,*")])
+[(set_attr "length" "4,4,8,8,8,4,4,4,4,8,8")
+ (set_attr "type"
+"load,store2,*,store2,load,ffarith,ffarith,f_load,f_store,r_mem_f,f_mem_r")])
;; Software floating point version. This is essentially the same as movdi.
;; Do not use `f' as a constraint to prevent reload from ever trying to use
;; an `f' reg.
(define_insn "*movdf_soft_insn"
- [(set (match_operand:DF 0 "soft_df_operand" "=r,r,o<>,r")
- (match_operand:DF 1 "soft_df_operand" "r,o<>,r,F"))]
+ [(set (match_operand:DF 0 "soft_df_operand" "=r,r,m")
+ (match_operand:DF 1 "soft_df_operand" "r,mF,r"))]
"TARGET_SOFT_FLOAT"
"* return output_move_double (operands);"
-[(set_attr "length" "8,8,8,32")
- (set_attr "type" "*,load,store2,*")])
+[(set_attr "length" "8,8,8")
+ (set_attr "type" "*,load,store2")])
(define_expand "movxf"
[(set (match_operand:XF 0 "general_operand" "")
;; Even when the XFmode patterns aren't enabled, we enable this after
;; reloading so that we can push floating point registers in the prologue.
-(define_insn ""
+(define_insn "*movxf_hard_insn"
[(set (match_operand:XF 0 "general_operand" "=f,f,f,m,f,r,r")
(match_operand:XF 1 "general_operand" "fG,H,m,f,r,f,r"))]
"TARGET_HARD_FLOAT && (ENABLE_XF_PATTERNS || reload_completed)"
;; Load multiple with write-back
-(define_insn ""
+(define_insn "*ldmsi_postinc"
[(match_parallel 0 "load_multiple_operation"
[(set (match_operand:SI 1 "s_register_operand" "+r")
(plus:SI (match_dup 1)
;; Ordinary load multiple
-(define_insn ""
+(define_insn "*ldmsi"
[(match_parallel 0 "load_multiple_operation"
[(set (match_operand:SI 1 "s_register_operand" "=r")
(match_operand:SI 2 "indirect_operand" "Q"))])]
;; Store multiple with write-back
-(define_insn ""
+(define_insn "*stmsi_postinc"
[(match_parallel 0 "store_multiple_operation"
[(set (match_operand:SI 1 "s_register_operand" "+r")
(plus:SI (match_dup 1)
;; Ordinary store multiple
-(define_insn ""
+(define_insn "*stmsi"
[(match_parallel 0 "store_multiple_operation"
[(set (match_operand:SI 2 "indirect_operand" "=Q")
(match_operand:SI 1 "s_register_operand" "r"))])]
}
")
-(define_insn ""
+(define_insn "*cmpsi_insn"
[(set (match_operand 0 "cc_register" "")
(compare (match_operand:SI 1 "s_register_operand" "r,r")
(match_operand:SI 2 "arm_add_operand" "rI,L")))]
cmn%?\\t%1, #%n2"
[(set_attr "conds" "set")])
-(define_insn ""
+(define_insn "*cmpsi_negsi"
[(set (match_operand 0 "cc_register" "")
(compare (match_operand:SI 1 "s_register_operand" "r")
(neg:SI (match_operand:SI 2 "s_register_operand" "r"))))]
"cmn%?\\t%1, %2"
[(set_attr "conds" "set")])
-(define_insn ""
+(define_insn "*cmpsi_shiftsi"
[(set (match_operand 0 "cc_register" "")
(compare (match_operand:SI 1 "s_register_operand" "r")
(match_operator:SI 2 "shift_operator"
"cmp%?\\t%1, %3%S2"
[(set_attr "conds" "set")])
-(define_insn ""
+(define_insn "*cmpsi_neg_shiftsi"
[(set (match_operand 0 "cc_register" "")
(compare (match_operand:SI 1 "s_register_operand" "r")
(neg:SI (match_operator:SI 2 "shift_operator"
"cmn%?\\t%1, %3%S2"
[(set_attr "conds" "set")])
-(define_insn ""
+(define_insn "*cmpsf_insn"
[(set (reg:CCFP 24)
(compare:CCFP (match_operand:SF 0 "s_register_operand" "f,f")
(match_operand:SF 1 "fpu_add_operand" "fG,H")))]
[(set_attr "conds" "set")
(set_attr "type" "f_2_r")])
-(define_insn ""
+(define_insn "*cmpdf_insn"
[(set (reg:CCFP 24)
(compare:CCFP (match_operand:DF 0 "s_register_operand" "f,f")
(match_operand:DF 1 "fpu_add_operand" "fG,H")))]
[(set_attr "conds" "set")
(set_attr "type" "f_2_r")])
-(define_insn ""
+(define_insn "*cmpesfdf_df"
[(set (reg:CCFP 24)
(compare:CCFP (float_extend:DF
(match_operand:SF 0 "s_register_operand" "f,f"))
[(set_attr "conds" "set")
(set_attr "type" "f_2_r")])
-(define_insn ""
+(define_insn "*cmpdf_esfdf"
[(set (reg:CCFP 24)
(compare:CCFP (match_operand:DF 0 "s_register_operand" "f")
(float_extend:DF
[(set_attr "conds" "set")
(set_attr "type" "f_2_r")])
-(define_insn ""
+(define_insn "*cmpxf_insn"
[(set (reg:CCFP 24)
(compare:CCFP (match_operand:XF 0 "s_register_operand" "f,f")
(match_operand:XF 1 "fpu_add_operand" "fG,H")))]
[(set_attr "conds" "set")
(set_attr "type" "f_2_r")])
-(define_insn ""
+(define_insn "*cmpsf_trap"
[(set (reg:CCFPE 24)
(compare:CCFPE (match_operand:SF 0 "s_register_operand" "f,f")
(match_operand:SF 1 "fpu_add_operand" "fG,H")))]
[(set_attr "conds" "set")
(set_attr "type" "f_2_r")])
-(define_insn ""
+(define_insn "*cmpdf_trap"
[(set (reg:CCFPE 24)
(compare:CCFPE (match_operand:DF 0 "s_register_operand" "f,f")
(match_operand:DF 1 "fpu_add_operand" "fG,H")))]
[(set_attr "conds" "set")
(set_attr "type" "f_2_r")])
-(define_insn ""
+(define_insn "*cmp_esfdf_df_trap"
[(set (reg:CCFPE 24)
(compare:CCFPE (float_extend:DF
(match_operand:SF 0 "s_register_operand" "f,f"))
[(set_attr "conds" "set")
(set_attr "type" "f_2_r")])
-(define_insn ""
+(define_insn "*cmp_df_esfdf_trap"
[(set (reg:CCFPE 24)
(compare:CCFPE (match_operand:DF 0 "s_register_operand" "f")
(float_extend:DF
[(set_attr "conds" "set")
(set_attr "type" "f_2_r")])
-(define_insn ""
+(define_insn "*cmpxf_trap"
[(set (reg:CCFPE 24)
(compare:CCFPE (match_operand:XF 0 "s_register_operand" "f,f")
(match_operand:XF 1 "fpu_add_operand" "fG,H")))]
; mode changes of the condition codes aren't lost by this even though we don't
; specify what they are.
-(define_insn ""
+(define_insn "*delted_compare"
[(set (match_operand 0 "cc_register" "") (match_dup 0))]
""
"\\t%@ deleted compare"
;; patterns to match conditional branch insns
-(define_insn ""
+(define_insn "*condbranch"
[(set (pc)
(if_then_else (match_operator 1 "comparison_operator"
[(reg 24) (const_int 0)])
}"
[(set_attr "conds" "use")])
-(define_insn ""
+(define_insn "*condbranch_reversed"
[(set (pc)
(if_then_else (match_operator 1 "comparison_operator"
[(reg 24) (const_int 0)])
}
")
-(define_insn ""
+(define_insn "*mov_scc"
[(set (match_operand:SI 0 "s_register_operand" "=r")
(match_operator:SI 1 "comparison_operator" [(reg 24) (const_int 0)]))]
""
[(set_attr "conds" "use")
(set_attr "length" "8")])
-(define_insn ""
+(define_insn "*mov_negscc"
[(set (match_operand:SI 0 "s_register_operand" "=r")
(neg:SI (match_operator:SI 1 "comparison_operator"
[(reg 24) (const_int 0)])))]
[(set_attr "conds" "use")
(set_attr "length" "8")])
-(define_insn ""
+(define_insn "*mov_notscc"
[(set (match_operand:SI 0 "s_register_operand" "=r")
(not:SI (match_operator:SI 1 "comparison_operator"
[(reg 24) (const_int 0)])))]
""
"")
-(define_insn ""
+(define_insn "*call_reg"
[(call (mem:SI (match_operand:SI 0 "s_register_operand" "r"))
(match_operand 1 "" "g"))
(clobber (reg:SI 14))]
"*
return output_call (operands);
"
-[(set (attr "conds")
- (if_then_else (eq_attr "cpu" "arm6")
- (const_string "clob")
- (const_string "nocond")))
;; length is worst case, normally it is only two
- (set_attr "length" "12")
+[(set_attr "length" "12")
(set_attr "type" "call")])
-(define_insn ""
+(define_insn "*call_mem"
[(call (mem:SI (match_operand 0 "memory_operand" "m"))
(match_operand 1 "general_operand" "g"))
(clobber (reg:SI 14))]
"*
return output_call_mem (operands);
"
-[(set (attr "conds")
- (if_then_else (eq_attr "cpu" "arm6")
- (const_string "clob")
- (const_string "nocond")))
- (set_attr "length" "12")
+[(set_attr "length" "12")
(set_attr "type" "call")])
(define_expand "call_value"
""
"")
-(define_insn ""
+(define_insn "*call_value_reg"
[(set (match_operand 0 "" "=rf")
(call (mem:SI (match_operand:SI 1 "s_register_operand" "r"))
(match_operand 2 "general_operand" "g")))
"*
return output_call (&operands[1]);
"
-[(set (attr "conds")
- (if_then_else (eq_attr "cpu" "arm6")
- (const_string "clob")
- (const_string "nocond")))
- (set_attr "length" "12")
+[(set_attr "length" "12")
(set_attr "type" "call")])
-(define_insn ""
+(define_insn "*call_value_mem"
[(set (match_operand 0 "" "=rf")
(call (mem:SI (match_operand 1 "memory_operand" "m"))
(match_operand 2 "general_operand" "g")))
"*
return output_call_mem (&operands[1]);
"
-[(set (attr "conds")
- (if_then_else (eq_attr "cpu" "arm6")
- (const_string "clob")
- (const_string "nocond")))
- (set_attr "length" "12")
+[(set_attr "length" "12")
(set_attr "type" "call")])
;; Allow calls to SYMBOL_REFs specially as they are not valid general addresses
;; The 'a' causes the operand to be treated as an address, i.e. no '#' output.
-(define_insn ""
- [(call (mem:SI (match_operand:SI 0 "" "i"))
+(define_insn "*call_symbol"
+ [(call (mem:SI (match_operand:SI 0 "" "X"))
(match_operand:SI 1 "general_operand" "g"))
(clobber (reg:SI 14))]
"GET_CODE (operands[0]) == SYMBOL_REF"
"bl%?\\t%a0"
-[(set (attr "conds")
- (if_then_else (eq_attr "cpu" "arm6")
- (const_string "clob")
- (const_string "nocond")))
- (set_attr "type" "call")])
+[(set_attr "type" "call")])
-(define_insn ""
+(define_insn "*call_value_symbol"
[(set (match_operand 0 "s_register_operand" "=rf")
- (call (mem:SI (match_operand:SI 1 "" "i"))
+ (call (mem:SI (match_operand:SI 1 "" "X"))
(match_operand:SI 2 "general_operand" "g")))
(clobber (reg:SI 14))]
"GET_CODE(operands[1]) == SYMBOL_REF"
"bl%?\\t%a1"
-[(set (attr "conds")
- (if_then_else (eq_attr "cpu" "arm6")
- (const_string "clob")
- (const_string "nocond")))
- (set_attr "type" "call")])
+[(set_attr "type" "call")])
;; Often the return insn will be the same as loading from memory, so set attr
(define_insn "return"
}"
[(set_attr "type" "load")])
-(define_insn ""
+(define_insn "*cond_return"
[(set (pc)
(if_then_else (match_operator 0 "comparison_operator"
[(reg 24) (const_int 0)])
[(set_attr "conds" "use")
(set_attr "type" "load")])
-(define_insn ""
+(define_insn "*cond_return_inverted"
[(set (pc)
(if_then_else (match_operator 0 "comparison_operator"
[(reg 24) (const_int 0)])
[(set_attr "length" "0")
(set_attr "type" "block")])
-(define_insn "tablejump"
- [(set (pc)
- (match_operand:SI 0 "s_register_operand" "r"))
- (use (label_ref (match_operand 1 "" "")))]
+(define_expand "casesi"
+ [(match_operand:SI 0 "s_register_operand" "") ; index to jump on
+ (match_operand:SI 1 "immediate_operand" "") ; lower bound
+ (match_operand:SI 2 "immediate_operand" "") ; total range
+ (match_operand:SI 3 "" "") ; table label
+ (match_operand:SI 4 "" "")] ; Out of range label
""
- "mov%?\\t%|pc, %0\\t%@ table jump, label %l1")
+ "
+{
+ rtx reg;
+ if (operands[1] != const0_rtx)
+ {
+ reg = gen_reg_rtx (SImode);
+ emit_insn (gen_addsi3 (reg, operands[0],
+ GEN_INT (-INTVAL (operands[1]))));
+ operands[0] = reg;
+ }
+
+ if (! const_ok_for_arm (INTVAL (operands[2])))
+ operands[2] = force_reg (SImode, operands[2]);
-(define_insn ""
+ emit_jump_insn (gen_casesi_internal (operands[0], operands[2], operands[3],
+ operands[4]));
+ DONE;
+}")
+
+(define_insn "casesi_internal"
[(set (pc)
- (match_operand:SI 0 "memory_operand" "m"))
- (use (label_ref (match_operand 1 "" "")))]
+ (if_then_else
+ (leu (match_operand:SI 0 "s_register_operand" "r")
+ (match_operand:SI 1 "arm_rhs_operand" "rI"))
+ (mem:SI (plus:SI (mult:SI (match_dup 0) (const_int 4))
+ (label_ref (match_operand 2 "" ""))))
+ (label_ref (match_operand 3 "" ""))))]
""
- "ldr%?\\t%|pc, %0\\t%@ table jump, label %l1"
-[(set_attr "type" "load")])
+ "*
+ if (flag_pic)
+ return \"cmp\\t%0, %1\;addls\\t%|pc, %|pc, %0, asl #2\;b\\t%l3\";
+ return \"cmp\\t%0, %1\;ldrls\\t%|pc, [%|pc, %0, asl #2]\;b\\t%l3\";
+"
+[(set_attr "conds" "clob")
+ (set_attr "length" "12")])
(define_insn "indirect_jump"
[(set (pc)
""
"mov%?\\t%|pc, %0\\t%@ indirect jump")
-(define_insn ""
+(define_insn "*load_indirect_jump"
[(set (pc)
(match_operand:SI 0 "memory_operand" "m"))]
""
\f
;; Patterns to allow combination of arithmetic, cond code and shifts
-(define_insn ""
+(define_insn "*arith_shiftsi"
[(set (match_operand:SI 0 "s_register_operand" "=r")
(match_operator:SI 1 "shiftable_operator"
[(match_operator:SI 3 "shift_operator"
""
"%i1%?\\t%0, %2, %4%S3")
-(define_insn ""
+(define_insn "*arith_shiftsi_compare0"
[(set (reg:CC_NOOV 24)
(compare:CC_NOOV (match_operator:SI 1 "shiftable_operator"
[(match_operator:SI 3 "shift_operator"
"%i1%?s\\t%0, %2, %4%S3"
[(set_attr "conds" "set")])
-(define_insn ""
+(define_insn "*arith_shiftsi_compare0_scratch"
[(set (reg:CC_NOOV 24)
(compare:CC_NOOV (match_operator:SI 1 "shiftable_operator"
[(match_operator:SI 3 "shift_operator"
"%i1%?s\\t%0, %2, %4%S3"
[(set_attr "conds" "set")])
-(define_insn ""
+(define_insn "*sub_shiftsi"
[(set (match_operand:SI 0 "s_register_operand" "=r")
(minus:SI (match_operand:SI 1 "s_register_operand" "r")
(match_operator:SI 2 "shift_operator"
""
"sub%?\\t%0, %1, %3%S2")
-(define_insn ""
+(define_insn "*sub_shiftsi_compare0"
[(set (reg:CC_NOOV 24)
(compare:CC_NOOV
(minus:SI (match_operand:SI 1 "s_register_operand" "r")
"sub%?s\\t%0, %1, %3%S2"
[(set_attr "conds" "set")])
-(define_insn ""
+(define_insn "*sub_shiftsi_compare0_scratch"
[(set (reg:CC_NOOV 24)
(compare:CC_NOOV
(minus:SI (match_operand:SI 1 "s_register_operand" "r")
;; how to reload pseudos that haven't got hard registers; the constraints will
;; sort everything out.
-(define_insn ""
+(define_insn "*reload_mulsi3"
[(set (match_operand:SI 0 "" "=&r")
(plus:SI (plus:SI (match_operator:SI 5 "shift_operator"
[(match_operand:SI 3 "" "r")
; we have no idea how long the add_immediate is, it could be up to 4.
[(set_attr "length" "20")])
-(define_insn ""
+(define_insn "*relaod_mulsi_compare0"
[(set (reg:CC_NOOV 24)
(compare:CC_NOOV (plus:SI
(plus:SI
[(set_attr "conds" "set")
(set_attr "length" "20")])
-(define_insn ""
+(define_insn "*reload_mulsi_compare0_scratch"
[(set (reg:CC_NOOV 24)
(compare:CC_NOOV (plus:SI
(plus:SI
;; These are similar, but are needed when the mla pattern contains the
;; eliminated register as operand 3.
-(define_insn ""
+(define_insn "*reload_muladdsi"
[(set (match_operand:SI 0 "" "=&r,&r")
(plus:SI (plus:SI (mult:SI (match_operand:SI 1 "" "%0,r")
(match_operand:SI 2 "" "r,r"))
operands[1] = operands[0];
return output_add_immediate (operands);
"
-[(set_attr "length" "20")])
+[(set_attr "length" "20")
+ (set_attr "type" "mult")])
-(define_insn ""
+(define_insn "*reload_muladdsi_compare0"
[(set (reg:CC_NOOV 24)
(compare:CC_NOOV (plus:SI (plus:SI (mult:SI
(match_operand:SI 3 "" "r")
return \"\";
"
[(set_attr "length" "20")
- (set_attr "conds" "set")])
+ (set_attr "conds" "set")
+ (set_attr "type" "mult")])
-(define_insn ""
+(define_insn "*reload_muladdsi_compare0_scratch"
[(set (reg:CC_NOOV 24)
(compare:CC_NOOV (plus:SI (plus:SI (mult:SI
(match_operand:SI 3 "" "r")
return \"mla%?s\\t%0, %3, %4, %0\";
"
[(set_attr "length" "20")
- (set_attr "conds" "set")])
-
+ (set_attr "conds" "set")
+ (set_attr "type" "mult")])
\f
-(define_insn ""
+(define_insn "*and_scc"
[(set (match_operand:SI 0 "s_register_operand" "=r")
(and:SI (match_operator 1 "comparison_operator"
[(match_operand 3 "reversible_cc_register" "") (const_int 0)])
[(set_attr "conds" "use")
(set_attr "length" "8")])
-(define_insn ""
+(define_insn "*ior_scc"
[(set (match_operand:SI 0 "s_register_operand" "=r,r")
(ior:SI (match_operator 2 "comparison_operator"
[(reg 24) (const_int 0)])
[(set_attr "conds" "use")
(set_attr "length" "4,8")])
-(define_insn ""
+(define_insn "*compare_scc"
[(set (match_operand:SI 0 "s_register_operand" "=r,r")
(match_operator 1 "comparison_operator"
[(match_operand:SI 2 "s_register_operand" "r,r")
[(set_attr "conds" "clob")
(set_attr "length" "12")])
-(define_insn ""
+(define_insn "*ior_compare_compare"
[(set (match_operand:SI 0 "s_register_operand" "=&r")
(ior:SI (match_operator 1 "comparison_operator"
[(match_operand:SI 2 "s_register_operand" "r")
;; tell the final prescan branch eliminator code that full branch inlining
;; can't be done.
-(define_insn ""
+(define_insn "*impossible_cond_compare"
[(set (pc)
(if_then_else
(ne (ior:SI (match_operator 5 "comparison_operator"
[(set_attr "conds" "jump_clob")
(set_attr "length" "16")])
-(define_insn ""
+(define_insn "*condition_compare_ior"
[(set (reg:CC 24)
(compare:CC
(ior:CC (match_operator 4 "comparison_operator"
[(set_attr "conds" "set")
(set_attr "length" "8")])
-(define_insn ""
+(define_insn "*cond_move"
[(set (match_operand:SI 0 "s_register_operand" "=r,r,r")
(if_then_else (match_operator 3 "equality_operator"
[(match_operator 4 "comparison_operator"
[(set_attr "conds" "use")
(set_attr "length" "4,4,8")])
-(define_insn ""
+(define_insn "*cond_arith"
[(set (match_operand:SI 0 "s_register_operand" "=r,r")
(match_operator:SI 5 "shiftable_operator"
[(match_operator:SI 4 "comparison_operator"
[(set_attr "conds" "clob")
(set_attr "length" "12")])
-(define_insn ""
+(define_insn "*cond_sub"
[(set (match_operand:SI 0 "s_register_operand" "=r,r")
(minus:SI (match_operand:SI 1 "s_register_operand" "0,?r")
(match_operator:SI 4 "comparison_operator"
[(set_attr "conds" "clob")
(set_attr "length" "8,12")])
-(define_insn ""
+(define_insn "*and_scc_scc"
[(set (match_operand:SI 0 "s_register_operand" "=&r")
(and:SI (match_operator 1 "comparison_operator"
[(match_operand:SI 2 "s_register_operand" "r")
;; tell the final prescan branch eliminator code that full branch inlining
;; can't be done.
-(define_insn ""
+(define_insn "*impossible_cond_branch_and"
[(set (pc)
(if_then_else
(eq (and:SI (match_operator 1 "comparison_operator"
[(set_attr "conds" "jump_clob")
(set_attr "length" "16")])
-(define_insn ""
+(define_insn "*negscc"
[(set (match_operand:SI 0 "s_register_operand" "=r")
(neg:SI (match_operator 3 "comparison_operator"
[(match_operand:SI 1 "s_register_operand" "r")
[(set_attr "conds" "clob")
(set_attr "length" "8,8,12")])
-(define_insn ""
+(define_insn "*ifcompare_arith_arith"
[(set (match_operand:SI 0 "s_register_operand" "=r,r")
(if_then_else:SI (match_operator 9 "comparison_operator"
[(match_operand:SI 5 "s_register_operand" "r,r")
[(set_attr "conds" "clob")
(set_attr "length" "12")])
-(define_insn ""
+(define_insn "*ifcompare_arith_move"
[(set (match_operand:SI 0 "s_register_operand" "=r,r")
(if_then_else:SI (match_operator 6 "comparison_operator"
[(match_operand:SI 2 "s_register_operand" "r,r")
[(set_attr "conds" "clob")
(set_attr "length" "8,12")])
-(define_insn ""
+(define_insn "*ifcompare_move_arith"
[(set (match_operand:SI 0 "s_register_operand" "=r,r")
(if_then_else:SI (match_operator 6 "comparison_operator"
[(match_operand:SI 4 "s_register_operand" "r,r")
[(set_attr "conds" "clob")
(set_attr "length" "8,12")])
-(define_insn ""
+(define_insn "*ifcompare_plus_move"
[(set (match_operand:SI 0 "s_register_operand" "=r,r")
(if_then_else:SI (match_operator 6 "comparison_operator"
[(match_operand:SI 4 "s_register_operand" "r,r")
[(set_attr "conds" "clob")
(set_attr "length" "8,12")])
-(define_insn ""
+(define_insn "*ifcompare_move_plus"
[(set (match_operand:SI 0 "s_register_operand" "=r,r")
(if_then_else:SI (match_operator 6 "comparison_operator"
[(match_operand:SI 4 "s_register_operand" "r,r")
[(set_attr "conds" "clob")
(set_attr "length" "8,12")])
-(define_insn ""
+(define_insn "ifcompare_move_not"
[(set (match_operand:SI 0 "s_register_operand" "=r,r")
(if_then_else:SI (match_operator 5 "comparison_operator"
[(match_operand:SI 3 "s_register_operand" "r,r")
[(set_attr "conds" "clob")
(set_attr "length" "8,12")])
-(define_insn ""
+(define_insn "*ifcompare_not_move"
[(set (match_operand:SI 0 "s_register_operand" "=r,r,r,r")
(if_then_else:SI
(match_operator 5 "comparison_operator"
[(set_attr "conds" "clob")
(set_attr "length" "8,8,12,12")])
-(define_insn ""
+(define_insn "*ifcompare_shift_move"
[(set (match_operand:SI 0 "s_register_operand" "=r,r,r,r")
(if_then_else:SI
(match_operator 6 "comparison_operator"
[(set_attr "conds" "clob")
(set_attr "length" "8,8,12,12")])
-(define_insn ""
+(define_insn "ifcompare_move_shift"
[(set (match_operand:SI 0 "s_register_operand" "=r,r,r,r")
(if_then_else:SI
(match_operator 6 "comparison_operator"
[(set_attr "conds" "clob")
(set_attr "length" "8,8,12,12")])
-(define_insn ""
+(define_insn "*ifcompare_shift_shift"
[(set (match_operand:SI 0 "s_register_operand" "=r,r")
(if_then_else:SI
(match_operator 7 "comparison_operator"
[(set_attr "conds" "clob")
(set_attr "length" "12")])
-(define_insn ""
+(define_insn "*ifcompare_not_arith"
[(set (match_operand:SI 0 "s_register_operand" "=r,r")
(if_then_else:SI
(match_operator 6 "comparison_operator"
[(set_attr "conds" "clob")
(set_attr "length" "12")])
-(define_insn ""
+(define_insn "*if_compare_arith_not"
[(set (match_operand:SI 0 "s_register_operand" "=r,r")
(if_then_else:SI
(match_operator 6 "comparison_operator"
[(set_attr "conds" "clob")
(set_attr "length" "12")])
-(define_insn ""
+(define_insn "*ifcompare_neg_move"
[(set (match_operand:SI 0 "s_register_operand" "=r,r,r,r")
(if_then_else:SI
(match_operator 5 "comparison_operator"
[(set_attr "conds" "clob")
(set_attr "length" "8,8,12,12")])
-(define_insn ""
+(define_insn "*ifcompare_move_neg"
[(set (match_operand:SI 0 "s_register_operand" "=r,r,r,r")
(if_then_else:SI
(match_operator 5 "comparison_operator"
[(set_attr "conds" "clob")
(set_attr "length" "8,8,12,12")])
-(define_insn ""
+(define_insn "*arith_adjacentmem"
[(set (match_operand:SI 0 "s_register_operand" "=r")
(match_operator:SI 1 "shiftable_operator"
[(match_operand:SI 2 "memory_operand" "m")
;; We reject the frame pointer if it occurs anywhere in these patterns since
;; elimination will cause too many headaches.
-(define_insn ""
+(define_insn "*strqi_preinc"
[(set (mem:QI (plus:SI (match_operand:SI 1 "s_register_operand" "%0")
(match_operand:SI 2 "index_operand" "rJ")))
(match_operand:QI 3 "s_register_operand" "r"))
"str%?b\\t%3, [%0, %2]!"
[(set_attr "type" "store1")])
-(define_insn ""
+(define_insn "*strqi_predec"
[(set (mem:QI (minus:SI (match_operand:SI 1 "s_register_operand" "0")
(match_operand:SI 2 "s_register_operand" "r")))
(match_operand:QI 3 "s_register_operand" "r"))
"str%?b\\t%3, [%0, -%2]!"
[(set_attr "type" "store1")])
-(define_insn ""
+(define_insn "*loadqi_preinc"
[(set (match_operand:QI 3 "s_register_operand" "=r")
(mem:QI (plus:SI (match_operand:SI 1 "s_register_operand" "%0")
(match_operand:SI 2 "index_operand" "rJ"))))
"ldr%?b\\t%3, [%0, %2]!"
[(set_attr "type" "load")])
-(define_insn ""
+(define_insn "*loadqi_predec"
[(set (match_operand:QI 3 "s_register_operand" "=r")
(mem:QI (minus:SI (match_operand:SI 1 "s_register_operand" "0")
(match_operand:SI 2 "s_register_operand" "r"))))
"ldr%?b\\t%3, [%0, -%2]!"
[(set_attr "type" "load")])
-(define_insn ""
+(define_insn "*loadqisi_preinc"
[(set (match_operand:SI 3 "s_register_operand" "=r")
(zero_extend:SI
(mem:QI (plus:SI (match_operand:SI 1 "s_register_operand" "%0")
"ldr%?b\\t%3, [%0, %2]!\\t%@ z_extendqisi"
[(set_attr "type" "load")])
-(define_insn ""
+(define_insn "*loadqisi_predec"
[(set (match_operand:SI 3 "s_register_operand" "=r")
(zero_extend:SI
(mem:QI (minus:SI (match_operand:SI 1 "s_register_operand" "0")
"ldr%?b\\t%3, [%0, -%2]!\\t%@ z_extendqisi"
[(set_attr "type" "load")])
-(define_insn ""
+(define_insn "*strsi_preinc"
[(set (mem:SI (plus:SI (match_operand:SI 1 "s_register_operand" "%0")
(match_operand:SI 2 "index_operand" "rJ")))
(match_operand:SI 3 "s_register_operand" "r"))
"str%?\\t%3, [%0, %2]!"
[(set_attr "type" "store1")])
-(define_insn ""
+(define_insn "*strqi_predec"
[(set (mem:SI (minus:SI (match_operand:SI 1 "s_register_operand" "0")
(match_operand:SI 2 "s_register_operand" "r")))
(match_operand:SI 3 "s_register_operand" "r"))
"str%?\\t%3, [%0, -%2]!"
[(set_attr "type" "store1")])
-(define_insn ""
+(define_insn "*loadsi_preinc"
[(set (match_operand:SI 3 "s_register_operand" "=r")
(mem:SI (plus:SI (match_operand:SI 1 "s_register_operand" "%0")
(match_operand:SI 2 "index_operand" "rJ"))))
"ldr%?\\t%3, [%0, %2]!"
[(set_attr "type" "load")])
-(define_insn ""
+(define_insn "*loadsi_predec"
[(set (match_operand:SI 3 "s_register_operand" "=r")
(mem:SI (minus:SI (match_operand:SI 1 "s_register_operand" "0")
(match_operand:SI 2 "s_register_operand" "r"))))
"ldr%?\\t%3, [%0, -%2]!"
[(set_attr "type" "load")])
-(define_insn ""
+(define_insn "*loadhi_preinc"
[(set (match_operand:HI 3 "s_register_operand" "=r")
(mem:HI (plus:SI (match_operand:SI 1 "s_register_operand" "%0")
(match_operand:SI 2 "index_operand" "rJ"))))
"ldr%?\\t%3, [%0, %2]!\\t%@ loadhi"
[(set_attr "type" "load")])
-(define_insn ""
+(define_insn "*loadhi_predec"
[(set (match_operand:HI 3 "s_register_operand" "=r")
(mem:HI (minus:SI (match_operand:SI 1 "s_register_operand" "0")
(match_operand:SI 2 "s_register_operand" "r"))))
"ldr%?\\t%3, [%0, -%2]!\\t%@ loadhi"
[(set_attr "type" "load")])
-(define_insn ""
+(define_insn "*strqi_shiftpreinc"
[(set (mem:QI (plus:SI (match_operator:SI 2 "shift_operator"
[(match_operand:SI 3 "s_register_operand" "r")
(match_operand:SI 4 "const_shift_operand" "n")])
"str%?b\\t%5, [%0, %3%S2]!"
[(set_attr "type" "store1")])
-(define_insn ""
+(define_insn "*strqi_shiftpredec"
[(set (mem:QI (minus:SI (match_operand:SI 1 "s_register_operand" "0")
(match_operator:SI 2 "shift_operator"
[(match_operand:SI 3 "s_register_operand" "r")
"str%?b\\t%5, [%0, -%3%S2]!"
[(set_attr "type" "store1")])
-(define_insn ""
+(define_insn "*loadqi_shiftpreinc"
[(set (match_operand:QI 5 "s_register_operand" "=r")
(mem:QI (plus:SI (match_operator:SI 2 "shift_operator"
[(match_operand:SI 3 "s_register_operand" "r")
"ldr%?b\\t%5, [%0, %3%S2]!"
[(set_attr "type" "load")])
-(define_insn ""
+(define_insn "*loadqi_shiftpredec"
[(set (match_operand:QI 5 "s_register_operand" "=r")
(mem:QI (minus:SI (match_operand:SI 1 "s_register_operand" "0")
(match_operator:SI 2 "shift_operator"
"ldr%?b\\t%5, [%0, -%3%S2]!"
[(set_attr "type" "load")])
-(define_insn ""
+(define_insn "*strsi_shiftpreinc"
[(set (mem:SI (plus:SI (match_operator:SI 2 "shift_operator"
[(match_operand:SI 3 "s_register_operand" "r")
(match_operand:SI 4 "const_shift_operand" "n")])
"str%?\\t%5, [%0, %3%S2]!"
[(set_attr "type" "store1")])
-(define_insn ""
+(define_insn "*strsi_shiftpredec"
[(set (mem:SI (minus:SI (match_operand:SI 1 "s_register_operand" "0")
(match_operator:SI 2 "shift_operator"
[(match_operand:SI 3 "s_register_operand" "r")
"str%?\\t%5, [%0, -%3%S2]!"
[(set_attr "type" "store1")])
-(define_insn ""
+(define_insn "*loadqi_shiftpreinc"
[(set (match_operand:SI 5 "s_register_operand" "=r")
(mem:SI (plus:SI (match_operator:SI 2 "shift_operator"
[(match_operand:SI 3 "s_register_operand" "r")
"ldr%?\\t%5, [%0, %3%S2]!"
[(set_attr "type" "load")])
-(define_insn ""
+(define_insn "*loadqi_shiftpredec"
[(set (match_operand:SI 5 "s_register_operand" "=r")
(mem:SI (minus:SI (match_operand:SI 1 "s_register_operand" "0")
(match_operator:SI 2 "shift_operator"
"ldr%?\\t%5, [%0, -%3%S2]!"
[(set_attr "type" "load")])
-(define_insn ""
+(define_insn "*loadhi_shiftpreinc"
[(set (match_operand:HI 5 "s_register_operand" "=r")
(mem:HI (plus:SI (match_operator:SI 2 "shift_operator"
[(match_operand:SI 3 "s_register_operand" "r")
"ldr%?\\t%5, [%0, %3%S2]!\\t%@ loadhi"
[(set_attr "type" "load")])
-(define_insn ""
+(define_insn "*loadhi_shiftpredec"
[(set (match_operand:HI 5 "s_register_operand" "=r")
(mem:HI (minus:SI (match_operand:SI 1 "s_register_operand" "0")
(match_operator:SI 2 "shift_operator"
;; calculations.
(define_peephole
- [(parallel [(call (mem:SI (match_operand:SI 0 "" "i"))
+ [(parallel [(call (mem:SI (match_operand:SI 0 "" "X"))
(match_operand:SI 1 "general_operand" "g"))
(clobber (reg:SI 14))])
(return)]
output_return_instruction (NULL, FALSE);
return \"b%?\\t%a0\";
}"
-[(set (attr "conds")
- (if_then_else (eq_attr "cpu" "arm6")
- (const_string "clob")
- (const_string "nocond")))
+[(set_attr "type" "call")
(set_attr "length" "8")])
(define_peephole
[(parallel [(set (match_operand 0 "s_register_operand" "=rf")
- (call (mem:SI (match_operand:SI 1 "" "i"))
+ (call (mem:SI (match_operand:SI 1 "" "X"))
(match_operand:SI 2 "general_operand" "g")))
(clobber (reg:SI 14))])
(return)]
output_return_instruction (NULL, FALSE);
return \"b%?\\t%a1\";
}"
-[(set (attr "conds")
- (if_then_else (eq_attr "cpu" "arm6")
- (const_string "clob")
- (const_string "nocond")))
+[(set_attr "type" "call")
(set_attr "length" "8")])
;; As above but when this function is not void, we must be returning the
(define_peephole
[(parallel [(set (match_operand 0 "s_register_operand" "=rf")
- (call (mem:SI (match_operand:SI 1 "" "i"))
+ (call (mem:SI (match_operand:SI 1 "" "X"))
(match_operand:SI 2 "general_operand" "g")))
(clobber (reg:SI 14))])
(use (match_dup 0))
output_return_instruction (NULL, FALSE);
return \"b%?\\t%a1\";
}"
-[(set (attr "conds")
- (if_then_else (eq_attr "cpu" "arm6")
- (const_string "clob")
- (const_string "nocond")))
+[(set_attr "type" "call")
(set_attr "length" "8")])
;; If calling a subroutine and then jumping back to somewhere else, but not
;; not this is possible, this is the same as the sparc does.
(define_peephole
- [(parallel[(call (mem:SI (match_operand:SI 0 "" "i"))
+ [(parallel[(call (mem:SI (match_operand:SI 0 "" "X"))
(match_operand:SI 1 "general_operand" "g"))
(clobber (reg:SI 14))])
(set (pc)
}
return \"b%?\\t%a0\";
}"
-[(set (attr "conds")
- (if_then_else (eq_attr "cpu" "arm6")
- (const_string "clob")
- (const_string "nocond")))
+[(set_attr "type" "call")
(set (attr "length")
- (if_then_else (eq_attr "cpu" "arm6")
+ (if_then_else (eq_attr "prog_mode" "prog32")
(const_int 8)
(const_int 12)))])
(define_peephole
[(parallel[(set (match_operand:SI 0 "s_register_operand" "=r")
- (call (mem:SI (match_operand:SI 1 "" "i"))
+ (call (mem:SI (match_operand:SI 1 "" "X"))
(match_operand:SI 2 "general_operand" "g")))
(clobber (reg:SI 14))])
(set (pc)
}
return \"b%?\\t%a1\";
}"
-[(set (attr "conds")
- (if_then_else (eq_attr "cpu" "arm6")
- (const_string "clob")
- (const_string "nocond")))
+[(set_attr "type" "call")
(set (attr "length")
- (if_then_else (eq_attr "cpu" "arm6")
+ (if_then_else (eq_attr "prog_mode" "prog32")
(const_int 8)
(const_int 12)))])
;; needed. Combine doesn't eliminate these because by the time it sees the
;; branch it no-longer knows that the data came from memory.
-(define_insn ""
+(define_insn "*loadqi_compare"
[(set (reg:CC_NOOV 24)
(compare:CC_NOOV
(ashift:SI (subreg:SI (match_operand:QI 0 "memory_operand" "m") 0)
")
-(define_insn ""
+(define_insn "*cond_move_not"
[(set (match_operand:SI 0 "s_register_operand" "=r,r")
(if_then_else:SI (match_operator 4 "comparison_operator"
[(match_operand 3 "reversible_cc_register" "")
;; The next two patterns occur when an AND operation is followed by a
;; scc insn sequence
-(define_insn ""
+(define_insn "*sign_extract_onebit"
[(set (match_operand:SI 0 "s_register_operand" "=r")
(sign_extract:SI (match_operand:SI 1 "s_register_operand" "r")
(const_int 1)
[(set_attr "conds" "clob")
(set_attr "length" "8")])
-(define_insn ""
+(define_insn "*not_signextract_onebit"
[(set (match_operand:SI 0 "s_register_operand" "=r")
(not:SI
(sign_extract:SI (match_operand:SI 1 "s_register_operand" "r")
;; Push multiple registers to the stack. The first register is in the
;; unspec part of the insn; subsequent registers are in parallel (use ...)
;; expressions.
-(define_insn ""
+(define_insn "*push_multi"
[(match_parallel 2 "multi_register_push"
[(set (match_operand:BLK 0 "memory_operand" "=m")
(unspec:BLK [(match_operand:SI 1 "s_register_operand" "r")] 2))])]
abort ();
return \"\";
}
- strcpy (pattern, \"stmfd\\t%m0!, {%|%1\");
+ strcpy (pattern, \"stmfd\\t%m0!, {%1\");
for (i = 1; i < XVECLEN (operands[2], 0); i++)
{
strcat (pattern, \", %|\");
return \"\";
}"
[(set_attr "type" "store4")])
+
+;; Special patterns for dealing with the constant pool
+
+(define_insn "consttable_4"
+ [(unspec_volatile [(match_operand 0 "" "")] 2)]
+ ""
+ "*
+{
+ switch (GET_MODE_CLASS (GET_MODE (operands[0])))
+ {
+ case MODE_FLOAT:
+ {
+ union real_extract u;
+ bcopy ((char *) &CONST_DOUBLE_LOW (operands[0]), (char *) &u, sizeof u);
+ assemble_real (u.d, GET_MODE (operands[0]));
+ break;
+ }
+ default:
+ assemble_integer (operands[0], 4, 1);
+ break;
+ }
+ return \"\";
+}"
+[(set_attr "length" "4")])
+
+(define_insn "consttable_8"
+ [(unspec_volatile [(match_operand 0 "" "")] 3)]
+ ""
+ "*
+{
+ switch (GET_MODE_CLASS (GET_MODE (operands[0])))
+ {
+ case MODE_FLOAT:
+ {
+ union real_extract u;
+ bcopy ((char *) &CONST_DOUBLE_LOW (operands[0]), (char *) &u, sizeof u);
+ assemble_real (u.d, GET_MODE (operands[0]));
+ break;
+ }
+ default:
+ assemble_integer (operands[0], 8, 1);
+ break;
+ }
+ return \"\";
+}"
+[(set_attr "length" "8")])
+
+(define_insn "consttable_end"
+ [(unspec_volatile [(const_int 0)] 4)]
+ ""
+ "*
+ text_section ();
+ return \"\";
+")
+
+(define_insn "align_4"
+ [(unspec_volatile [(const_int 0)] 5)]
+ ""
+ "*
+ readonly_data_section ();
+ assemble_align (32);
+ return \"\";
+")
git://gcc.gnu.org / gcc.git / commitdiff