pa.md (adddi3): For 32-bit targets...

	* pa.md (adddi3): For 32-bit targets, force constants to a register
	if they don't fit in an 11-bit immediate.  Change insn predicate to
	arith11_operand.  Remove comment.
	* pa.c (cint_ok_for_move): Fix comment.
	(emit_move_sequence):  Don't directly split DImode constants on 32-bit
	targets.

From-SVN: r55389

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index b94e96be382c35fce12ca9397df83e917c1c8ca8..711a231eed6bc82d1404174e77694791dc141f2f 100644 (file)
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,12 @@
+2002-07-11  John David Anglin  <dave@hiauly1.hia.nrc.ca>
+
+       * pa.md (adddi3): For 32-bit targets, force constants to a register
+       if they don't fit in an 11-bit immediate.  Change insn predicate to
+       arith11_operand.  Remove comment.
+       * pa.c (cint_ok_for_move): Fix comment.
+       (emit_move_sequence):  Don't directly split DImode constants on 32-bit
+       targets.
+
 2002-07-10  Roger Sayle  <roger@eyesopen.com>
 
        PR c/2454

diff --git a/gcc/config/pa/pa.c b/gcc/config/pa/pa.c
index 7661f596e935492ea247ff3d562d179b7a5055b5..c06a7b45215aaf390be438e33cde92d601215abc 100644 (file)
--- a/gcc/config/pa/pa.c
+++ b/gcc/config/pa/pa.c
@@ -442,7 +442,7 @@ reg_before_reload_operand (op, mode)
   return 0;
 }
 
-/* Accept any constant that can be moved in one instructions into a
+/* Accept any constant that can be moved in one instruction into a
    general register.  */
 int
 cint_ok_for_move (intval)
@@ -1744,9 +1744,13 @@ emit_move_sequence (operands, mode, scratch_reg)
          else
            temp = gen_reg_rtx (mode);
 
-         if (GET_CODE (operand1) == CONST_INT)
+         /* We don't directly split DImode constants on 32-bit targets
+            because PLUS uses an 11-bit immediate and the insn sequence
+            generated is not as efficient as the one using HIGH/LO_SUM.  */
+         if (GET_CODE (operand1) == CONST_INT
+             && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
            {
-             /* Directly break constant into low and high parts.  This
+             /* Directly break constant into high and low parts.  This
                 provides better optimization opportunities because various
                 passes recognize constants split with PLUS but not LO_SUM.
                 We use a 14-bit signed low part except when the addition

diff --git a/gcc/config/pa/pa.md b/gcc/config/pa/pa.md
index a81455465484bed29c28fae8ddb76a7a07345d83..10c0462b4e469ab439f369dacb126f29ca4ddb78 100644 (file)
--- a/gcc/config/pa/pa.md
+++ b/gcc/config/pa/pa.md
@@ -3815,20 +3815,18 @@
        (plus:DI (match_operand:DI 1 "register_operand" "")
                 (match_operand:DI 2 "arith_operand" "")))]
   ""
-  "")
-
-;; We allow arith_operand for operands2, even though strictly speaking it
-;; we would prefer to us arith11_operand since that's what the hardware
-;; can actually support.
-;;
-;; But the price of the extra reload in that case is worth the simplicity
-;; we get by allowing a trivial adddi3 expander to be used for both
-;; PA64 and PA32.
+  "
+{
+  if (!TARGET_64BIT
+      && GET_CODE (operands[2]) == CONST_INT
+      && !VAL_11_BITS_P (INTVAL (operands[2])))
+    operands[2] = force_reg (DImode, operands[2]);
+}")
 
 (define_insn ""
   [(set (match_operand:DI 0 "register_operand" "=r")
        (plus:DI (match_operand:DI 1 "register_operand" "%r")
-                (match_operand:DI 2 "arith_operand" "rI")))]
+                (match_operand:DI 2 "arith11_operand" "rI")))]
   "!TARGET_64BIT"
   "*
 {