(define_expand "vec_extract<mode><vel>"
[(set (match_operand:<VEL> 0 "register_operand")
(vec_select:<VEL>
- (match_operand:V_VLS 1 "register_operand")
+ (match_operand:V_VLS_ZVFH 1 "register_operand")
(parallel
[(match_operand 2 "nonmemory_operand")])))]
"TARGET_VECTOR"
(define_mode_iterator VLS [VLSI VLSF_ZVFHMIN])
+(define_mode_iterator VLS_ZVFH [VLSI VLSF])
+
(define_mode_iterator V [VI VF_ZVFHMIN])
(define_mode_iterator V_VLS [V VLS])
+(define_mode_iterator V_VLS_ZVFH [V VLS_ZVFH])
+
(define_mode_iterator V_VLSI [VI VLSI])
(define_mode_iterator V_VLSF [VF VLSF])
--- /dev/null
+/* Test there is no ICE when compile. */
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv_zvfhmin -mabi=lp64d -O3 -ftree-vectorize" } */
+
+#include <assert.h>
+#include <stdint-gcc.h>
+
+typedef _Float16 vnx4f __attribute__ ((vector_size (8)));
+
+vnx4f __attribute__ ((noinline, noclone))
+test_5 (vnx4f x, vnx4f y)
+{
+ return __builtin_shufflevector (x, y, 1, 3, 6, 7);
+}
+
+int
+main (void)
+{
+ vnx4f test_5_x = {0, 1, 3, 4};
+ vnx4f test_5_y = {4, 5, 6, 7};
+ vnx4f test_5_except = {1, 4, 6, 7};
+ vnx4f test_5_real;
+ test_5_real = test_5 (test_5_x, test_5_y);
+
+ for (int i = 0; i < 4; i++)
+ assert (test_5_real[i] == test_5_except[i]);
+
+ return 0;
+}
+
+/* { dg-final { scan-assembler-times {call\s+__extendhfsf2} 8 } } */