[(set_attr "type" "neon_dup<q>")]
)
-(define_insn "*aarch64_simd_mov<VDMOV:mode>"
+(define_insn_and_split "*aarch64_simd_mov<VDMOV:mode>"
[(set (match_operand:VDMOV 0 "nonimmediate_operand")
(match_operand:VDMOV 1 "general_operand"))]
"TARGET_FLOAT
&& (register_operand (operands[0], <MODE>mode)
|| aarch64_simd_reg_or_zero (operands[1], <MODE>mode))"
- {@ [cons: =0, 1; attrs: type, arch]
- [w , m ; neon_load1_1reg<q> , * ] ldr\t%d0, %1
- [r , m ; load_8 , * ] ldr\t%x0, %1
- [m , Dz; store_8 , * ] str\txzr, %0
- [m , w ; neon_store1_1reg<q>, * ] str\t%d1, %0
- [m , r ; store_8 , * ] str\t%x1, %0
- [w , w ; neon_logic<q> , simd] mov\t%0.<Vbtype>, %1.<Vbtype>
- [w , w ; neon_logic<q> , * ] fmov\t%d0, %d1
- [?r, w ; neon_to_gp<q> , simd] umov\t%0, %1.d[0]
- [?r, w ; neon_to_gp<q> , * ] fmov\t%x0, %d1
- [?w, r ; f_mcr , * ] fmov\t%d0, %1
- [?r, r ; mov_reg , * ] mov\t%0, %1
- [w , Dn; neon_move<q> , simd] << aarch64_output_simd_mov_immediate (operands[1], 64);
- [w , Dz; f_mcr , * ] fmov\t%d0, xzr
+ {@ [cons: =0, 1; attrs: type, arch, length]
+ [w , m ; neon_load1_1reg<q> , * , *] ldr\t%d0, %1
+ [r , m ; load_8 , * , *] ldr\t%x0, %1
+ [m , Dz; store_8 , * , *] str\txzr, %0
+ [m , w ; neon_store1_1reg<q>, * , *] str\t%d1, %0
+ [m , r ; store_8 , * , *] str\t%x1, %0
+ [w , w ; neon_logic<q> , simd, *] mov\t%0.<Vbtype>, %1.<Vbtype>
+ [w , w ; neon_logic<q> , * , *] fmov\t%d0, %d1
+ [?r, w ; neon_to_gp<q> , simd, *] umov\t%0, %1.d[0]
+ [?r, w ; neon_to_gp<q> , * , *] fmov\t%x0, %d1
+ [?w, r ; f_mcr , * , *] fmov\t%d0, %1
+ [?r, r ; mov_reg , * , *] mov\t%0, %1
+ [w , Dn; neon_move<q> , simd, *] << aarch64_output_simd_mov_immediate (operands[1], 64);
+ [w , Dz; f_mcr , * , *] fmov\t%d0, xzr
+ [w , Dx; neon_move , simd, 8] #
+ }
+ "CONST_INT_P (operands[1])
+ && aarch64_simd_special_constant_p (operands[1], <MODE>mode)
+ && FP_REGNUM_P (REGNO (operands[0]))"
+ [(const_int 0)]
+ {
+ aarch64_maybe_generate_simd_constant (operands[0], operands[1], <MODE>mode);
+ DONE;
}
)
[?r , r ; multiple , * , 8] #
[w , Dn; neon_move<q> , simd, 4] << aarch64_output_simd_mov_immediate (operands[1], 128);
[w , Dz; fmov , * , 4] fmov\t%d0, xzr
+ [w , Dx; neon_move , simd, 8] #
}
"&& reload_completed
- && (REG_P (operands[0])
+ && ((REG_P (operands[0])
&& REG_P (operands[1])
&& !(FP_REGNUM_P (REGNO (operands[0]))
- && FP_REGNUM_P (REGNO (operands[1]))))"
+ && FP_REGNUM_P (REGNO (operands[1]))))
+ || (aarch64_simd_special_constant_p (operands[1], <MODE>mode)
+ && FP_REGNUM_P (REGNO (operands[0]))))"
[(const_int 0)]
{
if (GP_REGNUM_P (REGNO (operands[0]))
&& GP_REGNUM_P (REGNO (operands[1])))
aarch64_simd_emit_reg_reg_move (operands, DImode, 2);
else
- aarch64_split_simd_move (operands[0], operands[1]);
+ {
+ if (FP_REGNUM_P (REGNO (operands[0]))
+ && <MODE>mode == V2DImode
+ && aarch64_maybe_generate_simd_constant (operands[0], operands[1],
+ <MODE>mode))
+ ;
+ else
+ aarch64_split_simd_move (operands[0], operands[1]);
+ }
DONE;
}
)
/* Return true if X is a CONST_INT, CONST_WIDE_INT or a constant vector
duplicate of such constants. If so, store in RET_WI the wide_int
representation of the constant paired with the inner mode of the vector mode
- or TImode for scalar X constants. */
+ or MODE for scalar X constants. If MODE is not provided then TImode is
+ used. */
static bool
-aarch64_extract_vec_duplicate_wide_int (rtx x, wide_int *ret_wi)
+aarch64_extract_vec_duplicate_wide_int (rtx x, wide_int *ret_wi,
+ scalar_mode mode = TImode)
{
rtx elt = unwrap_const_vec_duplicate (x);
if (!CONST_SCALAR_INT_P (elt))
return false;
scalar_mode smode
- = CONST_SCALAR_INT_P (x) ? TImode : GET_MODE_INNER (GET_MODE (x));
+ = CONST_SCALAR_INT_P (x) ? mode : GET_MODE_INNER (GET_MODE (x));
*ret_wi = rtx_mode_t (elt, smode);
return true;
}
&& IN_RANGE (INTVAL (elt), minval, maxval));
}
+/* Some constants can't be made using normal mov instructions in Advanced SIMD
+ but we can still create them in various ways. If the constant in VAL can be
+ created using alternate methods then if possible then return true and
+ additionally set TARGET to the rtx for the sequence if TARGET is not NULL.
+ Otherwise return false if sequence is not possible. */
+
+bool
+aarch64_maybe_generate_simd_constant (rtx target, rtx val, machine_mode mode)
+{
+ wide_int wval;
+ auto smode = GET_MODE_INNER (mode);
+ if (!aarch64_extract_vec_duplicate_wide_int (val, &wval, smode))
+ return false;
+
+ /* For Advanced SIMD we can create an integer with only the top bit set
+ using fneg (0.0f). */
+ if (TARGET_SIMD
+ && !TARGET_SVE
+ && smode == DImode
+ && wi::only_sign_bit_p (wval))
+ {
+ if (!target)
+ return true;
+
+ /* Use the same base type as aarch64_gen_shareable_zero. */
+ rtx zero = CONST0_RTX (V4SImode);
+ emit_move_insn (lowpart_subreg (V4SImode, target, mode), zero);
+ rtx neg = lowpart_subreg (V2DFmode, target, mode);
+ emit_insn (gen_negv2df2 (neg, copy_rtx (neg)));
+ return true;
+ }
+
+ return false;
+}
+
+/* Check if the value in VAL with mode MODE can be created using special
+ instruction sequences. */
+
+bool aarch64_simd_special_constant_p (rtx val, machine_mode mode)
+{
+ return aarch64_maybe_generate_simd_constant (NULL_RTX, val, mode);
+}
+
bool
aarch64_const_vec_all_same_int_p (rtx x, HOST_WIDE_INT val)
{
[r, w ; f_mrc , fp , 4] fmov\t%x0, %d1
[w, w ; fmov , fp , 4] fmov\t%d0, %d1
[w, Dd ; neon_move, simd, 4] << aarch64_output_scalar_simd_mov_immediate (operands[1], DImode);
- }
- "CONST_INT_P (operands[1]) && !aarch64_move_imm (INTVAL (operands[1]), DImode)
- && REG_P (operands[0]) && GP_REGNUM_P (REGNO (operands[0]))"
+ [w, Dx ; neon_move, simd, 8] #
+ }
+ "CONST_INT_P (operands[1])
+ && REG_P (operands[0])
+ && ((!aarch64_move_imm (INTVAL (operands[1]), DImode)
+ && GP_REGNUM_P (REGNO (operands[0])))
+ || (aarch64_simd_special_constant_p (operands[1], DImode)
+ && FP_REGNUM_P (REGNO (operands[0]))))"
[(const_int 0)]
{
+ if (GP_REGNUM_P (REGNO (operands[0])))
aarch64_expand_mov_immediate (operands[0], operands[1]);
- DONE;
+ else
+ aarch64_maybe_generate_simd_constant (operands[0], operands[1], DImode);
+ DONE;
}
)
git://gcc.gnu.org / gcc.git / commitdiff