Fix VIS3 assembler check and conditionalize testsuite on VIS3 support.

gcc/

	PR 50655
	* configure.ac: Add .register directives to VIS3 test.
	* configure: Regenerate.

gcc/testsuite/

	PR 50655
	* gcc.target/sparc/sparc.exp: Add vis3 target test.
	* gcc.target/sparc/cmask.c: Use it.
	* gcc.target/sparc/fhalve.c: Likewise.
	* gcc.target/sparc/fnegop.c: Likewise.
	* gcc.target/sparc/fpadds.c: Likewise.
	* gcc.target/sparc/fshift.c: Likewise.
	* gcc.target/sparc/fucmp.c: Likewise.
	* gcc.target/sparc/lzd.c: Likewise.
	* gcc.target/sparc/vis3misc.c: Likewise.
	* gcc.target/sparc/xmul.c: Likewise.

From-SVN: r179667

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index f840e4678ca2020b7e6f794d46d3af98e28ee3db..573ce6ec2799ba847b3a8f868939542977027563 100644 (file)
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,9 @@
+2011-10-07  David S. Miller  <davem@davemloft.net>
+
+       PR 50655
+       * configure.ac: Add .register directives to VIS3 test.
+       * configure: Regenerate.
+
 2011-10-07  Richard Henderson  <rth@redhat.com>
 
        * config.gcc (x86_64-*): Add core-avx-i, core-avx2 for with_cpu.

diff --git a/gcc/configure b/gcc/configure
index ac327053bc956747371141b49d872638fd6487ee..cb55ddaa2a48373345b85fe534e34e81141f2dae 100755 (executable)
--- a/gcc/configure
+++ b/gcc/configure
@@ -24060,6 +24060,8 @@ else
   gcc_cv_as_sparc_fmaf=no
   if test x$gcc_cv_as != x; then
     $as_echo '.text
+       .register %g2, #scratch
+       .register %g3, #scratch
        .align 4
        fmaddd %f0, %f2, %f4, %f6
        addxccc %g1, %g2, %g3

diff --git a/gcc/configure.ac b/gcc/configure.ac
index ed52c918afa079229dae933a1592949092373853..a7b94e64451ba77f55d2e16d715ff31463e8de34 100644 (file)
--- a/gcc/configure.ac
+++ b/gcc/configure.ac
@@ -3491,6 +3491,8 @@ foo:
       gcc_cv_as_sparc_fmaf,,
       [-xarch=v9d],
       [.text
+       .register %g2, #scratch
+       .register %g3, #scratch
        .align 4
        fmaddd %f0, %f2, %f4, %f6
        addxccc %g1, %g2, %g3

diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog
index aff35a6070188da970f3a099adf1ae011ad92636..ea79b6075fb50c7de5ccbe895a3a503febcfe932 100644 (file)
--- a/gcc/testsuite/ChangeLog
+++ b/gcc/testsuite/ChangeLog
@@ -1,3 +1,17 @@
+2011-10-07  David S. Miller  <davem@davemloft.net>
+
+       PR 50655
+       * gcc.target/sparc/sparc.exp: Add vis3 target test.
+       * gcc.target/sparc/cmask.c: Use it.
+       * gcc.target/sparc/fhalve.c: Likewise.
+       * gcc.target/sparc/fnegop.c: Likewise.
+       * gcc.target/sparc/fpadds.c: Likewise.
+       * gcc.target/sparc/fshift.c: Likewise.
+       * gcc.target/sparc/fucmp.c: Likewise.
+       * gcc.target/sparc/lzd.c: Likewise.
+       * gcc.target/sparc/vis3misc.c: Likewise.
+       * gcc.target/sparc/xmul.c: Likewise.
+
 2011-10-07  Richard Henderson  <rth@redhat.com>
 
        * gcc.target/i386/avx256-unaligned-load-2.c: Tweek vinsert pattern
@@ -17,7 +31,7 @@
 2011-10-06  Joern Rennecke <joern.rennecke@embecosm.com>
 
        * gcc.dg/pr47276.c (ASMNAME, ASMNAME2, STRING): Define.
-       (__EI___vsyslog_chk, __EI_syslog, __EI_vsyslog): Use ASMNAME.  
+       (__EI___vsyslog_chk, __EI_syslog, __EI_vsyslog): Use ASMNAME.
        (syslog, vsyslog, __vsyslog_chk): Likewise.
 
        * gcc.dg/lto/20081222_1.c (ASMNAME, ASMNAME2, STRING): Define.

diff --git a/gcc/testsuite/gcc.target/sparc/cmask.c b/gcc/testsuite/gcc.target/sparc/cmask.c
index b3168ec321d6324ab04cc35d2a57500886cd90a6..989274c68584c66afd0d59d1c4c9409bd1314aab 100644 (file)
--- a/gcc/testsuite/gcc.target/sparc/cmask.c
+++ b/gcc/testsuite/gcc.target/sparc/cmask.c
@@ -1,4 +1,4 @@
-/* { dg-do compile } */
+/* { dg-do compile { target { vis3 } } } */
 /* { dg-options "-mcpu=niagara3 -mvis" } */
 
 void test_cm8 (long x)

diff --git a/gcc/testsuite/gcc.target/sparc/fhalve.c b/gcc/testsuite/gcc.target/sparc/fhalve.c
index 340b936b8fa82de44b2e8afa46203f809300f883..737fc71bbcf64cbf7f8819bd92fddc236c477b59 100644 (file)
--- a/gcc/testsuite/gcc.target/sparc/fhalve.c
+++ b/gcc/testsuite/gcc.target/sparc/fhalve.c
@@ -1,4 +1,4 @@
-/* { dg-do compile } */
+/* { dg-do compile { target { vis3 } } } */
 /* { dg-options "-mcpu=niagara3 -mvis" } */
 
 float test_fhadds (float x, float y)

diff --git a/gcc/testsuite/gcc.target/sparc/fnegop.c b/gcc/testsuite/gcc.target/sparc/fnegop.c
index 25f8c199e2491d3af67f315133708ac88d0ed562..3e3e72c820cab695478345ebded37056f107351f 100644 (file)
--- a/gcc/testsuite/gcc.target/sparc/fnegop.c
+++ b/gcc/testsuite/gcc.target/sparc/fnegop.c
@@ -1,4 +1,4 @@
-/* { dg-do compile } */
+/* { dg-do compile { target { vis3 } } } */
 /* { dg-options "-O2 -mcpu=niagara3 -mvis" } */
 
 float test_fnadds(float x, float y)

diff --git a/gcc/testsuite/gcc.target/sparc/fpadds.c b/gcc/testsuite/gcc.target/sparc/fpadds.c
index d0704e03eda47b5be17851462c067a0b6ad5efb1..f55cb057a2ad2f21881c53f1358613f5ee632594 100644 (file)
--- a/gcc/testsuite/gcc.target/sparc/fpadds.c
+++ b/gcc/testsuite/gcc.target/sparc/fpadds.c
@@ -1,4 +1,4 @@
-/* { dg-do compile } */
+/* { dg-do compile { target { vis3 } } } */
 /* { dg-options "-mcpu=niagara3 -mvis" } */
 typedef int __v2si __attribute__((vector_size(8)));
 typedef int __v1si __attribute__((vector_size(4)));

diff --git a/gcc/testsuite/gcc.target/sparc/fshift.c b/gcc/testsuite/gcc.target/sparc/fshift.c
index a12df0451cb0ed8f980c199ca113fc6afc2aa186..6adbed6917190fa79876855ea58d33176854b8ba 100644 (file)
--- a/gcc/testsuite/gcc.target/sparc/fshift.c
+++ b/gcc/testsuite/gcc.target/sparc/fshift.c
@@ -1,4 +1,4 @@
-/* { dg-do compile } */
+/* { dg-do compile { target { vis3 } } } */
 /* { dg-options "-mcpu=niagara3 -mvis" } */
 typedef int __v2si __attribute__((vector_size(8)));
 typedef short __v4hi __attribute__((vector_size(8)));

diff --git a/gcc/testsuite/gcc.target/sparc/fucmp.c b/gcc/testsuite/gcc.target/sparc/fucmp.c
index 7f291c3e7ed85c85732237406fc1e612d24aa24c..4e7ecadcd4aeaca1613911ba971d2c6bc57af07b 100644 (file)
--- a/gcc/testsuite/gcc.target/sparc/fucmp.c
+++ b/gcc/testsuite/gcc.target/sparc/fucmp.c
@@ -1,4 +1,4 @@
-/* { dg-do compile } */
+/* { dg-do compile { target { vis3 } } } */
 /* { dg-options "-mcpu=niagara3 -mvis" } */
 typedef unsigned char vec8 __attribute__((vector_size(8)));
 

diff --git a/gcc/testsuite/gcc.target/sparc/lzd.c b/gcc/testsuite/gcc.target/sparc/lzd.c
index a8978296300f3ff0f439f66f5b6afaece38fde42..5ffaf56e5584cac7da0d17e2e68d97a058573a5c 100644 (file)
--- a/gcc/testsuite/gcc.target/sparc/lzd.c
+++ b/gcc/testsuite/gcc.target/sparc/lzd.c
@@ -1,4 +1,4 @@
-/* { dg-do compile } */
+/* { dg-do compile { target { vis3 } } } */
 /* { dg-options "-mcpu=niagara3" } */
 int test_clz(int a)
 {

diff --git a/gcc/testsuite/gcc.target/sparc/sparc.exp b/gcc/testsuite/gcc.target/sparc/sparc.exp
index 9658d08bc9cc107d9c00af4d95fbba8330bd76ba..51c9c16ecb77c912fa78c07170a4c7ab56ecf3d5 100644 (file)
--- a/gcc/testsuite/gcc.target/sparc/sparc.exp
+++ b/gcc/testsuite/gcc.target/sparc/sparc.exp
@@ -24,6 +24,17 @@ if ![istarget sparc*-*-*] then {
 # Load support procs.
 load_lib gcc-dg.exp
 
+# Return 1 if vis3 instructions can be compiled.
+proc check_effective_target_vis3 { } {
+    return [check_no_compiler_messages vis3 object {
+       long long
+       _vis3_fpadd64 (long long __X, long long __Y)
+       {
+           return __builtin_vis_fpadd64 (__X, __Y);
+       }
+    } "-mcpu=niagara3 -mvis" ]
+}
+
 # If a testcase doesn't have special options, use these.
 global DEFAULT_CFLAGS
 if ![info exists DEFAULT_CFLAGS] then {

diff --git a/gcc/testsuite/gcc.target/sparc/vis3misc.c b/gcc/testsuite/gcc.target/sparc/vis3misc.c
index 8a9535e8fb506db4a24bb3de358936776e66fc2e..e3ef49e210d3d26d1fc76d182d24c5b0456bc06a 100644 (file)
--- a/gcc/testsuite/gcc.target/sparc/vis3misc.c
+++ b/gcc/testsuite/gcc.target/sparc/vis3misc.c
@@ -1,4 +1,4 @@
-/* { dg-do compile } */
+/* { dg-do compile { target { vis3 } } } */
 /* { dg-options "-mcpu=niagara3 -mvis" } */
 typedef int __v2si __attribute__((vector_size(8)));
 typedef short __v4hi __attribute__((vector_size(8)));

diff --git a/gcc/testsuite/gcc.target/sparc/xmul.c b/gcc/testsuite/gcc.target/sparc/xmul.c
index ce80e6cbbe03e7d74b43e45e1bc6b18d30adfb48..5d249d092dbc5b19de4733e44ec4bc258c06eabf 100644 (file)
--- a/gcc/testsuite/gcc.target/sparc/xmul.c
+++ b/gcc/testsuite/gcc.target/sparc/xmul.c
@@ -1,4 +1,4 @@
-/* { dg-do compile } */
+/* { dg-do compile { target { vis3 } } } */
 /* { dg-options "-mcpu=niagara3 -mvis" } */
 typedef long long int64_t;