+2011-10-07 David S. Miller <davem@davemloft.net>
+
+ PR 50655
+ * configure.ac: Add .register directives to VIS3 test.
+ * configure: Regenerate.
+
2011-10-07 Richard Henderson <rth@redhat.com>
* config.gcc (x86_64-*): Add core-avx-i, core-avx2 for with_cpu.
gcc_cv_as_sparc_fmaf=no
if test x$gcc_cv_as != x; then
$as_echo '.text
+ .register %g2, #scratch
+ .register %g3, #scratch
.align 4
fmaddd %f0, %f2, %f4, %f6
addxccc %g1, %g2, %g3
gcc_cv_as_sparc_fmaf,,
[-xarch=v9d],
[.text
+ .register %g2, #scratch
+ .register %g3, #scratch
.align 4
fmaddd %f0, %f2, %f4, %f6
addxccc %g1, %g2, %g3
+2011-10-07 David S. Miller <davem@davemloft.net>
+
+ PR 50655
+ * gcc.target/sparc/sparc.exp: Add vis3 target test.
+ * gcc.target/sparc/cmask.c: Use it.
+ * gcc.target/sparc/fhalve.c: Likewise.
+ * gcc.target/sparc/fnegop.c: Likewise.
+ * gcc.target/sparc/fpadds.c: Likewise.
+ * gcc.target/sparc/fshift.c: Likewise.
+ * gcc.target/sparc/fucmp.c: Likewise.
+ * gcc.target/sparc/lzd.c: Likewise.
+ * gcc.target/sparc/vis3misc.c: Likewise.
+ * gcc.target/sparc/xmul.c: Likewise.
+
2011-10-07 Richard Henderson <rth@redhat.com>
* gcc.target/i386/avx256-unaligned-load-2.c: Tweek vinsert pattern
2011-10-06 Joern Rennecke <joern.rennecke@embecosm.com>
* gcc.dg/pr47276.c (ASMNAME, ASMNAME2, STRING): Define.
- (__EI___vsyslog_chk, __EI_syslog, __EI_vsyslog): Use ASMNAME.
+ (__EI___vsyslog_chk, __EI_syslog, __EI_vsyslog): Use ASMNAME.
(syslog, vsyslog, __vsyslog_chk): Likewise.
* gcc.dg/lto/20081222_1.c (ASMNAME, ASMNAME2, STRING): Define.
-/* { dg-do compile } */
+/* { dg-do compile { target { vis3 } } } */
/* { dg-options "-mcpu=niagara3 -mvis" } */
void test_cm8 (long x)
-/* { dg-do compile } */
+/* { dg-do compile { target { vis3 } } } */
/* { dg-options "-mcpu=niagara3 -mvis" } */
float test_fhadds (float x, float y)
-/* { dg-do compile } */
+/* { dg-do compile { target { vis3 } } } */
/* { dg-options "-O2 -mcpu=niagara3 -mvis" } */
float test_fnadds(float x, float y)
-/* { dg-do compile } */
+/* { dg-do compile { target { vis3 } } } */
/* { dg-options "-mcpu=niagara3 -mvis" } */
typedef int __v2si __attribute__((vector_size(8)));
typedef int __v1si __attribute__((vector_size(4)));
-/* { dg-do compile } */
+/* { dg-do compile { target { vis3 } } } */
/* { dg-options "-mcpu=niagara3 -mvis" } */
typedef int __v2si __attribute__((vector_size(8)));
typedef short __v4hi __attribute__((vector_size(8)));
-/* { dg-do compile } */
+/* { dg-do compile { target { vis3 } } } */
/* { dg-options "-mcpu=niagara3 -mvis" } */
typedef unsigned char vec8 __attribute__((vector_size(8)));
-/* { dg-do compile } */
+/* { dg-do compile { target { vis3 } } } */
/* { dg-options "-mcpu=niagara3" } */
int test_clz(int a)
{
# Load support procs.
load_lib gcc-dg.exp
+# Return 1 if vis3 instructions can be compiled.
+proc check_effective_target_vis3 { } {
+ return [check_no_compiler_messages vis3 object {
+ long long
+ _vis3_fpadd64 (long long __X, long long __Y)
+ {
+ return __builtin_vis_fpadd64 (__X, __Y);
+ }
+ } "-mcpu=niagara3 -mvis" ]
+}
+
# If a testcase doesn't have special options, use these.
global DEFAULT_CFLAGS
if ![info exists DEFAULT_CFLAGS] then {
-/* { dg-do compile } */
+/* { dg-do compile { target { vis3 } } } */
/* { dg-options "-mcpu=niagara3 -mvis" } */
typedef int __v2si __attribute__((vector_size(8)));
typedef short __v4hi __attribute__((vector_size(8)));
-/* { dg-do compile } */
+/* { dg-do compile { target { vis3 } } } */
/* { dg-options "-mcpu=niagara3 -mvis" } */
typedef long long int64_t;