RISC-V: Add VLS integer ABS support

Regression passed.

Committed.

gcc/ChangeLog:

	* config/riscv/autovec.md: Extend VLS modes.

gcc/testsuite/ChangeLog:

	* gcc.target/riscv/rvv/autovec/vls/abs-2.c: New test.

diff --git a/gcc/config/riscv/autovec.md b/gcc/config/riscv/autovec.md
index f0f1abc4e824647488936eafd9bb2ef28e99c40d..c895d41376dba4f7b533ec936b1706a193414626 100644 (file)
--- a/gcc/config/riscv/autovec.md
+++ b/gcc/config/riscv/autovec.md
@@ -1004,9 +1004,9 @@
 ;; -------------------------------------------------------------------------------
 
 (define_insn_and_split "abs<mode>2"
-  [(set (match_operand:VI 0 "register_operand")
-     (abs:VI
-       (match_operand:VI 1 "register_operand")))]
+  [(set (match_operand:V_VLSI 0 "register_operand")
+     (abs:V_VLSI
+       (match_operand:V_VLSI 1 "register_operand")))]
   "TARGET_VECTOR && can_create_pseudo_p ()"
   "#"
   "&& 1"

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/abs-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/abs-2.c
new file mode 100644 (file)
index 0000000..e98f5c4
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/abs-2.c
@@ -0,0 +1,62 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8 -fdump-tree-optimized" } */
+
+#include "def.h"
+
+DEF_OP_V (neg, 4, int8_t, __builtin_abs)
+DEF_OP_V (neg, 8, int8_t, __builtin_abs)
+DEF_OP_V (neg, 16, int8_t, __builtin_abs)
+DEF_OP_V (neg, 32, int8_t, __builtin_abs)
+DEF_OP_V (neg, 64, int8_t, __builtin_abs)
+DEF_OP_V (neg, 128, int8_t, __builtin_abs)
+DEF_OP_V (neg, 256, int8_t, __builtin_abs)
+DEF_OP_V (neg, 512, int8_t, __builtin_abs)
+DEF_OP_V (neg, 1024, int8_t, __builtin_abs)
+DEF_OP_V (neg, 2048, int8_t, __builtin_abs)
+DEF_OP_V (neg, 4096, int8_t, __builtin_abs)
+
+DEF_OP_V (neg, 4, int16_t, __builtin_abs)
+DEF_OP_V (neg, 8, int16_t, __builtin_abs)
+DEF_OP_V (neg, 16, int16_t, __builtin_abs)
+DEF_OP_V (neg, 32, int16_t, __builtin_abs)
+DEF_OP_V (neg, 64, int16_t, __builtin_abs)
+DEF_OP_V (neg, 128, int16_t, __builtin_abs)
+DEF_OP_V (neg, 256, int16_t, __builtin_abs)
+DEF_OP_V (neg, 512, int16_t, __builtin_abs)
+DEF_OP_V (neg, 1024, int16_t, __builtin_abs)
+DEF_OP_V (neg, 2048, int16_t, __builtin_abs)
+
+DEF_OP_V (neg, 4, int32_t, __builtin_abs)
+DEF_OP_V (neg, 8, int32_t, __builtin_abs)
+DEF_OP_V (neg, 16, int32_t, __builtin_abs)
+DEF_OP_V (neg, 32, int32_t, __builtin_abs)
+DEF_OP_V (neg, 64, int32_t, __builtin_abs)
+DEF_OP_V (neg, 128, int32_t, __builtin_abs)
+DEF_OP_V (neg, 256, int32_t, __builtin_abs)
+DEF_OP_V (neg, 512, int32_t, __builtin_abs)
+DEF_OP_V (neg, 1024, int32_t, __builtin_abs)
+
+DEF_OP_V (neg, 4, int64_t, __builtin_abs)
+DEF_OP_V (neg, 8, int64_t, __builtin_abs)
+DEF_OP_V (neg, 16, int64_t, __builtin_abs)
+DEF_OP_V (neg, 32, int64_t, __builtin_abs)
+DEF_OP_V (neg, 64, int64_t, __builtin_abs)
+DEF_OP_V (neg, 128, int64_t, __builtin_abs)
+DEF_OP_V (neg, 256, int64_t, __builtin_abs)
+DEF_OP_V (neg, 512, int64_t, __builtin_abs)
+
+/* { dg-final { scan-assembler-times {vneg\.v} 38 } } */
+/* { dg-final { scan-assembler-times {vmslt\.vi} 38 } } */
+/* { dg-final { scan-assembler-not {csrr} } } */
+/* { dg-final { scan-tree-dump-not "1,1" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "2,2" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "4,4" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "16,16" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "32,32" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "64,64" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "128,128" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "256,256" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "512,512" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "1024,1024" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "2048,2048" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "4096,4096" "optimized" } } */