Daily bump.

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 305caaa5ea52e581dc7f43322d0c337cf9b7aab0..1683937f3e21b504e31ce8b0c8ce4c83d2e15f23 100644 (file)
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,12 @@
+2022-02-10  Uros Bizjak  <ubizjak@gmail.com>
+
+       Backported from master:
+       2022-02-10  Uroš Bizjak  <ubizjak@gmail.com>
+
+       PR target/104469
+       * config/i386/sse.md (vec_unpacks_float_lo_v4si):
+       Change operand 1 constraint to register_operand.
+
 2022-02-09  Uroš Bizjak  <ubizjak@gmail.com>
 
        PR target/104462

diff --git a/gcc/DATESTAMP b/gcc/DATESTAMP
index 65c020f9c5e4676b8b8e9e789c0ea99aa186580d..f22e11ed9b089c9b240007ca2a1a094bd15bf64e 100644 (file)
--- a/gcc/DATESTAMP
+++ b/gcc/DATESTAMP
@@ -1 +1 @@
-20220210
+20220211

diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog
index 0ce9f18b5ffac0656aedd4a4471a03490d653b7e..2ed5bb605ced07195c35bff218897dd94053ad6c 100644 (file)
--- a/gcc/testsuite/ChangeLog
+++ b/gcc/testsuite/ChangeLog
@@ -1,3 +1,19 @@
+2022-02-10  H.J. Lu  <hjl.tools@gmail.com>
+
+       Backported from master:
+       2022-02-10  H.J. Lu  <hjl.tools@gmail.com>
+
+       PR target/104458
+       * gcc.target/i386/pr104458.c: Replace long with long long.
+
+2022-02-10  Uros Bizjak  <ubizjak@gmail.com>
+
+       Backported from master:
+       2022-02-10  Uroš Bizjak  <ubizjak@gmail.com>
+
+       PR target/104469
+       * gcc.target/i386/pr104469.c: New test.
+
 2022-02-09  Uros Bizjak  <ubizjak@gmail.com>
 
        Backported from master:

diff --git a/libstdc++-v3/ChangeLog b/libstdc++-v3/ChangeLog
index 545377e4dc0cf3bc659add2bd1376a72aed9ad6e..df215fcf24b110922d95d3334413f3fb9f337ed0 100644 (file)
--- a/libstdc++-v3/ChangeLog
+++ b/libstdc++-v3/ChangeLog
@@ -1,3 +1,12 @@
+2022-02-10  Thomas Rodgers  <rodgert@appliantology.com>
+
+       Backported from master:
+       2022-02-10  Thomas Rodgers  <rodgert@appliantology.com>
+
+       * include/bits/atomic_wait.h (__waiter_base::_S_do_spin,
+       __waiter_base::_S_do_spin_v): Change memory order from relaxed
+       to acquire.
+
 2022-02-09  Thomas Rodgers  <rodgert@appliantology.com>
 
        Backported from master: