/* Ranges for the various kinds of registers. */
#define ADDL_REGNO_P(REGNO) ((REGNO) >= 0 && (REGNO) <= 3)
#define GR_REGNO_P(REGNO) ((REGNO) >= 0 && (REGNO) <= 127)
-#define FR_FP_REGNO_P(REGNO) \
- (((REGNO) >= 128 && (REGNO) <= 143) || ((REGNO) >= 152 && (REGNO) <= 223))
-#define FR_INT_REGNO_P(REGNO) \
- (((REGNO) >= 144 && (REGNO) <= 151) || ((REGNO) >= 224 && (REGNO) <= 255))
#define FR_REGNO_P(REGNO) ((REGNO) >= 128 && (REGNO) <= 255)
#define PR_REGNO_P(REGNO) ((REGNO) >= 256 && (REGNO) <= 319)
#define BR_REGNO_P(REGNO) ((REGNO) >= 320 && (REGNO) <= 327)
that one). */
#define HARD_REGNO_MODE_OK(REGNO, MODE) \
- (FR_FP_REGNO_P (REGNO) ? ! INTEGRAL_MODE_P (MODE) \
- : FR_INT_REGNO_P (REGNO) ? ! FLOAT_MODE_P (MODE) \
- : PR_REGNO_P (REGNO) ? (MODE) == CCmode \
- : 1)
+ (PR_REGNO_P (REGNO) ? (MODE) == CCmode : 1)
/* A C expression that is nonzero if it is desirable to choose register
allocation so as to avoid move instructions between a value of mode MODE1
register class, followed by one more enumeral value, `LIM_REG_CLASSES',
which is not a register class but rather tells how many classes there
are. */
-/* ??? FP registers hold INT and FP values in different representations, so
- we can't just use a subreg to convert between the two. We get around this
- problem by segmenting the FP register set into two parts. One part (FR_INT)
- only holds integer values, and one part (FR_FP) only hold FP values. Thus
- we always know which representation is being used. */
/* ??? When compiling without optimization, it is possible for the only use of
a pseudo to be a parameter load from the stack with a REG_EQUIV note.
Regclass handles this case specially and does not assign any costs to the
BR_REGS,
ADDL_REGS,
GR_REGS,
- FR_INT_REGS,
- FR_FP_REGS,
FR_REGS,
- GR_AND_FR_INT_REGS,
- GR_AND_FR_FP_REGS,
GR_AND_FR_REGS,
ALL_REGS,
LIM_REG_CLASSES
/* An initializer containing the names of the register classes as C string
constants. These names are used in writing some of the debugging dumps. */
#define REG_CLASS_NAMES \
-{ "NO_REGS", "PR_REGS", "BR_REGS", "ADDL_REGS", "GR_REGS", "FR_INT_REGS", \
- "FR_FP_REGS", "FR_REGS", "GR_AND_FR_INT_REGS", "GR_AND_FR_FP_REGS", \
- "GR_AND_FR_REGS", "ALL_REGS" }
+{ "NO_REGS", "PR_REGS", "BR_REGS", "ADDL_REGS", "GR_REGS", \
+ "FR_REGS", "GR_AND_FR_REGS", "ALL_REGS" }
/* An initializer containing the contents of the register classes, as integers
which are bit masks. The Nth integer specifies the contents of class N.
{ 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, \
0x00000000, 0x00000000, 0x00000000, 0x00000000, \
0x00000000, 0x00000000, 0x300 }, \
- /* FR_INT_REGS. */ \
- { 0x00000000, 0x00000000, 0x00000000, 0x00000000, \
- 0x00FF0000, 0x00000000, 0x00000000, 0xFFFFFFFF, \
- 0x00000000, 0x00000000, 0x000 }, \
- /* FR_FP_REGS. */ \
- { 0x00000000, 0x00000000, 0x00000000, 0x00000000, \
- 0xFF00FFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, \
- 0x00000000, 0x00000000, 0x000 }, \
/* FR_REGS. */ \
{ 0x00000000, 0x00000000, 0x00000000, 0x00000000, \
0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, \
0x00000000, 0x00000000, 0x000 }, \
- /* GR_AND_FR_INT_REGS. */ \
- { 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, \
- 0x00FF0000, 0x00000000, 0x00000000, 0xFFFFFFFF, \
- 0x00000000, 0x00000000, 0x300 }, \
- /* GR_AND_FR_FP_REGS. */ \
- { 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, \
- 0xFF00FFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, \
- 0x00000000, 0x00000000, 0x300 }, \
/* GR_AND_FR_REGS. */ \
{ 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, \
0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, \
#define REGNO_REG_CLASS(REGNO) \
(ADDL_REGNO_P (REGNO) ? ADDL_REGS \
: GENERAL_REGNO_P (REGNO) ? GR_REGS \
- : FR_FP_REGNO_P (REGNO) ? FR_FP_REGS \
- : FR_INT_REGNO_P (REGNO) ? FR_INT_REGS \
+ : FR_REGNO_P (REGNO) ? FR_REGS \
: PR_REGNO_P (REGNO) ? PR_REGS \
: BR_REGNO_P (REGNO) ? BR_REGS \
: NO_REGS)
will not be passed to this macro; you do not need to handle it. */
#define REG_CLASS_FROM_LETTER(CHAR) \
-((CHAR) == 'f' ? FR_FP_REGS \
- : (CHAR) == 'e' ? FR_INT_REGS \
+((CHAR) == 'f' ? FR_REGS \
: (CHAR) == 'a' ? ADDL_REGS \
: (CHAR) == 'b' ? BR_REGS \
: (CHAR) == 'c' ? PR_REGS \
This is closely related to the macro `HARD_REGNO_NREGS'. */
#define CLASS_MAX_NREGS(CLASS, MODE) \
- ((MODE) == CCmode && (CLASS) == PR_REGS ? 2 \
- : (((CLASS) == FR_REGS || (CLASS) == FR_FP_REGS \
- || (CLASS) == FR_INT_REGS) && (MODE) == XFmode) ? 1 \
+ ((MODE) == CCmode && (CLASS) == PR_REGS ? 2 \
+ : ((CLASS) == FR_REGS && (MODE) == XFmode) ? 1 \
: (GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
/* If defined, gives a class of registers that cannot be used as the
or a `MEM' representing a location in the stack. This enables DWARF2
unwind info for C++ EH. */
#define INCOMING_RETURN_ADDR_RTX gen_rtx_REG (VOIDmode, BR_REG (0))
+
/* ??? This is not defined because of three problems.
1) dwarf2out.c assumes that DWARF_FRAME_RETURN_COLUMN fits in one byte.
The default value is FIRST_PSEUDO_REGISTER which doesn't. This can be
((FROM) == BR_REGS && (TO) == BR_REGS ? 8 \
: (((FROM) == BR_REGS && (TO) != GENERAL_REGS) \
|| ((TO) == BR_REGS && (FROM) != GENERAL_REGS)) ? 6 \
- : (((FROM) == FR_FP_REGS && (TO) == FR_INT_REGS) \
- || ((FROM) == FR_INT_REGS && (TO) == FR_FP_REGS)) ? 4 \
: 2)
/* A C expression for the cost of moving data of mode M between a register and
}")
(define_insn "*movqi_internal"
- [(set (match_operand:QI 0 "nonimmediate_operand" "=r,r,r,m,r,*e")
- (match_operand:QI 1 "move_operand" "r,J,m,r,*e,r"))]
+ [(set (match_operand:QI 0 "nonimmediate_operand" "=r,r,r, m, r,*f,*f")
+ (match_operand:QI 1 "move_operand" "rO,J,m,rO,*f,rO,*f"))]
"! memory_operand (operands[0], QImode)
|| ! memory_operand (operands[1], QImode)"
"@
- mov %0 = %1
+ mov %0 = %r1
addl %0 = %1, r0
ld1%O1 %0 = %1%P1
- st1%Q0 %0 = %1%P0
+ st1%Q0 %0 = %r1%P0
getf.sig %0 = %1
- setf.sig %0 = %1"
- [(set_attr "type" "A,A,M,M,M,M")])
+ setf.sig %0 = %r1
+ mov %0 = %1"
+ [(set_attr "type" "A,A,M,M,M,M,F")])
(define_expand "movhi"
[(set (match_operand:HI 0 "general_operand" "")
}")
(define_insn "*movhi_internal"
- [(set (match_operand:HI 0 "nonimmediate_operand" "=r,r,r,m,r,*e")
- (match_operand:HI 1 "move_operand" "r,J,m,r,*e,r"))]
+ [(set (match_operand:HI 0 "nonimmediate_operand" "=r,r,r, m, r,*f,*f")
+ (match_operand:HI 1 "move_operand" "rO,J,m,rO,*f,rO,*f"))]
"! memory_operand (operands[0], HImode)
|| !memory_operand (operands[1], HImode)"
"@
- mov %0 = %1
+ mov %0 = %r1
addl %0 = %1, r0
ld2%O1 %0 = %1%P1
- st2%Q0 %0 = %1%P0
+ st2%Q0 %0 = %r1%P0
getf.sig %0 = %1
- setf.sig %0 = %1"
- [(set_attr "type" "A,A,M,M,M,M")])
+ setf.sig %0 = %r1
+ mov %0 = %1"
+ [(set_attr "type" "A,A,M,M,M,M,F")])
(define_expand "movsi"
[(set (match_operand:SI 0 "general_operand" "")
}")
(define_insn "*movsi_internal"
- [(set (match_operand:SI 0 "nonimmediate_operand" "=r,r,r,r,m,r,*e,*e,r,*f")
- (match_operand:SI 1 "move_operand" "r,J,i,m,r,*e,r,*e,*f,r"))]
+ [(set (match_operand:SI 0 "nonimmediate_operand" "=r,r,r,r, m, r,*f,*f")
+ (match_operand:SI 1 "move_operand" "rO,J,i,m,rO,*f,rO,*f"))]
"! memory_operand (operands[0], SImode)
|| ! memory_operand (operands[1], SImode)"
"@
- mov %0 = %1
+ mov %0 = %r1
addl %0 = %1, r0
movl %0 = %1
ld4%O1 %0 = %1%P1
- st4%Q0 %0 = %1%P0
+ st4%Q0 %0 = %r1%P0
getf.sig %0 = %1
- setf.sig %0 = %1
- mov %0 = %1
- getf.s %0 = %1
- setf.s %0 = %1"
- [(set_attr "type" "A,A,L,M,M,M,M,F,M,M")])
+ setf.sig %0 = %r1
+ mov %0 = %1"
+ [(set_attr "type" "A,A,L,M,M,M,M,F")])
(define_expand "movdi"
[(set (match_operand:DI 0 "general_operand" "")
operands[1] = copy_to_mode_reg (DImode, operands[1]);
}")
-;; ??? Emit stf8 for m/*e constraint.
(define_insn "*movdi_internal"
- [(set (match_operand:DI 0 "nonimmediate_operand" "=r,r,r,r,m,r,*e,*e,r,*f,r,*b")
- (match_operand:DI 1 "move_operand" "r,J,i,m,r,*e,r,*e,*f,r,*b,r"))]
+ [(set (match_operand:DI 0 "nonimmediate_operand" "=r,r,r,r, m, r,*f,*f,*f, m, r,*b")
+ (match_operand:DI 1 "move_operand" "rO,J,i,m,rO,*f,rO,*f, m,*f,*b,rO"))]
"! memory_operand (operands[0], DImode)
|| ! memory_operand (operands[1], DImode)"
"@
- mov %0 = %1
+ mov %0 = %r1
addl %0 = %1, r0
movl %0 = %1
ld8%O1 %0 = %1%P1
- st8%Q0 %0 = %1%P0
+ st8%Q0 %0 = %r1%P0
getf.sig %0 = %1
- setf.sig %0 = %1
+ setf.sig %0 = %r1
mov %0 = %1
- getf.d %0 = %1
- setf.d %0 = %1
+ ldf8%O1 %0 = %1%P1
+ stf8%Q0 %0 = %1%P0
mov %0 = %1
- mov %0 = %1"
+ mov %0 = %r1"
[(set_attr "type" "A,A,L,M,M,M,M,F,M,M,I,I")])
(define_expand "load_fptr"
operands[1] = copy_to_mode_reg (SFmode, operands[1]);
}")
-;; ??? The r/m alternative is apparently needed because of paradoxical subregs,
-;; so it may no longer be necessary after scheduling is enabled.
-
(define_insn "*movsf_internal"
- [(set (match_operand:SF 0 "nonimmediate_operand" "=f,f,m,*r,f,*r,*r")
- (match_operand:SF 1 "general_operand" "fG,m,fG,fG,*r,*r,m"))]
+ [(set (match_operand:SF 0 "nonimmediate_operand" "=f,f, m,*r, f,*r,*r, m")
+ (match_operand:SF 1 "general_operand" "fG,m,fG,fG,*r,*r, m,*r"))]
"! memory_operand (operands[0], SFmode)
|| ! memory_operand (operands[1], SFmode)"
"@
getf.s %0 = %F1
setf.s %0 = %1
mov %0 = %1
- ld4%O1 %0 = %1"
- [(set_attr "type" "F,M,M,M,M,A,M")])
+ ld4%O1 %0 = %1%P1
+ st4%Q0 %0 = %1%P0"
+ [(set_attr "type" "F,M,M,M,M,A,M,M")])
(define_expand "movdf"
[(set (match_operand:DF 0 "general_operand" "")
operands[1] = copy_to_mode_reg (DFmode, operands[1]);
}")
-;; ??? movsf has a r/m alternative, movdf doesn't.
-
(define_insn "*movdf_internal"
- [(set (match_operand:DF 0 "nonimmediate_operand" "=f,f,m,*r,f,*r")
- (match_operand:DF 1 "general_operand" "fG,m,fG,fG,*r,*r"))]
+ [(set (match_operand:DF 0 "nonimmediate_operand" "=f,f, m,*r, f,*r,*r, m")
+ (match_operand:DF 1 "general_operand" "fG,m,fG,fG,*r,*r, m,*r"))]
"! memory_operand (operands[0], DFmode)
|| ! memory_operand (operands[1], DFmode)"
"@
stfd %0 = %F1%P0
getf.d %0 = %F1
setf.d %0 = %1
- mov %0 = %1"
- [(set_attr "type" "F,M,M,M,M,A")])
+ mov %0 = %1
+ ld8%O1 %0 = %1%P1
+ st8%Q0 %0 = %1%P0"
+ [(set_attr "type" "F,M,M,M,M,A,M,M")])
(define_expand "movxf"
[(set (match_operand:XF 0 "general_operand" "")
}")
(define_insn "*movxf_internal"
- [(set (match_operand:XF 0 "nonimmediate_operand" "=f,f,m")
- (match_operand:XF 1 "general_operand" "fG,m,fG"))]
+ [(set (match_operand:XF 0 "nonimmediate_operand" "=f,f, m")
+ (match_operand:XF 1 "general_operand" "fG,m,fG"))]
"! memory_operand (operands[0], XFmode)
|| ! memory_operand (operands[1], XFmode)"
"@
[(set_attr "type" "I")])
(define_insn "extendsidi2"
- [(set (match_operand:DI 0 "register_operand" "=r,*e")
- (sign_extend:DI (match_operand:SI 1 "register_operand" "r,*e")))]
+ [(set (match_operand:DI 0 "register_operand" "=r,*f")
+ (sign_extend:DI (match_operand:SI 1 "register_operand" "r,*f")))]
""
"@
sxt4 %0 = %1
[(set_attr "type" "I,M")])
(define_insn "zero_extendsidi2"
- [(set (match_operand:DI 0 "register_operand" "=r,r,*e")
- (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "r,m,*e")))]
+ [(set (match_operand:DI 0 "register_operand" "=r,r,*f")
+ (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "r,m,*f")))]
""
"@
zxt4 %0 = %1
(define_insn "floatdixf2"
[(set (match_operand:XF 0 "register_operand" "=f")
- (float:XF (match_operand:DI 1 "register_operand" "e")))]
+ (float:XF (match_operand:DI 1 "register_operand" "f")))]
""
"fcvt.xf %0 = %1"
[(set_attr "type" "F")])
(define_insn "fix_truncsfdi2"
- [(set (match_operand:DI 0 "register_operand" "=e")
+ [(set (match_operand:DI 0 "register_operand" "=f")
(fix:DI (match_operand:SF 1 "register_operand" "f")))]
""
"fcvt.fx.trunc %0 = %1%B0"
[(set_attr "type" "F")])
(define_insn "fix_truncdfdi2"
- [(set (match_operand:DI 0 "register_operand" "=e")
+ [(set (match_operand:DI 0 "register_operand" "=f")
(fix:DI (match_operand:DF 1 "register_operand" "f")))]
""
"fcvt.fx.trunc %0 = %1%B0"
(define_insn "floatunsdisf2"
[(set (match_operand:SF 0 "register_operand" "=f")
- (unsigned_float:SF (match_operand:DI 1 "register_operand" "e")))]
+ (unsigned_float:SF (match_operand:DI 1 "register_operand" "f")))]
""
"fcvt.xuf.s %0 = %1%B0"
[(set_attr "type" "F")])
(define_insn "floatunsdidf2"
[(set (match_operand:DF 0 "register_operand" "=f")
- (unsigned_float:DF (match_operand:DI 1 "register_operand" "e")))]
+ (unsigned_float:DF (match_operand:DI 1 "register_operand" "f")))]
""
"fcvt.xuf.d %0 = %1%B0"
[(set_attr "type" "F")])
(define_insn "fixuns_truncsfdi2"
- [(set (match_operand:DI 0 "register_operand" "=e")
+ [(set (match_operand:DI 0 "register_operand" "=f")
(unsigned_fix:DI (match_operand:SF 1 "register_operand" "f")))]
""
"fcvt.fxu.trunc %0 = %1%B0"
[(set_attr "type" "F")])
(define_insn "fixuns_truncdfdi2"
- [(set (match_operand:DI 0 "register_operand" "=e")
+ [(set (match_operand:DI 0 "register_operand" "=f")
(unsigned_fix:DI (match_operand:DF 1 "register_operand" "f")))]
""
"fcvt.fxu.trunc %0 = %1%B0"
;; ??? Could add maddsi3 patterns patterned after the madddi3 patterns.
(define_insn "*mulsi3_internal"
- [(set (match_operand:SI 0 "register_operand" "=e")
- (mult:SI (match_operand:SI 1 "register_operand" "e")
- (match_operand:SI 2 "nonmemory_operand" "e")))]
+ [(set (match_operand:SI 0 "register_operand" "=f")
+ (mult:SI (match_operand:SI 1 "register_operand" "f")
+ (match_operand:SI 2 "nonmemory_operand" "f")))]
""
"xma.l %0 = %1, %2, f0%B0"
[(set_attr "type" "F")])
[(set_attr "type" "A")])
(define_insn "muldi3"
- [(set (match_operand:DI 0 "register_operand" "=e")
- (mult:DI (match_operand:DI 1 "register_operand" "e")
- (match_operand:DI 2 "register_operand" "e")))]
+ [(set (match_operand:DI 0 "register_operand" "=f")
+ (mult:DI (match_operand:DI 1 "register_operand" "f")
+ (match_operand:DI 2 "register_operand" "f")))]
""
"xma.l %0 = %1, %2, f0%B0"
[(set_attr "type" "F")])
;; ??? Maybe we should change how adds are canonicalized.
(define_insn "*madddi3"
- [(set (match_operand:DI 0 "register_operand" "=e")
- (plus:DI (mult:DI (match_operand:DI 1 "register_operand" "e")
- (match_operand:DI 2 "register_operand" "e"))
- (match_operand:DI 3 "register_operand" "e")))
+ [(set (match_operand:DI 0 "register_operand" "=f")
+ (plus:DI (mult:DI (match_operand:DI 1 "register_operand" "f")
+ (match_operand:DI 2 "register_operand" "f"))
+ (match_operand:DI 3 "register_operand" "f")))
(clobber (match_scratch:DI 4 "=X"))]
""
"xma.l %0 = %1, %2, %3%B0"
(define_insn "*madddi3_elim"
[(set (match_operand:DI 0 "register_operand" "=&r")
- (plus:DI (plus:DI (mult:DI (match_operand:DI 1 "register_operand" "e")
- (match_operand:DI 2 "register_operand" "e"))
- (match_operand:DI 3 "register_operand" "e"))
+ (plus:DI (plus:DI (mult:DI (match_operand:DI 1 "register_operand" "f")
+ (match_operand:DI 2 "register_operand" "f"))
+ (match_operand:DI 3 "register_operand" "f"))
(match_operand:DI 4 "nonmemory_operand" "rI")))
- (clobber (match_scratch:DI 5 "=e"))]
+ (clobber (match_scratch:DI 5 "=f"))]
"reload_in_progress"
"#"
[(set_attr "type" "unknown")])
;; to generate them.
(define_insn "smuldi3_highpart"
- [(set (match_operand:DI 0 "register_operand" "=e")
+ [(set (match_operand:DI 0 "register_operand" "=f")
(truncate:DI
(lshiftrt:TI
- (mult:TI (sign_extend:TI (match_operand:DI 1 "register_operand" "e"))
- (sign_extend:TI (match_operand:DI 2 "register_operand" "e")))
+ (mult:TI (sign_extend:TI (match_operand:DI 1 "register_operand" "f"))
+ (sign_extend:TI (match_operand:DI 2 "register_operand" "f")))
(const_int 64))))]
""
"xma.h %0 = %1, %2, f0%B0"
[(set_attr "type" "F")])
(define_insn "umuldi3_highpart"
- [(set (match_operand:DI 0 "register_operand" "=e")
+ [(set (match_operand:DI 0 "register_operand" "=f")
(truncate:DI
(lshiftrt:TI
- (mult:TI (zero_extend:TI (match_operand:DI 1 "register_operand" "e"))
- (zero_extend:TI (match_operand:DI 2 "register_operand" "e")))
+ (mult:TI (zero_extend:TI (match_operand:DI 1 "register_operand" "f"))
+ (zero_extend:TI (match_operand:DI 2 "register_operand" "f")))
(const_int 64))))]
""
"xma.hu %0 = %1, %2, f0%B0"
;; ::::::::::::::::::::
(define_insn "anddi3"
- [(set (match_operand:DI 0 "register_operand" "=r,*e")
- (and:DI (match_operand:DI 1 "register_operand" "%r,*e")
- (match_operand:DI 2 "reg_or_8bit_operand" "rK,*e")))]
+ [(set (match_operand:DI 0 "register_operand" "=r,*f")
+ (and:DI (match_operand:DI 1 "register_operand" "%r,*f")
+ (match_operand:DI 2 "reg_or_8bit_operand" "rK,*f")))]
""
"@
and %0 = %2, %1
[(set_attr "type" "A,F")])
(define_insn "*andnot"
- [(set (match_operand:DI 0 "register_operand" "=r,*e")
- (and:DI (not:DI (match_operand:DI 1 "register_operand" "r,*e"))
- (match_operand:DI 2 "reg_or_8bit_operand" "rK,*e")))]
+ [(set (match_operand:DI 0 "register_operand" "=r,*f")
+ (and:DI (not:DI (match_operand:DI 1 "register_operand" "r,*f"))
+ (match_operand:DI 2 "reg_or_8bit_operand" "rK,*f")))]
""
"@
andcm %0 = %2, %1
[(set_attr "type" "A,F")])
(define_insn "iordi3"
- [(set (match_operand:DI 0 "register_operand" "=r,*e")
- (ior:DI (match_operand:DI 1 "register_operand" "%r,*e")
- (match_operand:DI 2 "reg_or_8bit_operand" "rK,*e")))]
+ [(set (match_operand:DI 0 "register_operand" "=r,*f")
+ (ior:DI (match_operand:DI 1 "register_operand" "%r,*f")
+ (match_operand:DI 2 "reg_or_8bit_operand" "rK,*f")))]
""
"@
or %0 = %2, %1
[(set_attr "type" "A,F")])
(define_insn "xordi3"
- [(set (match_operand:DI 0 "register_operand" "=r,*e")
- (xor:DI (match_operand:DI 1 "register_operand" "%r,*e")
- (match_operand:DI 2 "reg_or_8bit_operand" "rK,*e")))]
+ [(set (match_operand:DI 0 "register_operand" "=r,*f")
+ (xor:DI (match_operand:DI 1 "register_operand" "%r,*f")
+ (match_operand:DI 2 "reg_or_8bit_operand" "rK,*f")))]
""
"@
xor %0 = %2, %1
(return)
(pc)))]
"ia64_direct_return ()"
- "(%%J0) br.ret%+.many rp"
+ "(%J0) br.ret%+.many rp"
[(set_attr "type" "B")
(set_attr "predicable" "no")])
(pc)
(return)))]
"ia64_direct_return ()"
- "(%%j0) br.ret%+.many rp"
+ "(%j0) br.ret%+.many rp"
[(set_attr "type" "B")
(set_attr "predicable" "no")])
(define_insn "fr_spill"
[(set (match_operand:XF 0 "memory_operand" "=m")
- (unspec:XF [(match_operand:XF 1 "register_operand" "f*e")] 3))]
+ (unspec:XF [(match_operand:XF 1 "register_operand" "f")] 3))]
""
"stf.spill %0 = %1%P0"
[(set_attr "type" "M")])
(define_insn "fr_restore"
- [(set (match_operand:XF 0 "register_operand" "=f*e")
+ [(set (match_operand:XF 0 "register_operand" "=f")
(unspec:XF [(match_operand:XF 1 "memory_operand" "m")] 4))]
""
"ldf.fill %0 = %1%P1"
[(unspec_volatile [(const_int 0)] 5)
(use (match_operand:DI 0 "register_operand" "r"))]
""
- "flushrs\; \
- mov r19=ar.rsc\; \
- ;;\; \
- and r19=0x1c,r19\; \
- ;;\; \
- mov ar.rsc=r19\; \
- ;;\; \
- mov ar.bspstore=%0\; \
- ;;\; \
- or r19=0x3,r19\; \
- ;;\; \
- loadrs\; \
- invala\; \
- ;;\; \
- mov ar.rsc=r19\;"
+ "flushrs\;mov r19=ar.rsc\;;;\;and r19=0x1c,r19\;;;\;mov ar.rsc=r19\;;;\;mov ar.bspstore=%0\;;;\;or r19=0x3,r19\;;;\;loadrs\;invala\;;;\;mov ar.rsc=r19"
[(set_attr "type" "unknown")
(set_attr "predicable" "no")])
(define_insn "flushrs"
[(unspec [(const_int 0)] 21)]
""
- ";; \; flushrs"
+ ";;\;flushrs"
[(set_attr "type" "M")])
\f
;; ::::::::::::::::::::