As part of the final cleanup of aarch64_internal_mov_immediate a return was accidenta...

As part of the final cleanup of aarch64_internal_mov_immediate a return was
accidentally removed.  This causes the 2-instruction case to fallthrough
into the general case even when it found a match.  An example immediate is
0xcccccccccccccccd which was using 2 instructions in GCC5 but now requires 4.
Adding the return fixes the regressions.

2016-02-17  Wilco Dijkstra  <wdijkstr@arm.com>

    gcc/
	* config/aarch64/aarch64.c (aarch64_internal_mov_immediate):
	Add missing return.

From-SVN: r233490

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 2178ae6095d45692562bd3dd71e1990b2abc8bb9..607b33fa2e42521c2b38ec812d5cf0a504269bee 100644 (file)
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,8 @@
+2016-02-17  Wilco Dijkstra  <wdijkstr@arm.com>
+
+       * config/aarch64/aarch64.c (aarch64_internal_mov_immediate):
+       Add missing return.
+
 2016-02-17  Eric Botcazou  <ebotcazou@adacore.com>
 
        * config/visium/visium.c (machine_libfunc_index): New enum.

diff --git a/gcc/config/aarch64/aarch64.c b/gcc/config/aarch64/aarch64.c
index df7023f6c1ade3d4bf768da16bd9887a6dab03cc..923a4b3154289b97d434d1c541bb600598c038f4 100644 (file)
--- a/gcc/config/aarch64/aarch64.c
+++ b/gcc/config/aarch64/aarch64.c
@@ -1632,6 +1632,7 @@ aarch64_internal_mov_immediate (rtx dest, rtx imm, bool generate,
              emit_insn (gen_insv_immdi (dest, GEN_INT (i),
                                         GEN_INT ((val >> i) & 0xffff)));
            }
+         return 2;
        }
     }