expmed.c (store_bit_field_1): Properly truncate the paradoxical subreg of op0 to...

	* expmed.c (store_bit_field_1): Properly truncate the paradoxical
	subreg of op0 to the original op0.

testsuite/
	* gcc.target/mips/ins-2.c: New test.

From-SVN: r143288

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 28a86bc53ac592120ab72c6116461dfa21a00a99..ba53e7df4cc917205780d3027dd2aa1230d8f0d1 100644 (file)
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,8 @@
+2009-01-11  Adam Nemet  <anemet@caviumnetworks.com>
+
+       * expmed.c (store_bit_field_1): Properly truncate the paradoxical
+       subreg of op0 to the original op0.
+
 2009-01-11  Laurent GUERBY <laurent@guerby.net>
 
        * doc/sourcebuild.texi (Source Tree): Move up intl and fixinc.

diff --git a/gcc/expmed.c b/gcc/expmed.c
index 50eb45fa65178e0d49c4b4d4d360b22bbdf2bae5..9ee5f29883d064975e6b1bc07a102cceb2751053 100644 (file)
--- a/gcc/expmed.c
+++ b/gcc/expmed.c
@@ -749,6 +749,16 @@ store_bit_field_1 (rtx str_rtx, unsigned HOST_WIDE_INT bitsize,
       if (pat)
        {
          emit_insn (pat);
+
+         /* If the mode of the insertion is wider than the mode of the
+            target register we created a paradoxical subreg for the
+            target.  Truncate the paradoxical subreg of the target to
+            itself properly.  */
+         if (!TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (GET_MODE (op0)),
+                                     GET_MODE_BITSIZE (op_mode))
+             && (REG_P (xop0)
+                 || GET_CODE (xop0) == SUBREG))
+             convert_move (op0, xop0, true);
          return true;
        }
       delete_insns_since (last);

diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog
index 289a33027fa0b5911784897122f237bfba9230c8..41f53a92da6248ed0a4e8629fdcd0d64b0276b28 100644 (file)
--- a/gcc/testsuite/ChangeLog
+++ b/gcc/testsuite/ChangeLog
@@ -1,3 +1,7 @@
+2009-01-11  Adam Nemet  <anemet@caviumnetworks.com>
+
+       * gcc.target/mips/ins-2.c: New test.
+
 2009-01-11  H.J. Lu  <hongjiu.lu@intel.com>
 
        PR testsuite/38809

diff --git a/gcc/testsuite/gcc.target/mips/ins-2.c b/gcc/testsuite/gcc.target/mips/ins-2.c
new file mode 100644 (file)
index 0000000..a71e6c0
--- /dev/null
+++ b/gcc/testsuite/gcc.target/mips/ins-2.c
@@ -0,0 +1,27 @@
+/* { dg-do compile } */
+/* { dg-options "-O -meb isa_rev>=2 -mgp64" } */
+/* { dg-final { scan-assembler-times "\tins\t|\tdins\t" 1 } } */
+/* { dg-final { scan-assembler-times "\tsll\t|\tins\t" 1 } } */
+
+/* When inserting something into the top bit of a 32-bit structure,
+   we must make sure that the register remains properly sign-extended.
+   There are two ways of doing this:
+ 
+     - use purely 32-bit bit manipulations (a single INS, matched twice here).
+     - use a 64-bit bit manipulation (DINS), and sign-extend the result.  We
+     check for this extension using SLL.  */
+
+struct s
+{
+  int a:3;
+  int b:29;
+};
+
+NOMIPS16 void
+f (int a)
+{
+  struct s s;
+  asm volatile ("" : "=r"(s));
+  s.a = a;
+  asm volatile ("" :: "r"(s));
+}