Revert "RISC-V: Support RVV VFNMSAC rounding mode intrinsic API"

This reverts commit 236ec7aac051a062dc961b3c1482925893ee6e21.

diff --git a/gcc/config/riscv/riscv-vector-builtins-bases.cc b/gcc/config/riscv/riscv-vector-builtins-bases.cc
index 9c6ca8d1ddc6ad6abb79480475b2ea772e2a8197..e73051bbd8900cf6add9ce3227fb5582ecf4fb67 100644 (file)
--- a/gcc/config/riscv/riscv-vector-builtins-bases.cc
+++ b/gcc/config/riscv/riscv-vector-builtins-bases.cc
@@ -423,28 +423,6 @@ public:
   }
 };
 
-/* Implements below instructions for frm
-   - vfnmsac
-*/
-class vfnmsac_frm : public function_base
-{
-public:
-  bool has_rounding_mode_operand_p () const override { return true; }
-
-  bool has_merge_operand_p () const override { return false; }
-
-  rtx expand (function_expander &e) const override
-  {
-    if (e.op_info->op == OP_TYPE_vf)
-      return e.use_ternop_insn (
-       true, code_for_pred_mul_neg_scalar (PLUS, e.vector_mode ()));
-    if (e.op_info->op == OP_TYPE_vv)
-      return e.use_ternop_insn (
-       true, code_for_pred_mul_neg (PLUS, e.vector_mode ()));
-    gcc_unreachable ();
-  }
-};
-
 /* Implements vrsub.  */
 class vrsub : public function_base
 {
@@ -2207,7 +2185,6 @@ static CONSTEXPR const widen_binop_frm<MULT> vfwmul_frm_obj;
 static CONSTEXPR const vfmacc vfmacc_obj;
 static CONSTEXPR const vfmacc_frm vfmacc_frm_obj;
 static CONSTEXPR const vfnmsac vfnmsac_obj;
-static CONSTEXPR const vfnmsac_frm vfnmsac_frm_obj;
 static CONSTEXPR const vfmadd vfmadd_obj;
 static CONSTEXPR const vfnmsub vfnmsub_obj;
 static CONSTEXPR const vfnmacc vfnmacc_obj;
@@ -2446,7 +2423,6 @@ BASE (vfwmul_frm)
 BASE (vfmacc)
 BASE (vfmacc_frm)
 BASE (vfnmsac)
-BASE (vfnmsac_frm)
 BASE (vfmadd)
 BASE (vfnmsub)
 BASE (vfnmacc)

diff --git a/gcc/config/riscv/riscv-vector-builtins-bases.h b/gcc/config/riscv/riscv-vector-builtins-bases.h
index 28eec2c3e997883fb12a151c47348901fe720097..ca8a6dc1cc3ce837c24598f8c6a1f425c583b3cc 100644 (file)
--- a/gcc/config/riscv/riscv-vector-builtins-bases.h
+++ b/gcc/config/riscv/riscv-vector-builtins-bases.h
@@ -162,7 +162,6 @@ extern const function_base *const vfwmul_frm;
 extern const function_base *const vfmacc;
 extern const function_base *const vfmacc_frm;
 extern const function_base *const vfnmsac;
-extern const function_base *const vfnmsac_frm;
 extern const function_base *const vfmadd;
 extern const function_base *const vfnmsub;
 extern const function_base *const vfnmacc;

diff --git a/gcc/config/riscv/riscv-vector-builtins-functions.def b/gcc/config/riscv/riscv-vector-builtins-functions.def
index 9c964ae6fcb61730f7c4b700d2da8c3f303ff2b5..8bae7e616ba0720f610784cb2a240b39b84d0cca 100644 (file)
--- a/gcc/config/riscv/riscv-vector-builtins-functions.def
+++ b/gcc/config/riscv/riscv-vector-builtins-functions.def
@@ -354,8 +354,6 @@ DEF_RVV_FUNCTION (vfnmacc_frm, alu_frm, full_preds, f_vvvv_ops)
 DEF_RVV_FUNCTION (vfnmacc_frm, alu_frm, full_preds, f_vvfv_ops)
 DEF_RVV_FUNCTION (vfmsac_frm, alu_frm, full_preds, f_vvvv_ops)
 DEF_RVV_FUNCTION (vfmsac_frm, alu_frm, full_preds, f_vvfv_ops)
-DEF_RVV_FUNCTION (vfnmsac_frm, alu_frm, full_preds, f_vvvv_ops)
-DEF_RVV_FUNCTION (vfnmsac_frm, alu_frm, full_preds, f_vvfv_ops)
 
 // 13.7. Vector Widening Floating-Point Fused Multiply-Add Instructions
 DEF_RVV_FUNCTION (vfwmacc, alu, full_preds, f_wwvv_ops)

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-single-negate-multiply-sub.c b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-single-negate-multiply-sub.c
deleted file mode 100644 (file)
index c308923..0000000
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-single-negate-multiply-sub.c
+++ /dev/null
@@ -1,47 +0,0 @@
-/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64 -O3 -Wno-psabi" } */
-
-#include "riscv_vector.h"
-
-typedef float float32_t;
-
-vfloat32m1_t
-test_riscv_vfnmsac_vv_f32m1_rm (vfloat32m1_t vd, vfloat32m1_t op1,
-                               vfloat32m1_t op2, size_t vl) {
-  return __riscv_vfnmsac_vv_f32m1_rm (vd, op1, op2, 0, vl);
-}
-
-vfloat32m1_t
-test_vfnmsac_vv_f32m1_rm_m (vbool32_t mask, vfloat32m1_t vd, vfloat32m1_t op1,
-                           vfloat32m1_t op2, size_t vl) {
-  return __riscv_vfnmsac_vv_f32m1_rm_m (mask, vd, op1, op2, 1, vl);
-}
-
-vfloat32m1_t
-test_vfnmsac_vf_f32m1_rm (vfloat32m1_t vd, float32_t op1, vfloat32m1_t op2,
-                         size_t vl) {
-  return __riscv_vfnmsac_vf_f32m1_rm (vd, op1, op2, 2, vl);
-}
-
-vfloat32m1_t
-test_vfnmsac_vf_f32m1_rm_m (vfloat32m1_t vd, vbool32_t mask, float32_t op1,
-                           vfloat32m1_t op2, size_t vl) {
-  return __riscv_vfnmsac_vf_f32m1_rm_m (mask, vd, op1, op2, 3, vl);
-}
-
-vfloat32m1_t
-test_riscv_vfnmsac_vv_f32m1 (vfloat32m1_t vd, vfloat32m1_t op1,
-                            vfloat32m1_t op2, size_t vl) {
-  return __riscv_vfnmsac_vv_f32m1 (vd, op1, op2, vl);
-}
-
-vfloat32m1_t
-test_vfnmsac_vv_f32m1_m (vbool32_t mask, vfloat32m1_t vd, vfloat32m1_t op1,
-                        vfloat32m1_t op2, size_t vl) {
-  return __riscv_vfnmsac_vv_f32m1_m (mask, vd, op1, op2, vl);
-}
-
-/* { dg-final { scan-assembler-times {vfnmsac\.v[vf]\s+v[0-9]+,\s*[fav]+[0-9]+,\s*v[0-9]+} 6 } } */
-/* { dg-final { scan-assembler-times {frrm\s+[axs][0-9]+} 4 } } */
-/* { dg-final { scan-assembler-times {fsrm\s+[axs][0-9]+} 4 } } */
-/* { dg-final { scan-assembler-times {fsrmi\s+[01234]} 4 } } */