]> gcc.gnu.org Git - gcc.git/commitdiff
Daily bump.
authorGCC Administrator <gccadmin@gcc.gnu.org>
Thu, 4 Jul 2024 00:18:38 +0000 (00:18 +0000)
committerGCC Administrator <gccadmin@gcc.gnu.org>
Thu, 4 Jul 2024 00:18:38 +0000 (00:18 +0000)
ChangeLog
gcc/ChangeLog
gcc/DATESTAMP
gcc/ada/ChangeLog
gcc/c-family/ChangeLog
gcc/fortran/ChangeLog
gcc/testsuite/ChangeLog

index e9c3e0aadc61121d61c246f3633d912a5ecc67f0..c9e75216a7a8c76567a50ce25b1b7cafbfa361b8 100644 (file)
--- a/ChangeLog
+++ b/ChangeLog
@@ -1,3 +1,7 @@
+2024-07-03  Prathamesh Kulkarni  <prathameshk@nvidia.com>
+
+       * MAINTAINERS: Update my email address and add myself to DCO.
+
 2024-07-01  Claudiu Zissulescu  <claziss@gmail.com>
 
        * MAINTAINERS: Update claziss email address.
index 91ad053298ebae5ce2adf63cd103c421caaafd6b..6ea3039e1fb973fefa171a9e8989510f96e29886 100644 (file)
@@ -1,3 +1,154 @@
+2024-07-03  Jeff Law  <jlaw@ventanamicro.com>
+
+       * reorg.cc (relax_delay_slots): Do not optimize a conditional
+       jump around an unconditional jump/return in the presence of
+       a text section switch.
+
+2024-07-03  John David Anglin  <danglin@gcc.gnu.org>
+
+       Revert:
+       2023-10-05  John David Anglin  <danglin@gcc.gnu.org>
+
+       * config/pa/pa32-linux.h (MALLOC_ABI_ALIGNMENT): Delete.
+
+2024-07-03  Palmer Dabbelt  <palmer@rivosinc.com>
+
+       * doc/invoke.texi: Describe -march behavior for dependent extensions on
+       RISC-V.
+
+2024-07-03  Gianluca Guida  <gianluca@rivosinc.com>
+           Patrick O'Neill  <patrick@rivosinc.com>
+
+       * common/config/riscv/riscv-common.cc
+       (riscv_subset_list::to_string): Skip zabha when not supported by
+       the assembler.
+       * config.in: Regenerate.
+       * config/riscv/arch-canonicalize: Make zabha imply zaamo.
+       * config/riscv/iterators.md (amobh): Add iterator for amo
+       byte/halfword.
+       * config/riscv/riscv.opt: Add zabha.
+       * config/riscv/sync.md (atomic_<atomic_optab><mode>): Add
+       subword atomic op pattern.
+       (zabha_atomic_fetch_<atomic_optab><mode>): Add subword
+       atomic_fetch op pattern.
+       (lrsc_atomic_fetch_<atomic_optab><mode>): Prefer zabha over lrsc
+       for subword atomic ops.
+       (zabha_atomic_exchange<mode>): Add subword atomic exchange
+       pattern.
+       (lrsc_atomic_exchange<mode>): Prefer zabha over lrsc for subword
+       atomic exchange ops.
+       * configure: Regenerate.
+       * configure.ac: Add zabha assembler check.
+       * doc/sourcebuild.texi: Add zabha documentation.
+
+2024-07-03  Pan Li  <pan2.li@intel.com>
+
+       PR target/115763
+       * config/riscv/vector.md (*pred_broadcast<mode>): Split into
+       zvfh and zvfhmin part.
+       (*pred_broadcast<mode>_zvfh): New define_insn for zvfh part.
+       (*pred_broadcast<mode>_zvfhmin): Ditto but for zvfhmin.
+
+2024-07-03  Pan Li  <pan2.li@intel.com>
+
+       * match.pd: Allow any otype is less than itype truncation.
+
+2024-07-03  Pan Li  <pan2.li@intel.com>
+
+       * tree-vect-patterns.cc (gimple_unsigned_integer_sat_trunc): Add
+       new decl generated by match.
+       (vect_recog_sat_trunc_pattern): Add new func impl to recog the
+       .SAT_TRUNC pattern.
+
+2024-07-03  Richard Biener  <rguenther@suse.de>
+
+       * tree-vect-slp.cc (vectorizable_slp_permutation_1): Remove
+       redundant dump.
+
+2024-07-03  Jennifer Schmitz  <jschmitz@nvidia.com>
+
+       * match.pd: Fold x/sqrt(x) to sqrt(x).
+
+2024-07-03  Alexandre Oliva  <oliva@adacore.com>
+
+       * dwarf2out.cc (modified_type_die): Follow name's debug type.
+
+2024-07-03  Alexandre Oliva  <oliva@adacore.com>
+
+       PR target/113719
+       * config/i386/i386-options.cc
+       (ix86_override_options_after_change_1): Add opts and opts_set
+       parms, operate on them, after factoring out of...
+       (ix86_override_options_after_change): ... this.  Restore calls
+       of ix86_default_align and ix86_recompute_optlev_based_flags.
+       (ix86_option_override_internal): Call the factored-out bits.
+
+2024-07-03  Kyrylo Tkachov  <ktkachov@nvidia.com>
+
+       PR target/115475
+       * config/aarch64/aarch64-c.cc (aarch64_update_cpp_builtins):
+       Define __ARM_FEATURE_SVE_BF16 for TARGET_SVE_BF16.
+
+2024-07-03  Kyrylo Tkachov  <ktkachov@nvidia.com>
+
+       PR target/115457
+       * config/aarch64/aarch64-c.cc (aarch64_update_cpp_builtins):
+       Define __ARM_FEATURE_BF16 for TARGET_BF16_FP.
+
+2024-07-03  Richard Biener  <rguenther@suse.de>
+
+       * tree-vect-slp.cc (bst_traits::hash): Handle NULL elements
+       in SLP_TREE_SCALAR_STMTS.
+       (vect_print_slp_tree): Likewise.
+       (vect_mark_slp_stmts): Likewise.
+       (vect_mark_slp_stmts_relevant): Likewise.
+       (vect_find_last_scalar_stmt_in_slp): Likewise.
+       (vect_bb_slp_mark_live_stmts): Likewise.
+       (vect_slp_prune_covered_roots): Likewise.
+       (vect_bb_partition_graph_r): Likewise.
+       (vect_remove_slp_scalar_calls): Likewise.
+       (vect_slp_gather_vectorized_scalar_stmts): Likewise.
+       (vect_bb_slp_scalar_cost): Likewise.
+       (vect_contains_pattern_stmt_p): Likewise.
+       (vect_slp_convert_to_external): Likewise.
+       (vect_find_first_scalar_stmt_in_slp): Likewise.
+       (vect_optimize_slp_pass::remove_redundant_permutations): Likewise.
+       (vect_slp_analyze_node_operations_1): Likewise.
+       (vect_schedule_slp_node): Likewise.
+       * tree-vect-stmts.cc (can_vectorize_live_stmts): Likewise.
+       (vectorizable_shift): Likewise.
+       * tree-vect-data-refs.cc (vect_slp_analyze_load_dependences):
+       Handle NULL elements in SLP_TREE_SCALAR_STMTS.
+
+2024-07-03  Georg-Johann Lay  <avr@gjlay.de>
+
+       PR target/98762
+       * config/avr/avr.cc (avr_out_movqi_r_mr_reg_disp_tiny): Properly
+       restore the base register when it is partially clobbered.
+
+2024-07-03  Tamar Christina  <tamar.christina@arm.com>
+
+       PR tree-optimization/114932
+       * tree-ssa-loop-ivopts.cc (constant_multiple_of): Use
+       aff_combination_constant_multiple_p instead.
+
+2024-07-03  Tamar Christina  <tamar.christina@arm.com>
+
+       PR tree-optimization/114932
+       * tree-affine.cc (wide_int_constant_multiple_p): Support 0 and 0 being
+       multiples.
+
+2024-07-03  Richard Sandiford  <richard.sandiford@arm.com>
+
+       * df.h (DF_LR_DCE): New df_problem_id.
+       (df_lr_dce): New macro.
+       * df-core.cc (rest_of_handle_df_finish): Check for a null free_fun.
+       * df-problems.cc (df_lr_finalize): Split out fast DCE handling to...
+       (df_lr_dce_finalize): ...this new function.
+       (problem_LR_DCE): New df_problem.
+       (df_lr_add_problem): Register LR_DCE rather than LR itself.
+       * dce.cc (fast_dce): Clear df_lr_dce->solutions_dirty.
+
 2024-07-02  Pengxuan Zheng  <quic_pzheng@quicinc.com>
 
        PR target/113859
index f8fa5e4aa67e59875617690fc91a5b6d2a03d109..efaf824b8cd88a10b6ee00ed9cb200909ec95e77 100644 (file)
@@ -1 +1 @@
-20240703
+20240704
index 02db1fbecafe0aba7e20c310294c173b46d42154..986adf36dd23da9e200e799a5fd966f3e9a3f87f 100644 (file)
@@ -1,3 +1,28 @@
+2024-07-03  Alexandre Oliva  <oliva@adacore.com>
+
+       * gcc-interface/misc.cc (gnat_get_array_descr_info): Only follow
+       TYPE_DEBUG_TYPE if TYPE_CAN_HAVE_DEBUG_TYPE_P.
+       * gcc-interface/utils.cc (sized_type_hash): New struct.
+       (sized_type_hasher): New struct.
+       (sized_type_hash_table): New variable.
+       (init_gnat_utils): Allocate it.
+       (destroy_gnat_utils): Release it.
+       (sized_type_hasher::equal): New.
+       (hash_sized_type): New.
+       (canonicalize_sized_type): New.
+       (make_type_from_size): Use it to cache packed variants.  Fix
+       type reuse by combining biased_p and for_biased earlier.  Hold
+       the combination in for_biased, adjusting later uses.
+
+2024-07-03  Alexandre Oliva  <oliva@adacore.com>
+
+       * gcc-interface/cuintp.cc (UI_To_gnu): Add mode that selects a
+       wide enough unsigned type.  Fail if the constant exceeds the
+       representable numbers.
+       * gcc-interface/decl.cc (gnat_to_gnu_entity): Use it for
+       numerator and denominator of fixed-point types.  In case of
+       failure, fall back to an indeterminate fraction.
+
 2024-07-02  Eric Botcazou  <ebotcazou@adacore.com>
 
        * exp_ch4.adb (Expand_Concatenate): In the case where an operand
index f111c5982ab9412fe5b8705347f7771451c03510..edfee4d9760eb6206cb1f61799cba58fea755eef 100644 (file)
@@ -1,3 +1,10 @@
+2024-07-03  Lewis Hyatt  <lhyatt@gmail.com>
+
+       PR pch/115312
+       * c-opts.cc (c_common_init): Call c_init_preprocess() before
+       c_finish_options() so that a parser is available to process any
+       includes specified on the command line.
+
 2024-06-25  Andrew Pinski  <quic_apinski@quicinc.com>
 
        PR c++/115624
index d71616a840b5c69fcbd48ace81986cf1c67e2cb4..bc7a6f54a97cbd22464bbeb9380dea54accf0870 100644 (file)
@@ -1,3 +1,11 @@
+2024-07-03  Harald Anlauf  <anlauf@gmx.de>
+
+       PR fortran/115700
+       * trans-stmt.cc (trans_associate_var): When the associate target
+       is an array-valued character variable, the length is known at entry
+       of the associate block.  Move setting of string length of the
+       selector to the initialization part of the block.
+
 2024-07-01  Andrew Stubbs  <ams@baylibre.com>
            Thomas Schwinge  <thomas@codesourcery.com>
 
index 9aeec32f9e684e7f14011dd520a29f1134709c88..febb5244eea1ca239d87fdcb20adba5d98f5aecc 100644 (file)
@@ -1,3 +1,97 @@
+2024-07-03  Harald Anlauf  <anlauf@gmx.de>
+
+       PR fortran/115700
+       * gfortran.dg/associate_69.f90: New test.
+
+2024-07-03  Gianluca Guida  <gianluca@rivosinc.com>
+           Patrick O'Neill  <patrick@rivosinc.com>
+
+       * lib/target-supports.exp: Add zabha testsuite infra support.
+       * gcc.target/riscv/amo/inline-atomics-1.c: Remove zabha to continue to
+       test the lr/sc subword patterns.
+       * gcc.target/riscv/amo/inline-atomics-2.c: Ditto.
+       * gcc.target/riscv/amo/zalrsc-rvwmo-subword-amo-add-char-acq-rel.c: Ditto.
+       * gcc.target/riscv/amo/zalrsc-rvwmo-subword-amo-add-char-acquire.c: Ditto.
+       * gcc.target/riscv/amo/zalrsc-rvwmo-subword-amo-add-char-relaxed.c: Ditto.
+       * gcc.target/riscv/amo/zalrsc-rvwmo-subword-amo-add-char-release.c: Ditto.
+       * gcc.target/riscv/amo/zalrsc-rvwmo-subword-amo-add-char-seq-cst.c: Ditto.
+       * gcc.target/riscv/amo/zalrsc-ztso-subword-amo-add-char-acq-rel.c: Ditto.
+       * gcc.target/riscv/amo/zalrsc-ztso-subword-amo-add-char-acquire.c: Ditto.
+       * gcc.target/riscv/amo/zalrsc-ztso-subword-amo-add-char-relaxed.c: Ditto.
+       * gcc.target/riscv/amo/zalrsc-ztso-subword-amo-add-char-release.c: Ditto.
+       * gcc.target/riscv/amo/zalrsc-ztso-subword-amo-add-char-seq-cst.c: Ditto.
+       * gcc.target/riscv/amo/zabha-all-amo-ops-char-run.c: New test.
+       * gcc.target/riscv/amo/zabha-all-amo-ops-short-run.c: New test.
+       * gcc.target/riscv/amo/zabha-rvwmo-all-amo-ops-char.c: New test.
+       * gcc.target/riscv/amo/zabha-rvwmo-all-amo-ops-short.c: New test.
+       * gcc.target/riscv/amo/zabha-rvwmo-amo-add-char.c: New test.
+       * gcc.target/riscv/amo/zabha-rvwmo-amo-add-short.c: New test.
+       * gcc.target/riscv/amo/zabha-ztso-amo-add-char.c: New test.
+       * gcc.target/riscv/amo/zabha-ztso-amo-add-short.c: New test.
+
+2024-07-03  Luis Silva  <Luis.Silva1@synopsys.com>
+
+       * gcc.target/arc/pr9001184797.c: Fix compiler warnings.
+
+2024-07-03  Pan Li  <pan2.li@intel.com>
+
+       PR target/115763
+       * gcc.target/riscv/rvv/base/scalar_move-5.c: Adjust asm check.
+       * gcc.target/riscv/rvv/base/scalar_move-6.c: Ditto.
+       * gcc.target/riscv/rvv/base/scalar_move-7.c: Ditto.
+       * gcc.target/riscv/rvv/base/scalar_move-8.c: Ditto.
+       * gcc.target/riscv/rvv/base/pr115763-1.c: New test.
+       * gcc.target/riscv/rvv/base/pr115763-2.c: New test.
+
+2024-07-03  Jennifer Schmitz  <jschmitz@nvidia.com>
+
+       * gcc.dg/tree-ssa/sqrt_div.c: New test.
+
+2024-07-03  Alexandre Oliva  <oliva@adacore.com>
+
+       * gnat.dg/bias1.adb: Count occurrences of -7.*DW_AT_GNU_bias.
+
+2024-07-03  Kyrylo Tkachov  <ktkachov@nvidia.com>
+
+       PR target/115475
+       * gcc.target/aarch64/acle/bf16_sve_feature.c: New test.
+
+2024-07-03  Kyrylo Tkachov  <ktkachov@nvidia.com>
+
+       PR target/115457
+       * gcc.target/aarch64/acle/bf16_feature.c: New test.
+
+2024-07-03  Georg-Johann Lay  <avr@gjlay.de>
+
+       PR target/98762
+       * gcc.target/avr/torture/pr98762.c: New test.
+
+2024-07-03  liuhongt  <hongtao.liu@intel.com>
+
+       PR target/115748
+       * gcc.target/i386/avx512-check.h: Move runtime check into a
+       separate function and guard it with target ("no-avx").
+
+2024-07-03  Pan Li  <pan2.li@intel.com>
+
+       * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub_trunc-1.c:
+       Update vssubu check from vv to vx.
+       * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub_trunc-2.c:
+       Ditto.
+       * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub_trunc-3.c:
+       Ditto.
+
+2024-07-03  Richard Biener  <rguenther@suse.de>
+
+       PR tree-optimization/115764
+       * gcc.dg/vect/bb-slp-76.c: New testcase.
+
+2024-07-03  Lewis Hyatt  <lhyatt@gmail.com>
+
+       PR pch/115312
+       * g++.dg/pch/pr115312.C: New test.
+       * g++.dg/pch/pr115312.Hs: New test.
+
 2024-07-02  Pengxuan Zheng  <quic_pzheng@quicinc.com>
 
        PR target/113859
This page took 0.085146 seconds and 5 git commands to generate.