Revert some changes

diff --git a/gcc/config.gcc b/gcc/config.gcc
index 02004bee30b59edbce232d85143eb23c64e5f869..624e0dae191abaad974f2078b2e1b5084505bbd6 100644 (file)
--- a/gcc/config.gcc
+++ b/gcc/config.gcc
@@ -531,8 +531,7 @@ powerpc*-*-*)
        extra_headers="${extra_headers} ppu_intrinsics.h spu2vmx.h vec_types.h si2vmx.h"
        extra_headers="${extra_headers} amo.h"
        case x$with_cpu in
-           xpowerpc64 | xdefault64 | x6[23]0 | x970 | xG5 | xpower[3456789] \
-           | xpower1[01]|xpower6x|xrs64a|xcell|xa2|xe500mc64|xe5500|xe6500)
+           xpowerpc64|xdefault64|x6[23]0|x970|xG5|xpower[3456789]|xpower10|xpower6x|xrs64a|xcell|xa2|xe500mc64|xe5500|xe6500)
                cpu_is_64bit=yes
                ;;
        esac
@@ -5559,7 +5558,7 @@ case "${target}" in
                                eval "with_$which=405"
                                ;;
                        "" | common | native \
-                       | power[3456789] | power1[01] | power5+ | power6x \
+                       | power[3456789] | power10 | power5+ | power6x \
                        | powerpc | powerpc64 | powerpc64le \
                        | rs64 \
                        | 401 | 403 | 405 | 405fp | 440 | 440fp | 464 | 464fp \

diff --git a/gcc/config/rs6000/aix71.h b/gcc/config/rs6000/aix71.h
index 41037b3852d74eeb88c2d59bfdaf25d997198acb..24bc301e37d6a47091b35b216f81b2209c3cb260 100644 (file)
--- a/gcc/config/rs6000/aix71.h
+++ b/gcc/config/rs6000/aix71.h
@@ -79,7 +79,6 @@ do {                                                                  \
 #undef ASM_CPU_SPEC
 #define ASM_CPU_SPEC \
 "%{mcpu=native: %(asm_cpu_native); \
-  mcpu=power11: -mpwr11; \
   mcpu=power10: -mpwr10; \
   mcpu=power9: -mpwr9; \
   mcpu=power8: -mpwr8; \

diff --git a/gcc/config/rs6000/aix72.h b/gcc/config/rs6000/aix72.h
index fe59f8319b48c022b2d11183661fccc4f31d59a7..c43974f577afd44b3d350309a1e396c8e65509f2 100644 (file)
--- a/gcc/config/rs6000/aix72.h
+++ b/gcc/config/rs6000/aix72.h
@@ -79,7 +79,6 @@ do {                                                                  \
 #undef ASM_CPU_SPEC
 #define ASM_CPU_SPEC \
 "%{mcpu=native: %(asm_cpu_native); \
-  mcpu=power11: -mpwr11; \
   mcpu=power10: -mpwr10; \
   mcpu=power9: -mpwr9; \
   mcpu=power8: -mpwr8; \

diff --git a/gcc/config/rs6000/aix73.h b/gcc/config/rs6000/aix73.h
index 1318b0b3662d1ba0a380965e6949fb8e6be9d5e9..b1572bde81f963592d1cffd9fac2fbed579e4da9 100644 (file)
--- a/gcc/config/rs6000/aix73.h
+++ b/gcc/config/rs6000/aix73.h
@@ -79,7 +79,6 @@ do {                                                                  \
 #undef ASM_CPU_SPEC
 #define ASM_CPU_SPEC \
 "%{mcpu=native: %(asm_cpu_native); \
-  mcpu=power11: -mpwr11; \
   mcpu=power10: -mpwr10; \
   mcpu=power9: -mpwr9; \
   mcpu=power8: -mpwr8; \

diff --git a/gcc/config/rs6000/driver-rs6000.cc b/gcc/config/rs6000/driver-rs6000.cc
index f4900724b98a2b374bc0cd0e8aa032bccf392c0e..3ebbaa42622ab24edbc7d6f34a89f26f8ee34886 100644 (file)
--- a/gcc/config/rs6000/driver-rs6000.cc
+++ b/gcc/config/rs6000/driver-rs6000.cc
@@ -451,7 +451,6 @@ static const struct asm_name asm_names[] = {
   { "power8",  "-mpwr8" },
   { "power9",  "-mpwr9" },
   { "power10", "-mpwr10" },
-  { "power11", "-mpwr11" },
   { "powerpc", "-mppc" },
   { "rs64",    "-mppc" },
   { "603",     "-m603" },
@@ -480,7 +479,6 @@ static const struct asm_name asm_names[] = {
   { "power8",  "-mpower8" },
   { "power9",  "-mpower9" },
   { "power10", "-mpower10" },
-  { "power11", "-mpower11" },
   { "a2",      "-ma2" },
   { "powerpc", "-mppc" },
   { "powerpc64", "-mppc64" },

diff --git a/gcc/config/rs6000/power10.md b/gcc/config/rs6000/power10.md
index 22851db3318e23d5d8c8a40d9e6f9c5cfbfe19b7..fcc2199ab2911b31672a31669909ae15fd541840 100644 (file)
--- a/gcc/config/rs6000/power10.md
+++ b/gcc/config/rs6000/power10.md
@@ -97,12 +97,12 @@
        (eq_attr "update" "no")
        (eq_attr "size" "!128")
        (eq_attr "prefixed" "no")
-       (eq_attr "cpu" "power10,power11"))
+       (eq_attr "cpu" "power10"))
   "DU_any_power10,LU_power10")
 
 (define_insn_reservation "power10-fused-load" 4
   (and (eq_attr "type" "fused_load_cmpi,fused_addis_load,fused_load_load")
-       (eq_attr "cpu" "power10,power11"))
+       (eq_attr "cpu" "power10"))
   "DU_even_power10,LU_power10")
 
 (define_insn_reservation "power10-prefixed-load" 4
@@ -110,13 +110,13 @@
        (eq_attr "update" "no")
        (eq_attr "size" "!128")
        (eq_attr "prefixed" "yes")
-       (eq_attr "cpu" "power10,power11"))
+       (eq_attr "cpu" "power10"))
   "DU_even_power10,LU_power10")
 
 (define_insn_reservation "power10-load-update" 4
   (and (eq_attr "type" "load")
        (eq_attr "update" "yes")
-       (eq_attr "cpu" "power10,power11"))
+       (eq_attr "cpu" "power10"))
   "DU_even_power10,LU_power10+SXU_power10")
 
 (define_insn_reservation "power10-fpload-double" 4
@@ -124,7 +124,7 @@
        (eq_attr "update" "no")
        (eq_attr "size" "64")
        (eq_attr "prefixed" "no")
-       (eq_attr "cpu" "power10,power11"))
+       (eq_attr "cpu" "power10"))
   "DU_any_power10,LU_power10")
 
 (define_insn_reservation "power10-prefixed-fpload-double" 4
@@ -132,14 +132,14 @@
        (eq_attr "update" "no")
        (eq_attr "size" "64")
        (eq_attr "prefixed" "yes")
-       (eq_attr "cpu" "power10,power11"))
+       (eq_attr "cpu" "power10"))
   "DU_even_power10,LU_power10")
 
 (define_insn_reservation "power10-fpload-update-double" 4
   (and (eq_attr "type" "fpload")
        (eq_attr "update" "yes")
        (eq_attr "size" "64")
-       (eq_attr "cpu" "power10,power11"))
+       (eq_attr "cpu" "power10"))
   "DU_even_power10,LU_power10+SXU_power10")
 
 ; SFmode loads are cracked and have additional 3 cycles over DFmode
@@ -148,27 +148,27 @@
   (and (eq_attr "type" "fpload")
        (eq_attr "update" "no")
        (eq_attr "size" "32")
-       (eq_attr "cpu" "power10,power11"))
+       (eq_attr "cpu" "power10"))
   "DU_even_power10,LU_power10")
 
 (define_insn_reservation "power10-fpload-update-single" 7
   (and (eq_attr "type" "fpload")
        (eq_attr "update" "yes")
        (eq_attr "size" "32")
-       (eq_attr "cpu" "power10,power11"))
+       (eq_attr "cpu" "power10"))
   "DU_even_power10,LU_power10+SXU_power10")
 
 (define_insn_reservation "power10-vecload" 4
   (and (eq_attr "type" "vecload")
        (eq_attr "size" "!256")
-       (eq_attr "cpu" "power10,power11"))
+       (eq_attr "cpu" "power10"))
   "DU_any_power10,LU_power10")
 
 ; lxvp
 (define_insn_reservation "power10-vecload-pair" 4
   (and (eq_attr "type" "vecload")
        (eq_attr "size" "256")
-       (eq_attr "cpu" "power10,power11"))
+       (eq_attr "cpu" "power10"))
   "DU_even_power10,LU_power10+SXU_power10")
 
 ; Store Unit
@@ -178,12 +178,12 @@
        (eq_attr "prefixed" "no")
        (eq_attr "size" "!128")
        (eq_attr "size" "!256")
-       (eq_attr "cpu" "power10,power11"))
+       (eq_attr "cpu" "power10"))
   "DU_any_power10,STU_power10")
 
 (define_insn_reservation "power10-fused-store" 0
   (and (eq_attr "type" "fused_store_store")
-       (eq_attr "cpu" "power10,power11"))
+       (eq_attr "cpu" "power10"))
   "DU_even_power10,STU_power10")
 
 (define_insn_reservation "power10-prefixed-store" 0
@@ -191,52 +191,52 @@
        (eq_attr "prefixed" "yes")
        (eq_attr "size" "!128")
        (eq_attr "size" "!256")
-       (eq_attr "cpu" "power10,power11"))
+       (eq_attr "cpu" "power10"))
   "DU_even_power10,STU_power10")
 
 ; Update forms have 2 cycle latency for updated addr reg
 (define_insn_reservation "power10-store-update" 2
   (and (eq_attr "type" "store,fpstore")
        (eq_attr "update" "yes")
-       (eq_attr "cpu" "power10,power11"))
+       (eq_attr "cpu" "power10"))
   "DU_any_power10,STU_power10")
 
 ; stxvp
 (define_insn_reservation "power10-vecstore-pair" 0
   (and (eq_attr "type" "vecstore")
        (eq_attr "size" "256")
-       (eq_attr "cpu" "power10,power11"))
+       (eq_attr "cpu" "power10"))
   "DU_even_power10,stu0_power10+stu1_power10")
 
 (define_insn_reservation "power10-larx" 4
   (and (eq_attr "type" "load_l")
        (eq_attr "size" "!128")
-       (eq_attr "cpu" "power10,power11"))
+       (eq_attr "cpu" "power10"))
   "DU_any_power10,LU_power10")
 
 ; All load quad forms
 (define_insn_reservation "power10-lq" 4
   (and (eq_attr "type" "load,load_l")
        (eq_attr "size" "128")
-       (eq_attr "cpu" "power10,power11"))
+       (eq_attr "cpu" "power10"))
   "DU_even_power10,LU_power10+SXU_power10")
 
 (define_insn_reservation "power10-stcx" 0
   (and (eq_attr "type" "store_c")
        (eq_attr "size" "!128")
-       (eq_attr "cpu" "power10,power11"))
+       (eq_attr "cpu" "power10"))
   "DU_any_power10,STU_power10")
 
 ; All store quad forms
 (define_insn_reservation "power10-stq" 0
   (and (eq_attr "type" "store,store_c")
        (eq_attr "size" "128")
-       (eq_attr "cpu" "power10,power11"))
+       (eq_attr "cpu" "power10"))
   "DU_even_power10,stu0_power10+stu1_power10")
 
 (define_insn_reservation "power10-sync" 1
   (and (eq_attr "type" "sync,isync")
-       (eq_attr "cpu" "power10,power11"))
+       (eq_attr "cpu" "power10"))
   "DU_even_power10,STU_power10")
 
 
@@ -248,7 +248,7 @@
 (define_insn_reservation "power10-alu" 2
   (and (eq_attr "type" "add,exts,integer,logical,isel")
        (eq_attr "prefixed" "no")
-       (eq_attr "cpu" "power10,power11"))
+       (eq_attr "cpu" "power10"))
   "DU_any_power10,EXU_power10")
 ; 4 cycle CR latency
 (define_bypass 4 "power10-alu"
@@ -256,28 +256,28 @@
 
 (define_insn_reservation "power10-fused_alu" 2
   (and (eq_attr "type" "fused_arith_logical,fused_cmp_isel,fused_carry")
-       (eq_attr "cpu" "power10,power11"))
+       (eq_attr "cpu" "power10"))
   "DU_even_power10,EXU_power10")
 
 ; paddi
 (define_insn_reservation "power10-paddi" 2
   (and (eq_attr "type" "add")
        (eq_attr "prefixed" "yes")
-       (eq_attr "cpu" "power10,power11"))
+       (eq_attr "cpu" "power10"))
   "DU_even_power10,EXU_power10")
 
 ; Rotate/shift (non-record form)
 (define_insn_reservation "power10-rot" 2
   (and (eq_attr "type" "insert,shift")
        (eq_attr "dot" "no")
-       (eq_attr "cpu" "power10,power11"))
+       (eq_attr "cpu" "power10"))
   "DU_any_power10,EXU_power10")
 
 ; Record form rotate/shift
 (define_insn_reservation "power10-rot-compare" 3
   (and (eq_attr "type" "insert,shift")
        (eq_attr "dot" "yes")
-       (eq_attr "cpu" "power10,power11"))
+       (eq_attr "cpu" "power10"))
   "DU_any_power10,EXU_power10")
 ; 5 cycle CR latency
 (define_bypass 5 "power10-rot-compare"
@@ -285,7 +285,7 @@
 
 (define_insn_reservation "power10-alu2" 3
   (and (eq_attr "type" "cntlz,popcnt,trap")
-       (eq_attr "cpu" "power10,power11"))
+       (eq_attr "cpu" "power10"))
   "DU_any_power10,EXU_power10")
 ; 5 cycle CR latency
 (define_bypass 5 "power10-alu2"
@@ -293,24 +293,24 @@
 
 (define_insn_reservation "power10-cmp" 2
   (and (eq_attr "type" "cmp")
-       (eq_attr "cpu" "power10,power11"))
+       (eq_attr "cpu" "power10"))
   "DU_any_power10,EXU_power10")
 
 ; Treat 'two' and 'three' types as 2 or 3 way cracked
 (define_insn_reservation "power10-two" 4
   (and (eq_attr "type" "two")
-       (eq_attr "cpu" "power10,power11"))
+       (eq_attr "cpu" "power10"))
   "DU_even_power10,EXU_power10")
 
 (define_insn_reservation "power10-three" 6
   (and (eq_attr "type" "three")
-       (eq_attr "cpu" "power10,power11"))
+       (eq_attr "cpu" "power10"))
   "DU_all_power10,EXU_power10")
 
 (define_insn_reservation "power10-mul" 5
   (and (eq_attr "type" "mul")
        (eq_attr "dot" "no")
-       (eq_attr "cpu" "power10,power11"))
+       (eq_attr "cpu" "power10"))
   "DU_any_power10,EXU_power10")
 ; 4 cycle MUL->MUL latency
 (define_bypass 4 "power10-mul"
@@ -319,7 +319,7 @@
 (define_insn_reservation "power10-mul-compare" 5
   (and (eq_attr "type" "mul")
        (eq_attr "dot" "yes")
-       (eq_attr "cpu" "power10,power11"))
+       (eq_attr "cpu" "power10"))
   "DU_even_power10,EXU_power10")
 ; 4 cycle MUL->MUL latency
 (define_bypass 4 "power10-mul-compare"
@@ -331,13 +331,13 @@
 (define_insn_reservation "power10-div" 12
   (and (eq_attr "type" "div")
        (eq_attr "dot" "no")
-       (eq_attr "cpu" "power10,power11"))
+       (eq_attr "cpu" "power10"))
   "DU_any_power10,EXU_power10")
 
 (define_insn_reservation "power10-div-compare" 12
   (and (eq_attr "type" "div")
        (eq_attr "dot" "yes")
-       (eq_attr "cpu" "power10,power11"))
+       (eq_attr "cpu" "power10"))
   "DU_even_power10,EXU_power10")
 ; 14 cycle CR latency
 (define_bypass 14 "power10-div-compare"
@@ -345,34 +345,34 @@
 
 (define_insn_reservation "power10-crlogical" 2
   (and (eq_attr "type" "cr_logical")
-       (eq_attr "cpu" "power10,power11"))
+       (eq_attr "cpu" "power10"))
   "DU_any_power10,EXU_power10")
 
 (define_insn_reservation "power10-mfcrf" 2
   (and (eq_attr "type" "mfcrf")
-       (eq_attr "cpu" "power10,power11"))
+       (eq_attr "cpu" "power10"))
   "DU_any_power10,EXU_power10")
 
 (define_insn_reservation "power10-mfcr" 3
   (and (eq_attr "type" "mfcr")
-       (eq_attr "cpu" "power10,power11"))
+       (eq_attr "cpu" "power10"))
   "DU_even_power10,EXU_power10")
 
 ; Should differentiate between 1 cr field and > 1 since target of > 1 cr
 ; is cracked
 (define_insn_reservation "power10-mtcr" 3
   (and (eq_attr "type" "mtcr")
-       (eq_attr "cpu" "power10,power11"))
+       (eq_attr "cpu" "power10"))
   "DU_any_power10,EXU_power10")
 
 (define_insn_reservation "power10-mtjmpr" 3
   (and (eq_attr "type" "mtjmpr")
-       (eq_attr "cpu" "power10,power11"))
+       (eq_attr "cpu" "power10"))
   "DU_any_power10,EXU_power10")
 
 (define_insn_reservation "power10-mfjmpr" 2
   (and (eq_attr "type" "mfjmpr")
-       (eq_attr "cpu" "power10,power11"))
+       (eq_attr "cpu" "power10"))
   "DU_any_power10,EXU_power10")
 
 
@@ -380,126 +380,126 @@
 
 (define_insn_reservation "power10-fpsimple" 3
   (and (eq_attr "type" "fpsimple")
-       (eq_attr "cpu" "power10,power11"))
+       (eq_attr "cpu" "power10"))
   "DU_any_power10,EXU_power10")
 
 (define_insn_reservation "power10-fp" 5
   (and (eq_attr "type" "fp,dmul")
-       (eq_attr "cpu" "power10,power11"))
+       (eq_attr "cpu" "power10"))
   "DU_any_power10,EXU_power10")
 
 (define_insn_reservation "power10-fpcompare" 3
   (and (eq_attr "type" "fpcompare")
-       (eq_attr "cpu" "power10,power11"))
+       (eq_attr "cpu" "power10"))
   "DU_any_power10,EXU_power10")
 
 (define_insn_reservation "power10-sdiv" 22
   (and (eq_attr "type" "sdiv")
-       (eq_attr "cpu" "power10,power11"))
+       (eq_attr "cpu" "power10"))
   "DU_any_power10,EXU_power10")
 
 (define_insn_reservation "power10-ddiv" 27
   (and (eq_attr "type" "ddiv")
-       (eq_attr "cpu" "power10,power11"))
+       (eq_attr "cpu" "power10"))
   "DU_any_power10,EXU_power10")
 
 (define_insn_reservation "power10-sqrt" 26
   (and (eq_attr "type" "ssqrt")
-       (eq_attr "cpu" "power10,power11"))
+       (eq_attr "cpu" "power10"))
   "DU_any_power10,EXU_power10")
 
 (define_insn_reservation "power10-dsqrt" 36
   (and (eq_attr "type" "dsqrt")
-       (eq_attr "cpu" "power10,power11"))
+       (eq_attr "cpu" "power10"))
   "DU_any_power10,EXU_power10")
 
 (define_insn_reservation "power10-vec-2cyc" 2
   (and (eq_attr "type" "vecmove,veclogical,vecexts,veccmpfx")
-       (eq_attr "cpu" "power10,power11"))
+       (eq_attr "cpu" "power10"))
   "DU_any_power10,EXU_power10")
 
 (define_insn_reservation "power10-fused-vec" 2
   (and (eq_attr "type" "fused_vector")
-       (eq_attr "cpu" "power10,power11"))
+       (eq_attr "cpu" "power10"))
   "DU_even_power10,EXU_power10")
 
 (define_insn_reservation "power10-veccmp" 3
   (and (eq_attr "type" "veccmp")
-       (eq_attr "cpu" "power10,power11"))
+       (eq_attr "cpu" "power10"))
   "DU_any_power10,EXU_power10")
 
 (define_insn_reservation "power10-vecsimple" 2
   (and (eq_attr "type" "vecsimple")
-       (eq_attr "cpu" "power10,power11"))
+       (eq_attr "cpu" "power10"))
   "DU_any_power10,EXU_power10")
 
 (define_insn_reservation "power10-vecnormal" 5
   (and (eq_attr "type" "vecfloat,vecdouble")
        (eq_attr "size" "!128")
-       (eq_attr "cpu" "power10,power11"))
+       (eq_attr "cpu" "power10"))
   "DU_any_power10,EXU_power10")
 
 (define_insn_reservation "power10-qp" 12
   (and (eq_attr "type" "vecfloat,vecdouble")
        (eq_attr "size" "128")
-       (eq_attr "cpu" "power10,power11"))
+       (eq_attr "cpu" "power10"))
   "DU_any_power10,EXU_power10")
 
 (define_insn_reservation "power10-vecperm" 3
   (and (eq_attr "type" "vecperm")
        (eq_attr "prefixed" "no")
        (eq_attr "dot" "no")
-       (eq_attr "cpu" "power10,power11"))
+       (eq_attr "cpu" "power10"))
   "DU_any_power10,EXU_power10")
 
 (define_insn_reservation "power10-vecperm-compare" 3
   (and (eq_attr "type" "vecperm")
        (eq_attr "dot" "yes")
-       (eq_attr "cpu" "power10,power11"))
+       (eq_attr "cpu" "power10"))
   "DU_even_power10,EXU_power10")
 
 (define_insn_reservation "power10-prefixed-vecperm" 3
   (and (eq_attr "type" "vecperm")
        (eq_attr "prefixed" "yes")
-       (eq_attr "cpu" "power10,power11"))
+       (eq_attr "cpu" "power10"))
   "DU_even_power10,EXU_power10")
 
 (define_insn_reservation "power10-veccomplex" 6
   (and (eq_attr "type" "veccomplex")
-       (eq_attr "cpu" "power10,power11"))
+       (eq_attr "cpu" "power10"))
   "DU_any_power10,EXU_power10")
 
 (define_insn_reservation "power10-vecfdiv" 24
   (and (eq_attr "type" "vecfdiv")
-       (eq_attr "cpu" "power10,power11"))
+       (eq_attr "cpu" "power10"))
   "DU_any_power10,EXU_power10")
 
 (define_insn_reservation "power10-vecdiv" 27
   (and (eq_attr "type" "vecdiv")
        (eq_attr "size" "!128")
-       (eq_attr "cpu" "power10,power11"))
+       (eq_attr "cpu" "power10"))
   "DU_any_power10,EXU_power10")
 
 (define_insn_reservation "power10-qpdiv" 56
   (and (eq_attr "type" "vecdiv")
        (eq_attr "size" "128")
-       (eq_attr "cpu" "power10,power11"))
+       (eq_attr "cpu" "power10"))
   "DU_any_power10,EXU_power10")
 
 (define_insn_reservation "power10-qpmul" 24
   (and (eq_attr "type" "qmul")
        (eq_attr "size" "128")
-       (eq_attr "cpu" "power10,power11"))
+       (eq_attr "cpu" "power10"))
   "DU_any_power10,EXU_power10")
 
 (define_insn_reservation "power10-mtvsr" 2
   (and (eq_attr "type" "mtvsr")
-       (eq_attr "cpu" "power10,power11"))
+       (eq_attr "cpu" "power10"))
   "DU_any_power10,EXU_power10")
 
 (define_insn_reservation "power10-mfvsr" 2
   (and (eq_attr "type" "mfvsr")
-       (eq_attr "cpu" "power10,power11"))
+       (eq_attr "cpu" "power10"))
   "DU_any_power10,EXU_power10")
 
 
@@ -507,26 +507,26 @@
 ; Branch is 2 cycles, grouped with STU for issue
 (define_insn_reservation "power10-branch" 2
   (and (eq_attr "type" "jmpreg,branch")
-       (eq_attr "cpu" "power10,power11"))
+       (eq_attr "cpu" "power10"))
   "DU_any_power10,STU_power10")
 
 (define_insn_reservation "power10-fused-branch" 3
   (and (eq_attr "type" "fused_mtbc")
-       (eq_attr "cpu" "power10,power11"))
+       (eq_attr "cpu" "power10"))
   "DU_even_power10,STU_power10")
 
 
 ; Crypto
 (define_insn_reservation "power10-crypto" 4
   (and (eq_attr "type" "crypto")
-       (eq_attr "cpu" "power10,power11"))
+       (eq_attr "cpu" "power10"))
   "DU_any_power10,EXU_power10")
 
 
 ; HTM
 (define_insn_reservation "power10-htm" 2
   (and (eq_attr "type" "htmsimple,htm")
-       (eq_attr "cpu" "power10,power11"))
+       (eq_attr "cpu" "power10"))
   "DU_any_power10,EXU_power10")
 
 
@@ -535,26 +535,26 @@
 (define_insn_reservation "power10-dfp" 12
   (and (eq_attr "type" "dfp")
        (eq_attr "size" "!128")
-       (eq_attr "cpu" "power10,power11"))
+       (eq_attr "cpu" "power10"))
   "DU_any_power10,EXU_power10")
 
 (define_insn_reservation "power10-dfpq" 12
   (and (eq_attr "type" "dfp")
        (eq_attr "size" "128")
-       (eq_attr "cpu" "power10,power11"))
+       (eq_attr "cpu" "power10"))
   "DU_even_power10,EXU_power10")
 
 ; MMA
 (define_insn_reservation "power10-mma" 9
   (and (eq_attr "type" "mma")
        (eq_attr "prefixed" "no")
-       (eq_attr "cpu" "power10,power11"))
+       (eq_attr "cpu" "power10"))
   "DU_any_power10,EXU_super_power10")
 
 (define_insn_reservation "power10-prefixed-mma" 9
   (and (eq_attr "type" "mma")
        (eq_attr "prefixed" "yes")
-       (eq_attr "cpu" "power10,power11"))
+       (eq_attr "cpu" "power10"))
   "DU_even_power10,EXU_super_power10")
 ; 4 cycle MMA->MMA latency
 (define_bypass 4 "power10-mma,power10-prefixed-mma"

diff --git a/gcc/config/rs6000/ppc-auxv.h b/gcc/config/rs6000/ppc-auxv.h
index ed269e3b72b38cc7f59b37c13fd32f56183d1f62..364bba427d14bb811d8ce6505eadc09e12d256a1 100644 (file)
--- a/gcc/config/rs6000/ppc-auxv.h
+++ b/gcc/config/rs6000/ppc-auxv.h
@@ -47,8 +47,9 @@
 #define PPC_PLATFORM_PPC476            12
 #define PPC_PLATFORM_POWER8            13
 #define PPC_PLATFORM_POWER9            14
+
+/* This is not yet official.  */
 #define PPC_PLATFORM_POWER10           15
-#define PPC_PLATFORM_POWER11           16
 
 /* AT_HWCAP bits.  These must match the values defined in the Linux kernel.  */
 #define PPC_FEATURE_32              0x80000000

diff --git a/gcc/config/rs6000/rs6000-builtin.cc b/gcc/config/rs6000/rs6000-builtin.cc
index f3ba1eccdbdc4a0acb392d4ee784b3d447edf014..6698274031b903447187b98153fa20342e2d51e4 100644 (file)
--- a/gcc/config/rs6000/rs6000-builtin.cc
+++ b/gcc/config/rs6000/rs6000-builtin.cc
@@ -2493,7 +2493,6 @@ static const struct
   const char *cpu;
   unsigned int cpuid;
 } cpu_is_info[] = {
-  { "power11",    PPC_PLATFORM_POWER11 },
   { "power10",    PPC_PLATFORM_POWER10 },
   { "power9",     PPC_PLATFORM_POWER9 },
   { "power8",     PPC_PLATFORM_POWER8 },

diff --git a/gcc/config/rs6000/rs6000-c.cc b/gcc/config/rs6000/rs6000-c.cc
index ebed8b9554a7d71d37927646d105f0ace4be595c..ce0b14a8d373da9e8191eeffdae9858f453ed2cd 100644 (file)
--- a/gcc/config/rs6000/rs6000-c.cc
+++ b/gcc/config/rs6000/rs6000-c.cc
@@ -447,8 +447,6 @@ rs6000_target_modify_macros (bool define_p, HOST_WIDE_INT flags)
     rs6000_define_or_undefine_macro (define_p, "_ARCH_PWR9");
   if ((flags & OPTION_MASK_POWER10) != 0)
     rs6000_define_or_undefine_macro (define_p, "_ARCH_PWR10");
-  if ((flags & OPTION_MASK_POWER11) != 0)
-    rs6000_define_or_undefine_macro (define_p, "_ARCH_PWR11");
   if ((flags & OPTION_MASK_SOFT_FLOAT) != 0)
     rs6000_define_or_undefine_macro (define_p, "_SOFT_FLOAT");
   if ((flags & OPTION_MASK_RECIP_PRECISION) != 0)

diff --git a/gcc/config/rs6000/rs6000-cpus.def b/gcc/config/rs6000/rs6000-cpus.def
index 3237a5ada3055927115de9ed2e2d36667db8ff55..28249600318fd93ef76a7aedccfad75695265d69 100644 (file)
--- a/gcc/config/rs6000/rs6000-cpus.def
+++ b/gcc/config/rs6000/rs6000-cpus.def
@@ -86,9 +86,6 @@
                                 | OPTION_MASK_POWER10                  \
                                 | OTHER_POWER10_MASKS)
 
-#define ISA_POWER11_MASKS_SERVER (ISA_3_1_MASKS_SERVER                 \
-                                 | OPTION_MASK_POWER11)
-
 /* Flags that need to be turned off if -mno-vsx.  */
 #define OTHER_VSX_VECTOR_MASKS (OPTION_MASK_EFFICIENT_UNALIGNED_VSX    \
                                 | OPTION_MASK_FLOAT128_KEYWORD         \
@@ -128,7 +125,6 @@
                                 | OPTION_MASK_FLOAT128_KEYWORD         \
                                 | OPTION_MASK_FPRND                    \
                                 | OPTION_MASK_POWER10                  \
-                                | OPTION_MASK_POWER11                  \
                                 | OPTION_MASK_P10_FUSION               \
                                 | OPTION_MASK_HTM                      \
                                 | OPTION_MASK_ISEL                     \
@@ -261,4 +257,3 @@ RS6000_CPU ("powerpc64", PROCESSOR_POWERPC64, OPTION_MASK_PPC_GFXOPT
 RS6000_CPU ("powerpc64le", PROCESSOR_POWER8, MASK_POWERPC64
            | ISA_2_7_MASKS_SERVER | OPTION_MASK_HTM)
 RS6000_CPU ("rs64", PROCESSOR_RS64A, OPTION_MASK_PPC_GFXOPT | MASK_POWERPC64)
-RS6000_CPU ("power11", PROCESSOR_POWER11, MASK_POWERPC64 | ISA_POWER11_MASKS_SERVER)

diff --git a/gcc/config/rs6000/rs6000-opts.h b/gcc/config/rs6000/rs6000-opts.h
index 4f5af57ae1a6db12d0ffef15e09e5cea3807af1b..33fd0efc936fe98a71777040cbd538ff1e677206 100644 (file)
--- a/gcc/config/rs6000/rs6000-opts.h
+++ b/gcc/config/rs6000/rs6000-opts.h
@@ -67,8 +67,7 @@ enum processor_type
    PROCESSOR_MPCCORE,
    PROCESSOR_CELL,
    PROCESSOR_PPCA2,
-   PROCESSOR_TITAN,
-   PROCESSOR_POWER11
+   PROCESSOR_TITAN
 };
 
 

diff --git a/gcc/config/rs6000/rs6000-string.cc b/gcc/config/rs6000/rs6000-string.cc
index 9c8a81172e33abf754fdc9d574ddd81575d77bb6..917f5572a6d344bd7a8ce8aa15e5e9ec2ec1709b 100644 (file)
--- a/gcc/config/rs6000/rs6000-string.cc
+++ b/gcc/config/rs6000/rs6000-string.cc
@@ -964,7 +964,6 @@ expand_compare_loop (rtx operands[])
       break;
     case PROCESSOR_POWER9:
     case PROCESSOR_POWER10:
-    case PROCESSOR_POWER11:
       if (bytes_is_const)
        max_bytes = 191;
       else

diff --git a/gcc/config/rs6000/rs6000-tables.opt b/gcc/config/rs6000/rs6000-tables.opt
index 7e5bb6e7658ba05901c533d6624ac9c8025e424e..65f46709716f1b66f058cc1071d5fed010d14a7c 100644 (file)
--- a/gcc/config/rs6000/rs6000-tables.opt
+++ b/gcc/config/rs6000/rs6000-tables.opt
@@ -197,6 +197,3 @@ Enum(rs6000_cpu_opt_value) String(powerpc64le) Value(55)
 EnumValue
 Enum(rs6000_cpu_opt_value) String(rs64) Value(56)
 
-EnumValue
-Enum(rs6000_cpu_opt_value) String(power11) Value(57)
-

diff --git a/gcc/config/rs6000/rs6000.cc b/gcc/config/rs6000/rs6000.cc
index 5380dce7a0733c98110100bc24af6a67e064a2ab..6ba9df4f02e769664f28f1bc263f10d8b675f039 100644 (file)
--- a/gcc/config/rs6000/rs6000.cc
+++ b/gcc/config/rs6000/rs6000.cc
@@ -1087,26 +1087,6 @@ struct processor_costs power10_cost = {
   COSTS_N_INSNS (2),   /* SF->DF convert */
 };
 
-/* Instruction costs on POWER11 processors.  */
-static const
-struct processor_costs power11_cost = {
-  COSTS_N_INSNS (2),   /* mulsi */
-  COSTS_N_INSNS (2),   /* mulsi_const */
-  COSTS_N_INSNS (2),   /* mulsi_const9 */
-  COSTS_N_INSNS (2),   /* muldi */
-  COSTS_N_INSNS (6),   /* divsi */
-  COSTS_N_INSNS (6),   /* divdi */
-  COSTS_N_INSNS (2),   /* fp */
-  COSTS_N_INSNS (2),   /* dmul */
-  COSTS_N_INSNS (11),  /* sdiv */
-  COSTS_N_INSNS (13),  /* ddiv */
-  128,                 /* cache line size */
-  32,                  /* l1 cache */
-  512,                 /* l2 cache */
-  16,                  /* prefetch streams */
-  COSTS_N_INSNS (2),   /* SF->DF convert */
-};
-
 /* Instruction costs on POWER A2 processors.  */
 static const
 struct processor_costs ppca2_cost = {
@@ -4399,8 +4379,7 @@ rs6000_option_override_internal (bool global_init_p)
      generating power10 instructions.  */
   if (!(rs6000_isa_flags_explicit & OPTION_MASK_P10_FUSION))
     {
-      if (rs6000_tune == PROCESSOR_POWER10
-         || rs6000_tune == PROCESSOR_POWER11)
+      if (rs6000_tune == PROCESSOR_POWER10)
        rs6000_isa_flags |= OPTION_MASK_P10_FUSION;
       else
        rs6000_isa_flags &= ~OPTION_MASK_P10_FUSION;
@@ -4429,7 +4408,6 @@ rs6000_option_override_internal (bool global_init_p)
                        && rs6000_tune != PROCESSOR_POWER8
                        && rs6000_tune != PROCESSOR_POWER9
                        && rs6000_tune != PROCESSOR_POWER10
-                       && rs6000_tune != PROCESSOR_POWER11
                        && rs6000_tune != PROCESSOR_PPCA2
                        && rs6000_tune != PROCESSOR_CELL
                        && rs6000_tune != PROCESSOR_PPC476);
@@ -4444,7 +4422,6 @@ rs6000_option_override_internal (bool global_init_p)
                                 || rs6000_tune == PROCESSOR_POWER8
                                 || rs6000_tune == PROCESSOR_POWER9
                                 || rs6000_tune == PROCESSOR_POWER10
-                                || rs6000_tune == PROCESSOR_POWER11
                                 || rs6000_tune == PROCESSOR_PPCE500MC
                                 || rs6000_tune == PROCESSOR_PPCE500MC64
                                 || rs6000_tune == PROCESSOR_PPCE5500
@@ -4747,10 +4724,6 @@ rs6000_option_override_internal (bool global_init_p)
        rs6000_cost = &power10_cost;
        break;
 
-      case PROCESSOR_POWER11:
-       rs6000_cost = &power11_cost;
-       break;
-
       case PROCESSOR_PPCA2:
        rs6000_cost = &ppca2_cost;
        break;
@@ -5907,8 +5880,6 @@ rs6000_machine_from_flags (void)
   /* Disable the flags that should never influence the .machine selection.  */
   flags &= ~(OPTION_MASK_PPC_GFXOPT | OPTION_MASK_PPC_GPOPT | OPTION_MASK_ISEL);
 
-  if ((flags & (ISA_POWER11_MASKS_SERVER & ~ISA_3_1_MASKS_SERVER)) != 0)
-    return "power11";
   if ((flags & (ISA_3_1_MASKS_SERVER & ~ISA_3_0_MASKS_SERVER)) != 0)
     return "power10";
   if ((flags & (ISA_3_0_MASKS_SERVER & ~ISA_2_7_MASKS_SERVER)) != 0)
@@ -10155,7 +10126,6 @@ rs6000_reassociation_width (unsigned int opc ATTRIBUTE_UNUSED,
     case PROCESSOR_POWER8:
     case PROCESSOR_POWER9:
     case PROCESSOR_POWER10:
-    case PROCESSOR_POWER11:
       if (DECIMAL_FLOAT_MODE_P (mode))
        return 1;
       if (VECTOR_MODE_P (mode))
@@ -18237,8 +18207,7 @@ rs6000_adjust_cost (rtx_insn *insn, int dep_type, rtx_insn *dep_insn, int cost,
 
        /* Separate a load from a narrower, dependent store.  */
        if ((rs6000_sched_groups || rs6000_tune == PROCESSOR_POWER9
-            || rs6000_tune == PROCESSOR_POWER10
-            || rs6000_tune == PROCESSOR_POWER11)
+            || rs6000_tune == PROCESSOR_POWER10)
            && GET_CODE (PATTERN (insn)) == SET
            && GET_CODE (PATTERN (dep_insn)) == SET
            && MEM_P (XEXP (PATTERN (insn), 1))
@@ -18277,7 +18246,6 @@ rs6000_adjust_cost (rtx_insn *insn, int dep_type, rtx_insn *dep_insn, int cost,
                 || rs6000_tune == PROCESSOR_POWER8
                 || rs6000_tune == PROCESSOR_POWER9
                 || rs6000_tune == PROCESSOR_POWER10
-                || rs6000_tune == PROCESSOR_POWER11
                  || rs6000_tune == PROCESSOR_CELL)
                 && recog_memoized (dep_insn)
                 && (INSN_CODE (dep_insn) >= 0))
@@ -18852,7 +18820,6 @@ rs6000_issue_rate (void)
   case PROCESSOR_POWER9:
     return 6;
   case PROCESSOR_POWER10:
-  case PROCESSOR_POWER11:
     return 8;
   default:
     return 1;
@@ -19569,9 +19536,7 @@ rs6000_sched_reorder (FILE *dump ATTRIBUTE_UNUSED, int sched_verbose,
     load_store_pendulum = 0;
 
   /* Do Power10 dependent reordering.  */
-  if (last_scheduled_insn
-      && (rs6000_tune == PROCESSOR_POWER10
-         || rs6000_tune == PROCESSOR_POWER11))
+  if (rs6000_tune == PROCESSOR_POWER10 && last_scheduled_insn)
     power10_sched_reorder (ready, n_ready - 1);
 
   return rs6000_issue_rate ();
@@ -19595,9 +19560,8 @@ rs6000_sched_reorder2 (FILE *dump, int sched_verbose, rtx_insn **ready,
       && recog_memoized (last_scheduled_insn) >= 0)
     return power9_sched_reorder2 (ready, *pn_ready - 1);
 
-  if (last_scheduled_insn
-      && (rs6000_tune == PROCESSOR_POWER10
-         || rs6000_tune == PROCESSOR_POWER11))
+  /* Do Power10 dependent reordering.  */
+  if (rs6000_tune == PROCESSOR_POWER10 && last_scheduled_insn)
     return power10_sched_reorder (ready, *pn_ready - 1);
 
   return cached_can_issue_more;
@@ -22814,8 +22778,7 @@ rs6000_register_move_cost (machine_mode mode,
                 allocation a move within the same class might turn
                 out to be a nop.  */
              if (rs6000_tune == PROCESSOR_POWER9
-                 || rs6000_tune == PROCESSOR_POWER10
-                 || rs6000_tune == PROCESSOR_POWER11)
+                 || rs6000_tune == PROCESSOR_POWER10)
                ret = 3 * hard_regno_nregs (FIRST_GPR_REGNO, mode);
              else
                ret = 4 * hard_regno_nregs (FIRST_GPR_REGNO, mode);
@@ -24474,7 +24437,6 @@ static struct rs6000_opt_mask const rs6000_opt_masks[] =
   { "float128-hardware",       OPTION_MASK_FLOAT128_HW,        false, true  },
   { "fprnd",                   OPTION_MASK_FPRND,              false, true  },
   { "power10",                 OPTION_MASK_POWER10,            false, true  },
-  { "power11",                 OPTION_MASK_POWER11,            false, true  },
   { "hard-dfp",                        OPTION_MASK_DFP,                false, true  },
   { "htm",                     OPTION_MASK_HTM,                false, true  },
   { "isel",                    OPTION_MASK_ISEL,               false, true  },

diff --git a/gcc/config/rs6000/rs6000.h b/gcc/config/rs6000/rs6000.h
index 81e2f0a33ef39bdde58b02aab5988a747cc8e1ba..68bc45d65baaa8198c6a5f6984102a13f4860d35 100644 (file)
--- a/gcc/config/rs6000/rs6000.h
+++ b/gcc/config/rs6000/rs6000.h
@@ -107,7 +107,6 @@
 #define ASM_CPU_SPEC \
 "%{mcpu=native: %(asm_cpu_native); \
   mcpu=power10: -mpower10; \
-  mcpu=power11: -mpower11; \
   mcpu=power9: -mpower9; \
   mcpu=power8|mcpu=powerpc64le: -mpower8; \
   mcpu=power7: -mpower7; \

diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md
index ea4add5b2839771ddef0f32a4d8480af61b1f880..bc8bc6ab060bf93cb8b006e258ede3fc90e9557d 100644 (file)
--- a/gcc/config/rs6000/rs6000.md
+++ b/gcc/config/rs6000/rs6000.md
@@ -351,7 +351,7 @@
    ppc403,ppc405,ppc440,ppc476,
    ppc8540,ppc8548,ppce300c2,ppce300c3,ppce500mc,ppce500mc64,ppce5500,ppce6500,
    power4,power5,power6,power7,power8,power9,power10,
-   rs64a,mpccore,cell,ppca2,titan,power11"
+   rs64a,mpccore,cell,ppca2,titan"
   (const (symbol_ref "(enum attr_cpu) rs6000_tune")))
 
 ;; The ISA we implement.

diff --git a/gcc/config/rs6000/rs6000.opt b/gcc/config/rs6000/rs6000.opt
index e7a4e4a2ddd7475bc8e8785991cf75ae038894b1..83197681b661a5551edf30508787a935b876fb9e 100644 (file)
--- a/gcc/config/rs6000/rs6000.opt
+++ b/gcc/config/rs6000/rs6000.opt
@@ -581,9 +581,6 @@ Target Undocumented Var(rs6000_speculate_indirect_jumps) Init(1) Save
 mpower10
 Target Undocumented Mask(POWER10) Var(rs6000_isa_flags) WarnRemoved
 
-mpower11
-Target Undocumented Mask(POWER11) Var(rs6000_isa_flags) Warn(Do not use %<-mpower11>)
-
 mprefixed
 Target Mask(PREFIXED) Var(rs6000_isa_flags)
 Generate (do not generate) prefixed memory instructions.

diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi
index 162e63cd1497ce5f3c6f0a5ac6be6f036e047632..2390d478121cc85e001a635fa13804c36b8b3258 100644 (file)
--- a/gcc/doc/invoke.texi
+++ b/gcc/doc/invoke.texi
@@ -31153,9 +31153,8 @@ Supported values for @var{cpu_type} are @samp{401}, @samp{403},
 @samp{e6500}, @samp{ec603e}, @samp{G3}, @samp{G4}, @samp{G5},
 @samp{titan}, @samp{power3}, @samp{power4}, @samp{power5}, @samp{power5+},
 @samp{power6}, @samp{power6x}, @samp{power7}, @samp{power8},
-@samp{power9}, @samp{power10}, @samp{power11},
-@samp{powerpc}, @samp{powerpc64}, @samp{powerpc64le},
-@samp{rs64}, @samp{future}, and @samp{native}.
+@samp{power9}, @samp{power10}, @samp{powerpc}, @samp{powerpc64},
+@samp{powerpc64le}, @samp{rs64}, and @samp{native}.
 
 @option{-mcpu=powerpc}, @option{-mcpu=powerpc64}, and
 @option{-mcpu=powerpc64le} specify pure 32-bit PowerPC (either

diff --git a/gcc/testsuite/gcc.target/powerpc/power11-1.c b/gcc/testsuite/gcc.target/powerpc/power11-1.c
deleted file mode 100644 (file)
index 6a2e802..0000000
--- a/gcc/testsuite/gcc.target/powerpc/power11-1.c
+++ /dev/null
@@ -1,13 +0,0 @@
-/* { dg-do compile { target powerpc*-*-* } } */
-/* { dg-require-effective-target power11_ok } */
-/* { dg-options "-mdejagnu-cpu=power11 -O2" } */
-
-/* Basic check to see if the compiler supports -mcpu=power11.  */
-
-#ifndef _ARCH_PWR11
-#error "-mcpu=power11 is not supported"
-#endif
-
-void foo (void)
-{
-}

diff --git a/gcc/testsuite/gcc.target/powerpc/power11-2.c b/gcc/testsuite/gcc.target/powerpc/power11-2.c
deleted file mode 100644 (file)
index 7b9904c..0000000
--- a/gcc/testsuite/gcc.target/powerpc/power11-2.c
+++ /dev/null
@@ -1,20 +0,0 @@
-/* { dg-do compile { target powerpc*-*-* } } */
-/* { dg-require-effective-target power11_ok } */
-/* { dg-options "-O2" } */
-
-/* Check if we can set the power11 target via a target attribute.  */
-
-__attribute__((__target__("cpu=power9")))
-void foo_p9 (void)
-{
-}
-
-__attribute__((__target__("cpu=power10")))
-void foo_p10 (void)
-{
-}
-
-__attribute__((__target__("cpu=power11")))
-void foo_p11 (void)
-{
-}

diff --git a/gcc/testsuite/gcc.target/powerpc/power11-3.c b/gcc/testsuite/gcc.target/powerpc/power11-3.c
deleted file mode 100644 (file)
index 9b2d643..0000000
--- a/gcc/testsuite/gcc.target/powerpc/power11-3.c
+++ /dev/null
@@ -1,10 +0,0 @@
-/* { dg-do compile { target powerpc*-*-* } }  */
-/* { dg-require-effective-target power11_ok } */
-/* { dg-options "-mdejagnu-cpu=power8 -O2" }  */
-
-/* Check if we can set the power11 target via a target_clones attribute.  */
-
-__attribute__((__target_clones__("cpu=power11,cpu=power9,default")))
-void foo (void)
-{
-}

diff --git a/gcc/testsuite/lib/target-supports.exp b/gcc/testsuite/lib/target-supports.exp
index f68e440c35ee1587c66421a582f4af23599a13a2..ae33c4f1e3af03495606f4149c044aef5ffbde42 100644 (file)
--- a/gcc/testsuite/lib/target-supports.exp
+++ b/gcc/testsuite/lib/target-supports.exp
@@ -7104,23 +7104,6 @@ proc check_effective_target_power10_ok { } {
     }
 }
 
-# Return 1 if this is a PowerPC target supporting -mcpu=power11.
-
-proc check_effective_target_power11_ok { } {
-    if { ([istarget powerpc*-*-*]) } {
-       return [check_no_compiler_messages power11_ok object {
-           int main (void) {
-               #ifndef _ARCH_PWR11
-               #error "-mcpu=power11 is not supported"
-               #endif
-               return 0;
-           }
-       } "-mcpu=power11"]
-    } else {
-       return 0
-    }
-}
-
 # Return 1 if this is a PowerPC target supporting -mfloat128 via either
 # software emulation on power7/power8 systems or hardware support on power9.