+2013-09-05 James Greenhalgh <james.greenhalgh@arm.com>
+ Sofiane Naci <sofiane.naci@arm.com>
+
+ * config/aarch64/aarch64.md
+ (*movti_aarch64): Rename r_2_f and f_2_r.
+ (*movsf_aarch64): Likewise.
+ (*movdf_aarch64): Likewise.
+ (*movtf_aarch64): Likewise.
+ (aarch64_movdi_<mode>low): Likewise.
+ (aarch64_movdi_<mode>high): Likewise.
+ (aarch64_mov<mode>high_di): Likewise.
+ (aarch64_mov<mode>low_di): Likewise.
+ (aarch64_movtilow_tilow): Likewise.
+ * config/arm/arm.md (attribute "neon_type"): Delete. Move attribute
+ values to config/arm/types.md
+ (attribute "conds"): Update for attribute change.
+ (anddi3_insn): Likewise.
+ (iordi3_insn): Likewise.
+ (xordi3_insn): Likewise.
+ (one_cmpldi2): Likewise.
+ * config/arm/types.md (type): Add Neon types.
+ * config/arm/neon.md (neon_mov<mode>): Remove "neon_type" attribute,
+ use "type" attribute.
+ (movmisalign<mode>_neon_store): Likewise.
+ (movmisalign<mode>_neon_load): Likewise.
+ (vec_set<mode>_internal): Likewise.
+ (vec_setv2di_internal): Likewise.
+ (vec_extract<mode>): Likewise.
+ (vec_extractv2di): Likewise.
+ (add<mode>3_neon): Likewise.
+ (adddi3_neon): Likewise.
+ (sub<mode>3_neon): Likewise.
+ (subdi3_neon): Likewise.
+ (mul<mode>3_neon): Likewise.
+ (mul<mode>3add<mode>_neon): Likewise.
+ (mul<mode>3neg<mode>add<mode>_neon): Likewise.
+ (fma<VCVTF:mode>4)): Likewise.
+ (fma<VCVTF:mode>4_intrinsic): Likewise.
+ (fmsub<VCVTF:mode>4)): Likewise.
+ (fmsub<VCVTF:mode>4_intrinsic): Likewise.
+ (neon_vrint<NEON_VRINT:nvrint_variant><VCVTF:mode>): Likewise.
+ (ior<mode>3): Likewise.
+ (and<mode>3): Likewise.
+ (anddi3_neon): Likewise.
+ (orn<mode>3_neon): Likewise.
+ (orndi3_neon): Likewise.
+ (bic<mode>3_neon): Likewise.
+ (bicdi3_neon): Likewise.
+ (xor<mode>3): Likewise.
+ (one_cmpl<mode>2): Likewise.
+ (abs<mode>2): Likewise.
+ (neg<mode>2): Likewise.
+ (umin<mode>3_neon): Likewise.
+ (umax<mode>3_neon): Likewise.
+ (smin<mode>3_neon): Likewise.
+ (smax<mode>3_neon): Likewise.
+ (vashl<mode>3): Likewise.
+ (vashr<mode>3_imm): Likewise.
+ (vlshr<mode>3_imm): Likewise.
+ (ashl<mode>3_signed): Likewise.
+ (ashl<mode>3_unsigned): Likewise.
+ (neon_load_count): Likewise.
+ (ashldi3_neon_noclobber): Likewise.
+ (signed_shift_di3_neon): Likewise.
+ (unsigned_shift_di3_neon): Likewise.
+ (ashrdi3_neon_imm_noclobber): Likewise.
+ (lshrdi3_neon_imm_noclobber): Likewise.
+ (widen_ssum<mode>3): Likewise.
+ (widen_usum<mode>3): Likewise.
+ (quad_halves_<code>v4si): Likewise.
+ (quad_halves_<code>v4sf): Likewise.
+ (quad_halves_<code>v8hi): Likewise.
+ (quad_halves_<code>v16qi): Likewise.
+ (reduc_splus_v2di): Likewise.
+ (neon_vpadd_internal<mode>): Likewise.
+ (neon_vpsmin<mode>): Likewise.
+ (neon_vpsmax<mode>): Likewise.
+ (neon_vpumin<mode>): Likewise.
+ (neon_vpumax<mode>): Likewise.
+ (ss_add<mode>_neon): Likewise.
+ (us_add<mode>_neon): Likewise.
+ (ss_sub<mode>_neon): Likewise.
+ (us_sub<mode>_neon): Likewise.
+ (neon_vadd<mode>_unspec): Likewise.
+ (neon_vaddl<mode>): Likewise.
+ (neon_vaddw<mode>): Likewise.
+ (neon_vhadd<mode>): Likewise.
+ (neon_vqadd<mode>): Likewise.
+ (neon_vaddhn<mode>): Likewise.
+ (neon_vmul<mode>): Likewise.
+ (neon_vmla<mode>): Likewise.
+ (neon_vmlal<mode>): Likewise.
+ (neon_vmls<mode>): Likewise.
+ (neon_vmlsl<mode>): Likewise.
+ (neon_vqdmulh<mode>): Likewise.
+ (neon_vqdmlal<mode>): Likewise.
+ (neon_vqdmlsl<mode>): Likewise.
+ (neon_vmull<mode>): Likewise.
+ (neon_vqdmull<mode>): Likewise.
+ (neon_vsub<mode>_unspec): Likewise.
+ (neon_vsubl<mode>): Likewise.
+ (neon_vsubw<mode>): Likewise.
+ (neon_vqsub<mode>): Likewise.
+ (neon_vhsub<mode>): Likewise.
+ (neon_vsubhn<mode>): Likewise.
+ (neon_vceq<mode>): Likewise.
+ (neon_vcge<mode>): Likewise.
+ (neon_vcgeu<mode>): Likewise.
+ (neon_vcgt<mode>): Likewise.
+ (neon_vcgtu<mode>): Likewise.
+ (neon_vcle<mode>): Likewise.
+ (neon_vclt<mode>): Likewise.
+ (neon_vcage<mode>): Likewise.
+ (neon_vcagt<mode>): Likewise.
+ (neon_vtst<mode>): Likewise.
+ (neon_vabd<mode>): Likewise.
+ (neon_vabdl<mode>): Likewise.
+ (neon_vaba<mode>): Likewise.
+ (neon_vabal<mode>): Likewise.
+ (neon_vmax<mode>): Likewise.
+ (neon_vmin<mode>): Likewise.
+ (neon_vpaddl<mode>): Likewise.
+ (neon_vpadal<mode>): Likewise.
+ (neon_vpmax<mode>): Likewise.
+ (neon_vpmin<mode>): Likewise.
+ (neon_vrecps<mode>): Likewise.
+ (neon_vrsqrts<mode>): Likewise.
+ (neon_vqabs<mode>): Likewise.
+ (neon_vqneg<mode>): Likewise.
+ (neon_vcls<mode>): Likewise.
+ (clz<mode>2): Likewise.
+ (popcount<mode>2): Likewise.
+ (neon_vrecpe): Likewise.
+ (neon_vrsqrte): Likewise.
+ (neon_vget_lane<mode>_sext_internal): Likewise.
+ (neon_vget_lane<mode>_zext_internal): Likewise.
+ (neon_vdup_n<mode>): Likewise.
+ (neon_vdup_nv2di): Likewise.
+ (neon_vdpu_lane<mode>_internal): Likewise.
+ (neon_vswp<mode>): Likewise.
+ (float<mode><V_cvtto>2): Likewise.
+ (floatuns<mode><V_cvtto>2): Likewise.
+ (fix_trunc<mode><V_cvtto>)2): Likewise
+ (fixuns_trunc<mode><V_cvtto)2): Likewise.
+ (neon_vcvt<mode>): Likewise.
+ (neon_vcvtv4sfv4hf): Likewise.
+ (neon_vcvtv4hfv4sf): Likewise.
+ (neon_vcvt_n<mode>): Likewise.
+ (neon_vmovn<mode>): Likewise.
+ (neon_vqmovn<mode>): Likewise.
+ (neon_vqmovun<mode>): Likewise.
+ (neon_vmovl<mode>): Likewise.
+ (neon_vmul_lane<mode>): Likewise.
+ (neon_vmull_lane<mode>): Likewise.
+ (neon_vqdmull_lane<mode>): Likewise.
+ (neon_vqdmulh_lane<mode>): Likewise.
+ (neon_vmla_lane<mode>): Likewise.
+ (neon_vmlal_lane<mode>): Likewise.
+ (neon_vqdmlal_lane<mode>): Likewise.
+ (neon_vmls_lane<mode>): Likewise.
+ (neon_vmlsl_lane<mode>): Likewise.
+ (neon_vqdmlsl_lane<mode>): Likewise.
+ (neon_vext<mode>): Likewise.
+ (neon_vrev64<mode>): Likewise.
+ (neon_vrev32<mode>): Likewise.
+ (neon_vrev16<mode>): Likewise.
+ (neon_vbsl<mode>_internal): Likewise.
+ (neon_vshl<mode>): Likewise.
+ (neon_vqshl<mode>): Likewise.
+ (neon_vshr_n<mode>): Likewise.
+ (neon_vshrn_n<mode>): Likewise.
+ (neon_vqshrn_n<mode>): Likewise.
+ (neon_vqshrun_n<mode>): Likewise.
+ (neon_vshl_n<mode>): Likewise.
+ (neon_vqshl_n<mode>): Likewise.
+ (neon_vqshlu_n<mode>): Likewise.
+ (neon_vshll_n<mode>): Likewise.
+ (neon_vsra_n<mode>): Likewise.
+ (neon_vsri_n<mode>): Likewise.
+ (neon_vsli_n<mode>): Likewise.
+ (neon_vtbl1v8qi): Likewise.
+ (neon_vtbl2v8qi): Likewise.
+ (neon_vtbl3v8qi): Likewise.
+ (neon_vtbl4v8qi): Likewise.
+ (neon_vtbx1v8qi): Likewise.
+ (neon_vtbx2v8qi): Likewise.
+ (neon_vtbx3v8qi): Likewise.
+ (neon_vtbx4v8qi): Likewise.
+ (neon_vtrn<mode>_internal): Likewise.
+ (neon_vzip<mode>_internal): Likewise.
+ (neon_vuzp<mode>_internal): Likewise.
+ (neon_vld1<mode>): Likewise.
+ (neon_vld1_lane<mode>): Likewise.
+ (neon_vld1_dup<mode>): Likewise.
+ (neon_vld1_dupv2di): Likewise.
+ (neon_vst1<mode>): Likewise.
+ (neon_vst1_lane<mode>): Likewise.
+ (neon_vld2<mode>): Likewise.
+ (neon_vld2_lane<mode>): Likewise.
+ (neon_vld2_dup<mode>): Likewise.
+ (neon_vst2<mode>): Likewise.
+ (neon_vst2_lane<mode>): Likewise.
+ (neon_vld3<mode>): Likewise.
+ (neon_vld3qa<mode>): Likewise.
+ (neon_vld3qb<mode>): Likewise.
+ (neon_vld3_lane<mode>): Likewise.
+ (neon_vld3_dup<mode>): Likewise.
+ (neon_vst3<mode>): Likewise.
+ (neon_vst3qa<mode>): Likewise.
+ (neon_vst3qb<mode>): Likewise.
+ (neon_vst3_lane<mode>): Likewise.
+ (neon_vld4<mode>): Likewise.
+ (neon_vld4qa<mode>): Likewise.
+ (neon_vld4qb<mode>): Likewise.
+ (neon_vld4_lane<mode>): Likewise.
+ (neon_vld4_dup<mode>): Likewise.
+ (neon_vst4<mode>): Likewise.
+ (neon_vst4qa<mode>): Likewise.
+ (neon_vst4qb<mode>): Likewise.
+ (neon_vst4_lane<mode>): Likewise.
+ (neon_vec_unpack<US>_lo_<mode>): Likewise.
+ (neon_vec_unpack<US>_hi_<mode>): Likewise.
+ (neon_vec_<US>mult_lo_<mode>): Likewise.
+ (neon_vec_<US>mult_hi_<mode>): Likewise.
+ (neon_vec_<US>shiftl_<mode>): Likewise.
+ (neon_unpack<US>_<mode>): Likewise.
+ (neon_vec_<US>mult_<mode>): Likewise.
+ (vec_pack_trunc_<mode>): Likewise.
+ (neon_vec_pack_trunk_<mode>): Likewise.
+ (neon_vabd<mode>_2): Likewise.
+ (neon_vabd<mode>_3): Likewise.
+ * config/arm/vfp.md (arm_movsi_vfp): Update for attribute changes.
+ (thumb2_movsi_vfp): Likewise.
+ (movdi_vfp): Likewise.
+ (movdi_vfp_cortexa8): Likewise.
+ (movhf_vfp_neon): Likewise.
+ (movhf_vfp): Likewiwse.
+ (movsf_vfp): Likewiwse.
+ (thumb2_movsf_vfp): Likewiwse.
+ (movdf_vfp): Likewise.
+ (thumb2_movdf_vfp): Likewise.
+ (movsfcc_vfp): Likewise.
+ (thumb2_movsfcc_vfp): Likewise.
+ (movdfcc_vfp): Likewise.
+ (thumb2_movdfcc_vfp): Likewise.
+ * config/arm/arm.c (cortexa7_older_only): Update for attribute change.
+ * config/arm/arm1020e.md (v10_c2v): Update for attribute change.
+ (v10_v2c): Likewise.
+ * config/arm/cortex-a15-neon.md (cortex_a15_neon_int_1): Update for
+ attribute change.
+ (cortex_a15_neon_int_2): Likewise.
+ (cortex_a15_neon_int_3): Likewise.
+ (cortex_a15_neon_int_4): Likewise.
+ (cortex_a15_neon_int_5): Likewise.
+ (cortex_a15_neon_vqneg_vqabs): Likewise.
+ (cortex_a15_neon_vmov): Likewise.
+ (cortex_a15_neon_vaba): Likewise.
+ (cortex_a15_neon_vaba_qqq): Likewise.
+ (cortex_a15_neon_mul_ddd_8_16_qdd_16_8_long_32_16_long): Likewise.
+ (cortex_a15_neon_mul_qqq_8_16_32_ddd_32): Likewise.
+ (cortex_a15_neon_mul_qdd_64_32_long_qqd_16_ddd_32_\
+ scalar_64_32_long_scalar): Likewise.
+ (cortex_a15_neon_mla_ddd_8_16_qdd_16_8_long_32_16_long): Likewise.
+ (cortex_a15_neon_mla_qqq_8_16): Likewise.
+ (cortex_a15_neon_mla_ddd_32_qqd_16_ddd_32_scalar_qdd_64_32_\
+ lotype_qdd_64_32_long): Likewise.
+ (cortex_a15_neon_mla_qqq_32_qqd_32_scalar): Likewise.
+ (cortex_a15_neon_mul_ddd_16_scalar_32_16_long_scalar): Likewise.
+ (cortex_a15_neon_mul_qqd_32_scalar): Likewise.
+ (cortex_a15_neon_mla_ddd_16_scalar_qdd_32_16_long_scalar): Likewise.
+ (cortex_a15_neon_shift_1): Likewise.
+ (cortex_a15_neon_shift_2): Likewise.
+ (cortex_a15_neon_shift_3): Likewise.
+ (cortex_a15_neon_vshl_ddd): Likewise.
+ (cortex_a15_neon_vqshl_vrshl_vqrshl_qqq): Likewise.
+ (cortex_a15_neon_vsra_vrsra): Likewise.
+ (cortex_a15_neon_fp_vadd_ddd_vabs_dd): Likewise.
+ (cortex_a15_neon_fp_vadd_qqq_vabs_qq): Likewise.
+ (cortex_a15_neon_fp_vmul_ddd): Likewise.
+ (cortex_a15_neon_fp_vmul_qqd): Likewise.
+ (cortex_a15_neon_fp_vmla_ddd): Likewise.
+ (cortex_a15_neon_fp_vmla_qqq): Likewise.
+ (cortex_a15_neon_fp_vmla_ddd_scalar): Likewise.
+ (cortex_a15_neon_fp_vmla_qqq_scalar): Likewise.
+ (cortex_a15_neon_fp_vrecps_vrsqrts_ddd): Likewise.
+ (cortex_a15_neon_fp_vrecps_vrsqrts_qqq): Likewise.
+ (cortex_a15_neon_bp_simple): Likewise.
+ (cortex_a15_neon_bp_2cycle): Likewise.
+ (cortex_a15_neon_bp_3cycle): Likewise.
+ (cortex_a15_neon_vld1_1_2_regs): Likewise.
+ (cortex_a15_neon_vld1_3_4_regs): Likewise.
+ (cortex_a15_neon_vld2_2_regs_vld1_vld2_all_lanes): Likewise.
+ (cortex_a15_neon_vld2_4_regs): Likewise.
+ (cortex_a15_neon_vld3_vld4): Likewise.
+ (cortex_a15_neon_vst1_1_2_regs_vst2_2_regs): Likewise.
+ (cortex_a15_neon_vst1_3_4_regs): Likewise.
+ (cortex_a15_neon_vst2_4_regs_vst3_vst4): Likewise.
+ (cortex_a15_neon_vst3_vst4): Likewise.
+ (cortex_a15_neon_vld1_vld2_lane): Likewise.
+ (cortex_a15_neon_vld3_vld4_lane" 10
+ (cortex_a15_neon_vst1_vst2_lane): Likewise.
+ (cortex_a15_neon_vst3_vst4_lane): Likewise.
+ (cortex_a15_neon_vld3_vld4_all_lanes): Likewise.
+ (cortex_a15_neon_ldm_2): Likewise.0
+ (cortex_a15_neon_stm_2): Likewise.
+ (cortex_a15_neon_mcr): Likewise.
+ (cortex_a15_neon_mcr_2_mcrr): Likewise.
+ (cortex_a15_neon_mrc): Likewise.
+ (cortex_a15_neon_mrrc): Likewise.
+ * config/arm/cortex-a15.md (cortex_a15_alu): Update for attribute
+ change.
+ (cortex_a15_alu_shift): Likewise.
+ (cortex_a15_alu_shift_reg): Likewise.
+ (cortex_a15_mult32): Likewise.
+ (cortex_a15_mult64): Likewise.
+ (cortex_a15_block): Likewise.
+ (cortex_a15_branch): Likewise.
+ (cortex_a15_load1): Likewise.
+ (cortex_a15_load3): Likewise.
+ (cortex_a15_store1): Likewise.
+ (cortex_a15_store3): Likewise.
+ (cortex_a15_call): Likewise.
+ * config/arm/cortex-a5.md (cortex_a5_r2f): Update for attribute
+ change.
+ (cortex_a5_f2r): Likewise.
+ * config/arm/cortex-a53.md (cortex_a53_r2f): Update for attribute
+ change.
+ (cortex_a53_f2r): Likewise.
+ * config/arm/cortex-a7.md
+ (cortex_a7_branch): Update for attribute change.
+ (cortex_a7_call): Likewise.
+ (cortex_a7_alu_imm): Likewise.
+ (cortex_a7_alu_reg): Likewise.
+ (cortex_a7_alu_shift): Likewise.
+ (cortex_a7_mul): Likewise.
+ (cortex_a7_load1): Likewise.
+ (cortex_a7_store1): Likewise.
+ (cortex_a7_load2): Likewise.
+ (cortex_a7_store2): Likewise.
+ (cortex_a7_load3): Likewise.
+ (cortex_a7_store3): Likewise.
+ (cortex_a7_load4): Likewise.
+ (cortex_a7_store4): Likewise.
+ (cortex_a7_fpalu): Likewise.
+ (cortex_a7_fconst): Likewise.
+ (cortex_a7_fpmuls): Likewise.
+ (cortex_a7_neon_mul): Likewise.
+ (cortex_a7_fpmacs): Likewise.
+ (cortex_a7_neon_mla: Likewise.
+ (cortex_a7_fpmuld: Likewise.
+ (cortex_a7_fpmacd: Likewise.
+ (cortex_a7_fpfmad: Likewise.
+ (cortex_a7_fdivs: Likewise.
+ (cortex_a7_fdivd: Likewise.
+ (cortex_a7_r2f: Likewise.
+ (cortex_a7_f2r: Likewise.
+ (cortex_a7_f_flags: Likewise.
+ (cortex_a7_f_loads: Likewise.
+ (cortex_a7_f_loadd: Likewise.
+ (cortex_a7_f_stores: Likewise.
+ (cortex_a7_f_stored: Likewise.
+ (cortex_a7_neon): Likewise.
+ * config/arm/cortex-a8-neon.md
+ (cortex_a8_neon_mrc): Update for attribute change.
+ (cortex_a8_neon_mrrc): Likewise.
+ (cortex_a8_neon_int_1): Likewise.
+ (cortex_a8_neon_int_2): Likewise.
+ (cortex_a8_neon_int_3): Likewise.
+ (cortex_a8_neon_int_4): Likewise.
+ (cortex_a8_neon_int_5): Likewise.
+ (cortex_a8_neon_vqneg_vqabs): Likewise.
+ (cortex_a8_neon_vmov): Likewise.
+ (cortex_a8_neon_vaba): Likewise.
+ (cortex_a8_neon_vaba_qqq): Likewise.
+ (cortex_a8_neon_vsma): Likewise.
+ (cortex_a8_neon_mul_ddd_8_16_qdd_16_8_long_32_16_long): Likewise.
+ (cortex_a8_neon_mul_qqq_8_16_32_ddd_32): Likewise.
+ (cortex_a8_neon_mul_qdd_64_32_long_qqd_16_ddd_32_scalar_64_32_long_scalar):
+ Likewise.
+ (cortex_a8_neon_mla_ddd_8_16_qdd_16_8_long_32_16_long): Likewise.
+ (cortex_a8_neon_mla_qqq_8_16): Likewise.
+ (cortex_a8_neon_mla_ddd_32_qqd_16_ddd_32_scalar_qdd_64_32_\
+ long_scalar_qdd_64_32_long): Likewise.
+ (cortex_a8_neon_mla_qqq_32_qqd_32_scalar): Likewise.
+ (cortex_a8_neon_mul_ddd_16_scalar_32_16_long_scalar): Likewise.
+ (cortex_a8_neon_mul_qqd_32_scalar): Likewise.
+ (cortex_a8_neon_mla_ddd_16_scalar_qdd_32_16_long_scalar): Likewise.
+ (cortex_a8_neon_shift_1): Likewise.
+ (cortex_a8_neon_shift_2): Likewise.
+ (cortex_a8_neon_shift_3): Likewise.
+ (cortex_a8_neon_vshl_ddd): Likewise.
+ (cortex_a8_neon_vqshl_vrshl_vqrshl_qqq): Likewise.
+ (cortex_a8_neon_vsra_vrsra): Likewise.
+ (cortex_a8_neon_fp_vadd_ddd_vabs_dd): Likewise.
+ (cortex_a8_neon_fp_vadd_qqq_vabs_qq): Likewise.
+ (cortex_a8_neon_fp_vsum): Likewise.
+ (cortex_a8_neon_fp_vmul_ddd): Likewise.
+ (cortex_a8_neon_fp_vmul_qqd): Likewise.
+ (cortex_a8_neon_fp_vmla_ddd): Likewise.
+ (cortex_a8_neon_fp_vmla_qqq): Likewise.
+ (cortex_a8_neon_fp_vmla_ddd_scalar): Likewise.
+ (cortex_a8_neon_fp_vmla_qqq_scalar): Likewise.
+ (cortex_a8_neon_fp_vrecps_vrsqrts_ddd): Likewise.
+ (cortex_a8_neon_fp_vrecps_vrsqrts_qqq): Likewise.
+ (cortex_a8_neon_bp_simple): Likewise.
+ (cortex_a8_neon_bp_2cycle): Likewise.
+ (cortex_a8_neon_bp_3cycle): Likewise.
+ (cortex_a8_neon_ldr): Likewise.
+ (cortex_a8_neon_str): Likewise.
+ (cortex_a8_neon_vld1_1_2_regs): Likewise.
+ (cortex_a8_neon_vld1_3_4_regs): Likewise.
+ (cortex_a8_neon_vld2_2_regs_vld1_vld2_all_lanes): Likewise.
+ (cortex_a8_neon_vld2_4_regs): Likewise.
+ (cortex_a8_neon_vld3_vld4): Likewise.
+ (cortex_a8_neon_vst1_1_2_regs_vst2_2_regs): Likewise.
+ (cortex_a8_neon_vst1_3_4_regs): Likewise.
+ (cortex_a8_neon_vst2_4_regs_vst3_vst4): Likewise.
+ (cortex_a8_neon_vst3_vst4): Likewise.
+ (cortex_a8_neon_vld1_vld2_lane): Likewise.
+ (cortex_a8_neon_vld3_vld4_lane): Likewise.
+ (cortex_a8_neon_vst1_vst2_lane): Likewise.
+ (cortex_a8_neon_vst3_vst4_lane): Likewise.
+ (cortex_a8_neon_vld3_vld4_all_lanes): Likewise.
+ (cortex_a8_neon_mcr): Likewise.
+ (cortex_a8_neon_mcr_2_mcrr): Likewise.
+ * config/arm/cortex-a8.md (cortex_a8_alu): Update for attribute
+ change.
+ * config/arm/cortex-a9-neon.md (ca9_neon_mrc): Update for attribute
+ change.
+ (ca9_neon_mrrc): Likewise.
+ (cortex_a9_neon_int_1): Likewise.
+ (cortex_a9_neon_int_2): Likewise.
+ (cortex_a9_neon_int_3): Likewise.
+ (cortex_a9_neon_int_4): Likewise.
+ (cortex_a9_neon_int_5): Likewise.
+ (cortex_a9_neon_vqneg_vqabs): Likewise.
+ (cortex_a9_neon_vmov): Likewise.
+ (cortex_a9_neon_vaba): Likewise.
+ (cortex_a9_neon_vaba_qqq): Likewise.
+ (cortex_a9_neon_vsma): Likewise.
+ (cortex_a9_neon_mul_ddd_8_16_qdd_16_8_long_32_16_long): Likewise.
+ (cortex_a9_neon_mul_qqq_8_16_32_ddd_32): Likewise.
+ (cortex_a9_neon_mul_qdd_64_32_long_qqd_16_ddd_32_scalar_64_32_long_scalar):
+ Likewise.
+ (cortex_a9_neon_mla_ddd_8_16_qdd_16_8_long_32_16_long): Likewise.
+ (cortex_a9_neon_mla_qqq_8_16): Likewise.
+ (cortex_a9_neon_mla_ddd_32_qqd_16_ddd_32_scalar_qdd_64_32_\
+ long_scalar_qdd_64_32_long): Likewise.
+ (cortex_a9_neon_mla_qqq_32_qqd_32_scalar): Likewise.
+ (cortex_a9_neon_mul_ddd_16_scalar_32_16_long_scalar): Likewise.
+ (cortex_a9_neon_mul_qqd_32_scalar): Likewise.
+ (cortex_a9_neon_mla_ddd_16_scalar_qdd_32_16_long_scalar): Likewise.
+ (cortex_a9_neon_shift_1): Likewise.
+ (cortex_a9_neon_shift_2): Likewise.
+ (cortex_a9_neon_shift_3): Likewise.
+ (cortex_a9_neon_vshl_ddd): Likewise.
+ (cortex_a9_neon_vqshl_vrshl_vqrshl_qqq): Likewise.
+ (cortex_a9_neon_vsra_vrsra): Likewise.
+ (cortex_a9_neon_fp_vadd_ddd_vabs_dd): Likewise.
+ (cortex_a9_neon_fp_vadd_qqq_vabs_qq): Likewise.
+ (cortex_a9_neon_fp_vsum): Likewise.
+ (cortex_a9_neon_fp_vmul_ddd): Likewise.
+ (cortex_a9_neon_fp_vmul_qqd): Likewise.
+ (cortex_a9_neon_fp_vmla_ddd): Likewise.
+ (cortex_a9_neon_fp_vmla_qqq): Likewise.
+ (cortex_a9_neon_fp_vmla_ddd_scalar): Likewise.
+ (cortex_a9_neon_fp_vmla_qqq_scalar): Likewise.
+ (cortex_a9_neon_fp_vrecps_vrsqrts_ddd): Likewise.
+ (cortex_a9_neon_fp_vrecps_vrsqrts_qqq): Likewise.
+ (cortex_a9_neon_bp_simple): Likewise.
+ (cortex_a9_neon_bp_2cycle): Likewise.
+ (cortex_a9_neon_bp_3cycle): Likewise.
+ (cortex_a9_neon_ldr): Likewise.
+ (cortex_a9_neon_str): Likewise.
+ (cortex_a9_neon_vld1_1_2_regs): Likewise.
+ (cortex_a9_neon_vld1_3_4_regs): Likewise.
+ (cortex_a9_neon_vld2_2_regs_vld1_vld2_all_lanes): Likewise.
+ (cortex_a9_neon_vld2_4_regs): Likewise.
+ (cortex_a9_neon_vld3_vld4): Likewise.
+ (cortex_a9_neon_vst1_1_2_regs_vst2_2_regs): Likewise.
+ (cortex_a9_neon_vst1_3_4_regs): Likewise.
+ (cortex_a9_neon_vst2_4_regs_vst3_vst4): Likewise.
+ (cortex_a9_neon_vst3_vst4): Likewise.
+ (cortex_a9_neon_vld1_vld2_lane): Likewise.
+ (cortex_a9_neon_vld3_vld4_lane): Likewise.
+ (cortex_a9_neon_vst1_vst2_lane): Likewise.
+ (cortex_a9_neon_vst3_vst4_lane): Likewise.
+ (cortex_a9_neon_vld3_vld4_all_lanes): Likewise.
+ (cortex_a9_neon_mcr): Likewise.
+ (cortex_a9_neon_mcr_2_mcrr): Likewise.
+ * config/arm/cortex-a9.md (cortex_a9_dp): Update for attribute change.
+ (cortex_a9_fps): Likewise.
+ * config/arm/cortex-m4-fpu.md (cortex_m4_vmov_2): Update for attribute
+ change.
+ (cortex_m4_fmuls): Likewise.
+ * config/arm/cortex-r4f.md (cortex_r4_mcr): Update for attribute
+ change.
+ (cortex_r4_mrc): Likewise.
+ * config/arm/iterators.md: Update comment referring to neon_type.
+ * config/arm/iwmmxt.md
+ (iwmmxt_arm_movdi): Update for attribute change.
+ (iwmmxt_movsi_insn): Likewise.
+ * config/arm/marvell-pj4.md
+ (pj4_vfp_to_core): Update for attribute change.
+ (pj4_core_to_vfp): Likewise.
+ * config/arm/neon-schedgen.ml (emit_insn_reservations): Update for
+ attribute change.
+ * config/arm/vfp11.md (vfp_fload): Update for attribute change.
+ (vfp_fstore): Likewise.
+ * doc/md.texi: Change references to neon_type to refer to type.
+
2013-09-04 Dodji Seketeli <dodji@redhat.com>
* tree.h (DECL_BUILT_IN): Fix typo in comment.
str\\t%q1, %0"
[(set_attr "v8type" "move2,fmovi2f,fmovf2i,*, \
load2,store2,store2,fpsimd_load,fpsimd_store")
- (set_attr "type" "mov_reg,r_2_f,f_2_r,*, \
+ (set_attr "type" "mov_reg,f_mcr,f_mrc,*, \
load2,store2,store2,f_loadd,f_stored")
(set_attr "simd_type" "*,*,*,simd_move,*,*,*,*,*")
(set_attr "mode" "DI,DI,DI,TI,DI,DI,DI,TI,TI")
[(set_attr "v8type" "fmovi2f,fmovf2i,\
fmov,fconst,fpsimd_load,\
fpsimd_store,fpsimd_load,fpsimd_store,fmov")
- (set_attr "type" "r_2_f,f_2_r,mov_reg,fconsts,\
+ (set_attr "type" "f_mcr,f_mrc,mov_reg,fconsts,\
f_loads,f_stores,f_loads,f_stores,mov_reg")
(set_attr "mode" "SF")]
)
[(set_attr "v8type" "fmovi2f,fmovf2i,\
fmov,fconst,fpsimd_load,\
fpsimd_store,fpsimd_load,fpsimd_store,move")
- (set_attr "type" "r_2_f,f_2_r,mov_reg,fconstd,\
+ (set_attr "type" "f_mcr,f_mrc,mov_reg,fconstd,\
f_loadd,f_stored,f_loadd,f_stored,mov_reg")
(set_attr "mode" "DF")]
)
ldp\\t%0, %H0, %1
stp\\t%1, %H1, %0"
[(set_attr "v8type" "logic,move2,fmovi2f,fmovf2i,fconst,fconst,fpsimd_load,fpsimd_store,fpsimd_load2,fpsimd_store2")
- (set_attr "type" "arlo_reg,mov_reg,r_2_f,f_2_r,fconstd,fconstd,\
+ (set_attr "type" "arlo_reg,mov_reg,f_mcr,f_mrc,fconstd,fconstd,\
f_loadd,f_stored,f_loadd,f_stored")
(set_attr "mode" "DF,DF,DF,DF,DF,DF,TF,TF,DF,DF")
(set_attr "length" "4,8,8,8,4,4,4,4,4,4")
"reload_completed || reload_in_progress"
"fmov\\t%x0, %d1"
[(set_attr "v8type" "fmovf2i")
- (set_attr "type" "f_2_r")
+ (set_attr "type" "f_mrc")
(set_attr "mode" "DI")
(set_attr "length" "4")
])
"reload_completed || reload_in_progress"
"fmov\\t%x0, %1.d[1]"
[(set_attr "v8type" "fmovf2i")
- (set_attr "type" "f_2_r")
+ (set_attr "type" "f_mrc")
(set_attr "mode" "DI")
(set_attr "length" "4")
])
"reload_completed || reload_in_progress"
"fmov\\t%0.d[1], %x1"
[(set_attr "v8type" "fmovi2f")
- (set_attr "type" "r_2_f")
+ (set_attr "type" "f_mcr")
(set_attr "mode" "DI")
(set_attr "length" "4")
])
"reload_completed || reload_in_progress"
"fmov\\t%d0, %x1"
[(set_attr "v8type" "fmovi2f")
- (set_attr "type" "r_2_f")
+ (set_attr "type" "f_mcr")
(set_attr "mode" "DI")
(set_attr "length" "4")
])
"reload_completed || reload_in_progress"
"fmov\\t%d0, %d1"
[(set_attr "v8type" "fmovi2f")
- (set_attr "type" "r_2_f")
+ (set_attr "type" "f_mcr")
(set_attr "mode" "DI")
(set_attr "length" "4")
])
case TYPE_FMACD:
case TYPE_FDIVS:
case TYPE_FDIVD:
- case TYPE_F_2_R:
+ case TYPE_F_MRC:
+ case TYPE_F_MRRC:
case TYPE_F_FLAG:
case TYPE_F_LOADS:
case TYPE_F_STORES:
; initialized by arm_option_override()
(define_attr "ldsched" "no,yes" (const (symbol_ref "arm_ld_sched")))
-;; Classification of NEON instructions for scheduling purposes.
-(define_attr "neon_type"
- "neon_int_1,\
- neon_int_2,\
- neon_int_3,\
- neon_int_4,\
- neon_int_5,\
- neon_vqneg_vqabs,\
- neon_vmov,\
- neon_vaba,\
- neon_vsma,\
- neon_vaba_qqq,\
- neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\
- neon_mul_qqq_8_16_32_ddd_32,\
- neon_mul_qdd_64_32_long_qqd_16_ddd_32_scalar_64_32_long_scalar,\
- neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\
- neon_mla_qqq_8_16,\
- neon_mla_ddd_32_qqd_16_ddd_32_scalar_qdd_64_32_long_scalar_qdd_64_32_long,\
- neon_mla_qqq_32_qqd_32_scalar,\
- neon_mul_ddd_16_scalar_32_16_long_scalar,\
- neon_mul_qqd_32_scalar,\
- neon_mla_ddd_16_scalar_qdd_32_16_long_scalar,\
- neon_shift_1,\
- neon_shift_2,\
- neon_shift_3,\
- neon_vshl_ddd,\
- neon_vqshl_vrshl_vqrshl_qqq,\
- neon_vsra_vrsra,\
- neon_fp_vadd_ddd_vabs_dd,\
- neon_fp_vadd_qqq_vabs_qq,\
- neon_fp_vsum,\
- neon_fp_vmul_ddd,\
- neon_fp_vmul_qqd,\
- neon_fp_vmla_ddd,\
- neon_fp_vmla_qqq,\
- neon_fp_vmla_ddd_scalar,\
- neon_fp_vmla_qqq_scalar,\
- neon_fp_vrecps_vrsqrts_ddd,\
- neon_fp_vrecps_vrsqrts_qqq,\
- neon_bp_simple,\
- neon_bp_2cycle,\
- neon_bp_3cycle,\
- neon_ldr,\
- neon_str,\
- neon_vld1_1_2_regs,\
- neon_vld1_3_4_regs,\
- neon_vld2_2_regs_vld1_vld2_all_lanes,\
- neon_vld2_4_regs,\
- neon_vld3_vld4,\
- neon_vst1_1_2_regs_vst2_2_regs,\
- neon_vst1_3_4_regs,\
- neon_vst2_4_regs_vst3_vst4,\
- neon_vst3_vst4,\
- neon_vld1_vld2_lane,\
- neon_vld3_vld4_lane,\
- neon_vst1_vst2_lane,\
- neon_vst3_vst4_lane,\
- neon_vld3_vld4_all_lanes,\
- neon_mcr,\
- neon_mcr_2_mcrr,\
- neon_mrc,\
- neon_mrrc,\
- neon_ldm_2,\
- neon_stm_2,\
- none"
- (const_string "none"))
-
; condition codes: this one is used by final_prescan_insn to speed up
; conditionalizing instructions. It saves having to scan the rtl to see if
; it uses or alters the condition codes.
(ior (eq_attr "is_thumb1" "yes")
(eq_attr "type" "call"))
(const_string "clob")
- (if_then_else (eq_attr "neon_type" "none")
- (const_string "nocond")
- (const_string "unconditional"))))
+ (if_then_else (eq_attr "type"
+ "!neon_int_1, neon_int_2, neon_int_3, neon_int_4, neon_int_5,\
+ neon_vqneg_vqabs, neon_vmov, neon_vaba, neon_vsma, neon_vaba_qqq,\
+ neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\
+ neon_mul_qqq_8_16_32_ddd_32,\
+ neon_mul_qdd_64_32_long_qqd_16_ddd_32_scalar_64_32_long_scalar,\
+ neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\
+ neon_mla_qqq_8_16,\
+ neon_mla_ddd_32_qqd_16_ddd_32_scalar_qdd_64_32_long_scalar_qdd_64_32_long,\
+ neon_mla_qqq_32_qqd_32_scalar,\
+ neon_mul_ddd_16_scalar_32_16_long_scalar, neon_mul_qqd_32_scalar,\
+ neon_mla_ddd_16_scalar_qdd_32_16_long_scalar, neon_shift_1,\
+ neon_shift_2, neon_shift_3, neon_vshl_ddd,\
+ neon_vqshl_vrshl_vqrshl_qqq, neon_vsra_vrsra,\
+ neon_fp_vadd_ddd_vabs_dd, neon_fp_vadd_qqq_vabs_qq, neon_fp_vsum,\
+ neon_fp_vmul_ddd, neon_fp_vmul_qqd, neon_fp_vmla_ddd,\
+ neon_fp_vmla_qqq, neon_fp_vmla_ddd_scalar, neon_fp_vmla_qqq_scalar,\
+ neon_fp_vrecps_vrsqrts_ddd, neon_fp_vrecps_vrsqrts_qqq,\
+ neon_bp_simple, neon_bp_2cycle, neon_bp_3cycle, neon_ldr, neon_str,\
+ neon_vld1_1_2_regs, neon_vld1_3_4_regs,\
+ neon_vld2_2_regs_vld1_vld2_all_lanes, neon_vld2_4_regs,\
+ neon_vld3_vld4, neon_vst1_1_2_regs_vst2_2_regs, neon_vst1_3_4_regs,\
+ neon_vst2_4_regs_vst3_vst4, neon_vst3_vst4, neon_vld1_vld2_lane,\
+ neon_vld3_vld4_lane, neon_vst1_vst2_lane, neon_vst3_vst4_lane,\
+ neon_vld3_vld4_all_lanes, neon_mcr, neon_mcr_2_mcrr, neon_mrc,\
+ neon_mrrc, neon_ldm_2, neon_stm_2")
+ (const_string "nocond")
+ (const_string "unconditional"))))
; Predicable means that the insn can be conditionally executed based on
; an automatically added predicate (additional patterns are generated by
gen_highpart_mode (SImode, DImode, operands[2]));
}"
- [(set_attr "neon_type" "neon_int_1,neon_int_1,*,*,*,*,neon_int_1,neon_int_1")
+ [(set_attr "type" "neon_int_1,neon_int_1,*,*,*,*,neon_int_1,neon_int_1")
(set_attr "arch" "neon_for_64bits,neon_for_64bits,*,*,*,*,
avoid_neon_for_64bits,avoid_neon_for_64bits")
(set_attr "length" "*,*,8,8,8,8,*,*")
gen_highpart_mode (SImode, DImode, operands[2]));
}"
- [(set_attr "neon_type" "neon_int_1,neon_int_1,*,*,*,*,neon_int_1,neon_int_1")
+ [(set_attr "type" "neon_int_1,neon_int_1,*,*,*,*,neon_int_1,neon_int_1")
(set_attr "length" "*,*,8,8,8,8,*,*")
(set_attr "arch" "neon_for_64bits,neon_for_64bits,*,*,*,*,avoid_neon_for_64bits,avoid_neon_for_64bits")]
)
}"
[(set_attr "length" "*,8,8,8,8,*")
- (set_attr "neon_type" "neon_int_1,*,*,*,*,neon_int_1")
+ (set_attr "type" "neon_int_1,*,*,*,*,neon_int_1")
(set_attr "arch" "neon_for_64bits,*,*,*,*,avoid_neon_for_64bits")]
)
}"
[(set_attr "length" "*,8,8,*")
(set_attr "predicable" "no,yes,yes,no")
- (set_attr "neon_type" "neon_int_1,*,*,neon_int_1")
+ (set_attr "type" "neon_int_1,*,*,neon_int_1")
(set_attr "arch" "neon_for_64bits,*,*,avoid_neon_for_64bits")]
)
(define_insn_reservation "v10_c2v" 4
(and (eq_attr "vfp10" "yes")
- (eq_attr "type" "r_2_f"))
+ (eq_attr "type" "f_mcr,f_mcrr"))
"1020a_e+1020l_e+v10_ls1,v10_ls2")
(define_insn_reservation "v10_fstores" 1
(define_insn_reservation "v10_v2c" 1
(and (eq_attr "vfp10" "yes")
- (eq_attr "type" "f_2_r"))
+ (eq_attr "type" "f_mrc,f_mrrc"))
"1020a_e+1020l_e,1020l_m,1020l_w")
(define_insn_reservation "v10_to_cpsr" 2
(define_insn_reservation "cortex_a15_neon_int_1" 5
(and (eq_attr "tune" "cortexa15")
- (eq_attr "neon_type" "neon_int_1"))
+ (eq_attr "type" "neon_int_1"))
"ca15_issue1,ca15_cx_ialu")
(define_insn_reservation "cortex_a15_neon_int_2" 5
(and (eq_attr "tune" "cortexa15")
- (eq_attr "neon_type" "neon_int_2"))
+ (eq_attr "type" "neon_int_2"))
"ca15_issue1,ca15_cx_ialu")
(define_insn_reservation "cortex_a15_neon_int_3" 5
(and (eq_attr "tune" "cortexa15")
- (eq_attr "neon_type" "neon_int_3"))
+ (eq_attr "type" "neon_int_3"))
"ca15_issue1,ca15_cx_ialu")
(define_insn_reservation "cortex_a15_neon_int_4" 5
(and (eq_attr "tune" "cortexa15")
- (eq_attr "neon_type" "neon_int_4"))
+ (eq_attr "type" "neon_int_4"))
"ca15_issue1,ca15_cx_ialu")
(define_insn_reservation "cortex_a15_neon_int_5" 5
(and (eq_attr "tune" "cortexa15")
- (eq_attr "neon_type" "neon_int_5"))
+ (eq_attr "type" "neon_int_5"))
"ca15_issue1,ca15_cx_ialu")
(define_insn_reservation "cortex_a15_neon_vqneg_vqabs" 5
(and (eq_attr "tune" "cortexa15")
- (eq_attr "neon_type" "neon_vqneg_vqabs"))
+ (eq_attr "type" "neon_vqneg_vqabs"))
"ca15_issue1,ca15_cx_ialu")
(define_insn_reservation "cortex_a15_neon_vmov" 5
(and (eq_attr "tune" "cortexa15")
- (eq_attr "neon_type" "neon_vmov"))
+ (eq_attr "type" "neon_vmov"))
"ca15_issue1,ca15_cx_ialu")
(define_insn_reservation "cortex_a15_neon_vaba" 7
(and (eq_attr "tune" "cortexa15")
- (eq_attr "neon_type" "neon_vaba"))
+ (eq_attr "type" "neon_vaba"))
"ca15_issue1,ca15_cx_ialu_with_acc")
(define_insn_reservation "cortex_a15_neon_vaba_qqq" 8
(and (eq_attr "tune" "cortexa15")
- (eq_attr "neon_type" "neon_vaba_qqq"))
+ (eq_attr "type" "neon_vaba_qqq"))
"ca15_issue2,ca15_cx_ialu_with_acc*2")
(define_insn_reservation
"cortex_a15_neon_mul_ddd_8_16_qdd_16_8_long_32_16_long" 6
(and (eq_attr "tune" "cortexa15")
- (eq_attr "neon_type" "neon_mul_ddd_8_16_qdd_16_8_long_32_16_long"))
+ (eq_attr "type" "neon_mul_ddd_8_16_qdd_16_8_long_32_16_long"))
"ca15_issue1,ca15_cx_imac")
(define_insn_reservation "cortex_a15_neon_mul_qqq_8_16_32_ddd_32" 7
(and (eq_attr "tune" "cortexa15")
- (eq_attr "neon_type" "neon_mul_qqq_8_16_32_ddd_32"))
+ (eq_attr "type" "neon_mul_qqq_8_16_32_ddd_32"))
"ca15_issue1,ca15_cx_imac*2")
(define_insn_reservation
"cortex_a15_neon_mul_qdd_64_32_long_qqd_16_ddd_32_scalar_64_32_long_scalar" 7
(and (eq_attr "tune" "cortexa15")
- (eq_attr "neon_type"
+ (eq_attr "type"
"neon_mul_qdd_64_32_long_qqd_16_ddd_32_scalar_64_32_long_scalar"))
"ca15_issue1,ca15_cx_imac*2")
(define_insn_reservation
"cortex_a15_neon_mla_ddd_8_16_qdd_16_8_long_32_16_long" 6
(and (eq_attr "tune" "cortexa15")
- (eq_attr "neon_type"
+ (eq_attr "type"
"neon_mla_ddd_8_16_qdd_16_8_long_32_16_long"))
"ca15_issue1,ca15_cx_imac")
(define_insn_reservation
"cortex_a15_neon_mla_qqq_8_16" 7
(and (eq_attr "tune" "cortexa15")
- (eq_attr "neon_type"
+ (eq_attr "type"
"neon_mla_qqq_8_16"))
"ca15_issue1,ca15_cx_imac*2")
(define_insn_reservation
"cortex_a15_neon_mla_ddd_32_qqd_16_ddd_32_scalar_\
- qdd_64_32_long_scalar_qdd_64_32_long" 7
+ qdd_64_32_lotype_qdd_64_32_long" 7
(and (eq_attr "tune" "cortexa15")
- (eq_attr "neon_type"
- "neon_mla_ddd_32_qqd_16_ddd_32_scalar_qdd_64_32_long_scalar_qdd_64_32_long"))
+ (eq_attr "type" "neon_mla_ddd_32_qqd_16_ddd_32_scalar_qdd_64_32_long_scalar_qdd_64_32_long"))
"ca15_issue1,ca15_cx_imac")
(define_insn_reservation
"cortex_a15_neon_mla_qqq_32_qqd_32_scalar" 7
(and (eq_attr "tune" "cortexa15")
- (eq_attr "neon_type"
- "neon_mla_qqq_32_qqd_32_scalar"))
+ (eq_attr "type" "neon_mla_qqq_32_qqd_32_scalar"))
"ca15_issue1,ca15_cx_imac*2")
(define_insn_reservation
"cortex_a15_neon_mul_ddd_16_scalar_32_16_long_scalar" 6
(and (eq_attr "tune" "cortexa15")
- (eq_attr "neon_type"
- "neon_mul_ddd_16_scalar_32_16_long_scalar"))
+ (eq_attr "type" "neon_mul_ddd_16_scalar_32_16_long_scalar"))
"ca15_issue1,ca15_cx_imac")
(define_insn_reservation
"cortex_a15_neon_mul_qqd_32_scalar" 7
(and (eq_attr "tune" "cortexa15")
- (eq_attr "neon_type"
- "neon_mul_qqd_32_scalar"))
+ (eq_attr "type" "neon_mul_qqd_32_scalar"))
"ca15_issue1,ca15_cx_imac*2")
(define_insn_reservation
"cortex_a15_neon_mla_ddd_16_scalar_qdd_32_16_long_scalar" 6
(and (eq_attr "tune" "cortexa15")
- (eq_attr "neon_type"
- "neon_mla_ddd_16_scalar_qdd_32_16_long_scalar"))
+ (eq_attr "type" "neon_mla_ddd_16_scalar_qdd_32_16_long_scalar"))
"ca15_issue1,ca15_cx_imac")
(define_insn_reservation
"cortex_a15_neon_shift_1" 5
(and (eq_attr "tune" "cortexa15")
- (eq_attr "neon_type"
- "neon_shift_1"))
+ (eq_attr "type" "neon_shift_1"))
"ca15_issue1,ca15_cx_ik+ca15_cx_ishf")
(define_insn_reservation
"cortex_a15_neon_shift_2" 5
(and (eq_attr "tune" "cortexa15")
- (eq_attr "neon_type"
- "neon_shift_2"))
+ (eq_attr "type" "neon_shift_2"))
"ca15_issue1,ca15_cx_ik+ca15_cx_ishf")
(define_insn_reservation
"cortex_a15_neon_shift_3" 6
(and (eq_attr "tune" "cortexa15")
- (eq_attr "neon_type"
- "neon_shift_3"))
+ (eq_attr "type" "neon_shift_3"))
"ca15_issue2,(ca15_cx_ik+ca15_cx_ishf)*2")
(define_insn_reservation
"cortex_a15_neon_vshl_ddd" 5
(and (eq_attr "tune" "cortexa15")
- (eq_attr "neon_type"
- "neon_vshl_ddd"))
+ (eq_attr "type" "neon_vshl_ddd"))
"ca15_issue1,ca15_cx_ik+ca15_cx_ishf")
(define_insn_reservation
"cortex_a15_neon_vqshl_vrshl_vqrshl_qqq" 6
(and (eq_attr "tune" "cortexa15")
- (eq_attr "neon_type"
- "neon_vqshl_vrshl_vqrshl_qqq"))
+ (eq_attr "type" "neon_vqshl_vrshl_vqrshl_qqq"))
"ca15_issue2,(ca15_cx_ik+ca15_cx_ishf)*2")
(define_insn_reservation
"cortex_a15_neon_vsra_vrsra" 7
(and (eq_attr "tune" "cortexa15")
- (eq_attr "neon_type"
- "neon_vsra_vrsra"))
+ (eq_attr "type" "neon_vsra_vrsra"))
"ca15_issue1,ca15_cx_ishf_with_acc")
(define_insn_reservation
"cortex_a15_neon_fp_vadd_ddd_vabs_dd" 6
(and (eq_attr "tune" "cortexa15")
- (eq_attr "neon_type"
- "neon_fp_vadd_ddd_vabs_dd"))
+ (eq_attr "type" "neon_fp_vadd_ddd_vabs_dd"))
"ca15_issue1,ca15_cx_falu")
(define_insn_reservation
"cortex_a15_neon_fp_vadd_qqq_vabs_qq" 7
(and (eq_attr "tune" "cortexa15")
- (eq_attr "neon_type"
- "neon_fp_vadd_qqq_vabs_qq"))
+ (eq_attr "type" "neon_fp_vadd_qqq_vabs_qq"))
"ca15_issue2,ca15_cx_falu_2")
(define_insn_reservation
"cortex_a15_neon_fp_vmul_ddd" 5
(and (eq_attr "tune" "cortexa15")
- (eq_attr "neon_type"
- "neon_fp_vmul_ddd"))
+ (eq_attr "type" "neon_fp_vmul_ddd"))
"ca15_issue1,ca15_cx_fmul")
(define_insn_reservation
"cortex_a15_neon_fp_vmul_qqd" 6
(and (eq_attr "tune" "cortexa15")
- (eq_attr "neon_type"
- "neon_fp_vmul_qqd"))
+ (eq_attr "type" "neon_fp_vmul_qqd"))
"ca15_issue2,ca15_cx_fmul_2")
(define_insn_reservation
"cortex_a15_neon_fp_vmla_ddd" 9
(and (eq_attr "tune" "cortexa15")
- (eq_attr "neon_type"
- "neon_fp_vmla_ddd"))
+ (eq_attr "type" "neon_fp_vmla_ddd"))
"ca15_issue1,ca15_cx_fmac")
(define_insn_reservation
"cortex_a15_neon_fp_vmla_qqq" 11
(and (eq_attr "tune" "cortexa15")
- (eq_attr "neon_type"
- "neon_fp_vmla_qqq"))
+ (eq_attr "type" "neon_fp_vmla_qqq"))
"ca15_issue2,ca15_cx_fmac_2")
(define_insn_reservation
"cortex_a15_neon_fp_vmla_ddd_scalar" 9
(and (eq_attr "tune" "cortexa15")
- (eq_attr "neon_type"
- "neon_fp_vmla_ddd_scalar"))
+ (eq_attr "type" "neon_fp_vmla_ddd_scalar"))
"ca15_issue1,ca15_cx_fmac")
(define_insn_reservation
"cortex_a15_neon_fp_vmla_qqq_scalar" 11
(and (eq_attr "tune" "cortexa15")
- (eq_attr "neon_type"
- "neon_fp_vmla_qqq_scalar"))
+ (eq_attr "type" "neon_fp_vmla_qqq_scalar"))
"ca15_issue2,ca15_cx_fmac_2")
(define_insn_reservation
"cortex_a15_neon_fp_vrecps_vrsqrts_ddd" 9
(and (eq_attr "tune" "cortexa15")
- (eq_attr "neon_type"
- "neon_fp_vrecps_vrsqrts_ddd"))
+ (eq_attr "type" "neon_fp_vrecps_vrsqrts_ddd"))
"ca15_issue1,ca15_cx_fmac")
(define_insn_reservation
"cortex_a15_neon_fp_vrecps_vrsqrts_qqq" 11
(and (eq_attr "tune" "cortexa15")
- (eq_attr "neon_type"
- "neon_fp_vrecps_vrsqrts_qqq"))
+ (eq_attr "type" "neon_fp_vrecps_vrsqrts_qqq"))
"ca15_issue2,ca15_cx_fmac_2")
(define_insn_reservation
"cortex_a15_neon_bp_simple" 4
(and (eq_attr "tune" "cortexa15")
- (eq_attr "neon_type"
- "neon_bp_simple"))
+ (eq_attr "type" "neon_bp_simple"))
"ca15_issue3,ca15_ls+ca15_cx_perm_2,ca15_cx_perm")
(define_insn_reservation
"cortex_a15_neon_bp_2cycle" 4
(and (eq_attr "tune" "cortexa15")
- (eq_attr "neon_type"
- "neon_bp_2cycle"))
+ (eq_attr "type" "neon_bp_2cycle"))
"ca15_issue1,ca15_cx_perm")
(define_insn_reservation
"cortex_a15_neon_bp_3cycle" 7
(and (eq_attr "tune" "cortexa15")
- (eq_attr "neon_type"
- "neon_bp_3cycle"))
+ (eq_attr "type" "neon_bp_3cycle"))
"ca15_issue3,ca15_cx_ialu+ca15_cx_perm_2,ca15_cx_perm")
(define_insn_reservation
"cortex_a15_neon_vld1_1_2_regs" 7
(and (eq_attr "tune" "cortexa15")
- (eq_attr "neon_type"
- "neon_vld1_1_2_regs"))
+ (eq_attr "type" "neon_vld1_1_2_regs"))
"ca15_issue2,ca15_ls,ca15_ldr")
(define_insn_reservation
"cortex_a15_neon_vld1_3_4_regs" 8
(and (eq_attr "tune" "cortexa15")
- (eq_attr "neon_type"
- "neon_vld1_3_4_regs"))
+ (eq_attr "type" "neon_vld1_3_4_regs"))
"ca15_issue3,ca15_ls1+ca15_ls2,ca15_ldr,ca15_ldr")
(define_insn_reservation
"cortex_a15_neon_vld2_2_regs_vld1_vld2_all_lanes" 9
(and (eq_attr "tune" "cortexa15")
- (eq_attr "neon_type"
- "neon_vld2_2_regs_vld1_vld2_all_lanes"))
+ (eq_attr "type" "neon_vld2_2_regs_vld1_vld2_all_lanes"))
"ca15_issue3,ca15_ls,ca15_ldr")
(define_insn_reservation
"cortex_a15_neon_vld2_4_regs" 12
(and (eq_attr "tune" "cortexa15")
- (eq_attr "neon_type"
- "neon_vld2_4_regs"))
+ (eq_attr "type" "neon_vld2_4_regs"))
"ca15_issue3,ca15_issue3+ca15_ls1+ca15_ls2,ca15_ldr*2")
(define_insn_reservation
"cortex_a15_neon_vld3_vld4" 12
(and (eq_attr "tune" "cortexa15")
- (eq_attr "neon_type"
- "neon_vld3_vld4"))
+ (eq_attr "type" "neon_vld3_vld4"))
"ca15_issue3,ca15_issue3+ca15_ls1+ca15_ls2,ca15_ldr*2")
(define_insn_reservation
"cortex_a15_neon_vst1_1_2_regs_vst2_2_regs" 0
(and (eq_attr "tune" "cortexa15")
- (eq_attr "neon_type"
- "neon_vst1_1_2_regs_vst2_2_regs"))
+ (eq_attr "type" "neon_vst1_1_2_regs_vst2_2_regs"))
"ca15_issue3,ca15_issue3+ca15_cx_perm+ca15_ls1+ca15_ls2,ca15_str*2")
(define_insn_reservation
"cortex_a15_neon_vst1_3_4_regs" 0
(and (eq_attr "tune" "cortexa15")
- (eq_attr "neon_type"
- "neon_vst1_3_4_regs"))
+ (eq_attr "type" "neon_vst1_3_4_regs"))
"ca15_issue3,ca15_issue3+ca15_ls1+ca15_ls2,ca15_str*3")
(define_insn_reservation
"cortex_a15_neon_vst2_4_regs_vst3_vst4" 0
(and (eq_attr "tune" "cortexa15")
- (eq_attr "neon_type"
- "neon_vst2_4_regs_vst3_vst4"))
+ (eq_attr "type" "neon_vst2_4_regs_vst3_vst4"))
"ca15_issue3,ca15_issue3+ca15_cx_perm_2+ca15_ls1+ca15_ls2,\
ca15_issue3+ca15_str,ca15_str*3")
(define_insn_reservation
"cortex_a15_neon_vst3_vst4" 0
(and (eq_attr "tune" "cortexa15")
- (eq_attr "neon_type"
- "neon_vst3_vst4"))
+ (eq_attr "type" "neon_vst3_vst4"))
"ca15_issue3,ca15_issue3+ca15_cx_perm_2+ca15_ls1+ca15_ls2,ca15_str*4")
(define_insn_reservation
"cortex_a15_neon_vld1_vld2_lane" 9
(and (eq_attr "tune" "cortexa15")
- (eq_attr "neon_type"
- "neon_vld1_vld2_lane"))
+ (eq_attr "type" "neon_vld1_vld2_lane"))
"ca15_issue3,ca15_ls,ca15_ldr")
(define_insn_reservation
"cortex_a15_neon_vld3_vld4_lane" 10
(and (eq_attr "tune" "cortexa15")
- (eq_attr "neon_type"
- "neon_vld3_vld4_lane"))
+ (eq_attr "type" "neon_vld3_vld4_lane"))
"ca15_issue3,ca15_issue3+ca15_ls,ca15_issue3+ca15_ldr")
(define_insn_reservation
"cortex_a15_neon_vst1_vst2_lane" 0
(and (eq_attr "tune" "cortexa15")
- (eq_attr "neon_type"
- "neon_vst1_vst2_lane"))
+ (eq_attr "type" "neon_vst1_vst2_lane"))
"ca15_issue3,ca15_cx_perm+ca15_ls,ca15_str")
(define_insn_reservation
"cortex_a15_neon_vst3_vst4_lane" 0
(and (eq_attr "tune" "cortexa15")
- (eq_attr "neon_type"
- "neon_vst3_vst4_lane"))
+ (eq_attr "type" "neon_vst3_vst4_lane"))
"ca15_issue3,ca15_issue3+ca15_cx_perm+ca15_ls1+ca15_ls2,ca15_str*2")
(define_insn_reservation
"cortex_a15_neon_vld3_vld4_all_lanes" 11
(and (eq_attr "tune" "cortexa15")
- (eq_attr "neon_type"
- "neon_vld3_vld4_all_lanes"))
+ (eq_attr "type" "neon_vld3_vld4_all_lanes"))
"ca15_issue3,ca15_issue3+ca15_ls,ca15_ldr")
(define_insn_reservation
"cortex_a15_neon_ldm_2" 20
(and (eq_attr "tune" "cortexa15")
- (eq_attr "neon_type"
- "neon_ldm_2"))
+ (eq_attr "type" "neon_ldm_2"))
"ca15_issue3*6")
(define_insn_reservation
"cortex_a15_neon_stm_2" 0
(and (eq_attr "tune" "cortexa15")
- (eq_attr "neon_type"
- "neon_stm_2"))
+ (eq_attr "type" "neon_stm_2"))
"ca15_issue3*6")
(define_insn_reservation
"cortex_a15_neon_mcr" 6
(and (eq_attr "tune" "cortexa15")
- (eq_attr "neon_type"
- "neon_mcr"))
+ (eq_attr "type" "neon_mcr"))
"ca15_issue2,ca15_ls,ca15_cx_perm")
(define_insn_reservation
"cortex_a15_neon_mcr_2_mcrr" 6
(and (eq_attr "tune" "cortexa15")
- (eq_attr "neon_type"
- "neon_mcr_2_mcrr"))
+ (eq_attr "type" "neon_mcr_2_mcrr"))
"ca15_issue2,ca15_ls1+ca15_ls2")
(define_insn_reservation
"cortex_a15_neon_mrc" 5
(and (eq_attr "tune" "cortexa15")
- (eq_attr "neon_type"
- "neon_mrc"))
+ (eq_attr "type" "neon_mrc"))
"ca15_issue1,ca15_ls")
(define_insn_reservation
"cortex_a15_neon_mrrc" 6
(and (eq_attr "tune" "cortexa15")
- (eq_attr "neon_type"
- "neon_mrrc"))
+ (eq_attr "type" "neon_mrrc"))
"ca15_issue2,ca15_ls1+ca15_ls2")
(define_insn_reservation "cortex_a15_vfp_const" 4
;; Simple ALU without shift
(define_insn_reservation "cortex_a15_alu" 2
(and (eq_attr "tune" "cortexa15")
- (and (eq_attr "type" "arlo_imm,arlo_reg,shift,shift_reg,\
+ (eq_attr "type" "arlo_imm,arlo_reg,shift,shift_reg,\
mov_imm,mov_reg,\
- mvn_imm,mvn_reg")
- (eq_attr "neon_type" "none")))
+ mvn_imm,mvn_reg"))
"ca15_issue1,(ca15_sx1,ca15_sx1_alu)|(ca15_sx2,ca15_sx2_alu)")
;; ALU ops with immediate shift
(define_insn_reservation "cortex_a15_alu_shift" 3
(and (eq_attr "tune" "cortexa15")
- (and (eq_attr "type" "extend,arlo_shift,,mov_shift,mvn_shift")
- (eq_attr "neon_type" "none")))
+ (eq_attr "type" "extend,arlo_shift,,mov_shift,mvn_shift"))
"ca15_issue1,(ca15_sx1,ca15_sx1+ca15_sx1_shf,ca15_sx1_alu)\
|(ca15_sx2,ca15_sx2+ca15_sx2_shf,ca15_sx2_alu)")
;; ALU ops with register controlled shift
(define_insn_reservation "cortex_a15_alu_shift_reg" 3
(and (eq_attr "tune" "cortexa15")
- (and (eq_attr "type" "arlo_shift_reg,mov_shift_reg,mvn_shift_reg")
- (eq_attr "neon_type" "none")))
+ (eq_attr "type" "arlo_shift_reg,mov_shift_reg,mvn_shift_reg"))
"(ca15_issue2,ca15_sx1+ca15_sx2,ca15_sx1_shf,ca15_sx2_alu)\
|(ca15_issue1,(ca15_issue1+ca15_sx2,ca15_sx1+ca15_sx2_shf)\
|(ca15_issue1+ca15_sx1,ca15_sx1+ca15_sx1_shf),ca15_sx1_alu)")
;; 32-bit multiplies
(define_insn_reservation "cortex_a15_mult32" 3
(and (eq_attr "tune" "cortexa15")
- (and (eq_attr "mul32" "yes")
- (eq_attr "neon_type" "none")))
+ (eq_attr "mul32" "yes"))
"ca15_issue1,ca15_mx")
;; 64-bit multiplies
(define_insn_reservation "cortex_a15_mult64" 4
(and (eq_attr "tune" "cortexa15")
- (and (eq_attr "mul64" "yes")
- (eq_attr "neon_type" "none")))
+ (eq_attr "mul64" "yes"))
"ca15_issue1,ca15_mx*2")
;; Integer divide
;; Block all issue pipes for a cycle
(define_insn_reservation "cortex_a15_block" 1
(and (eq_attr "tune" "cortexa15")
- (and (eq_attr "type" "block")
- (eq_attr "neon_type" "none")))
+ (eq_attr "type" "block"))
"ca15_issue3")
;; Branch execution Unit
;; No latency as there is no result
(define_insn_reservation "cortex_a15_branch" 0
(and (eq_attr "tune" "cortexa15")
- (and (eq_attr "type" "branch")
- (eq_attr "neon_type" "none")))
+ (eq_attr "type" "branch"))
"ca15_issue1,ca15_bx")
;; Load-store execution Unit
;; Loads of up to two words.
(define_insn_reservation "cortex_a15_load1" 4
(and (eq_attr "tune" "cortexa15")
- (and (eq_attr "type" "load_byte,load1,load2")
- (eq_attr "neon_type" "none")))
+ (eq_attr "type" "load_byte,load1,load2"))
"ca15_issue1,ca15_ls,ca15_ldr,nothing")
;; Loads of three or four words.
(define_insn_reservation "cortex_a15_load3" 5
(and (eq_attr "tune" "cortexa15")
- (and (eq_attr "type" "load3,load4")
- (eq_attr "neon_type" "none")))
+ (eq_attr "type" "load3,load4"))
"ca15_issue2,ca15_ls1+ca15_ls2,ca15_ldr,ca15_ldr,nothing")
;; Stores of up to two words.
(define_insn_reservation "cortex_a15_store1" 0
(and (eq_attr "tune" "cortexa15")
- (and (eq_attr "type" "store1,store2")
- (eq_attr "neon_type" "none")))
+ (eq_attr "type" "store1,store2"))
"ca15_issue1,ca15_ls,ca15_str")
;; Stores of three or four words.
(define_insn_reservation "cortex_a15_store3" 0
(and (eq_attr "tune" "cortexa15")
- (and (eq_attr "type" "store3,store4")
- (eq_attr "neon_type" "none")))
+ (eq_attr "type" "store3,store4"))
"ca15_issue2,ca15_ls1+ca15_ls2,ca15_str,ca15_str")
;; We include Neon.md here to ensure that the branch can block the Neon units.
;; pipeline. The result however is available the next cycle.
(define_insn_reservation "cortex_a15_call" 1
(and (eq_attr "tune" "cortexa15")
- (and (eq_attr "type" "call")
- (eq_attr "neon_type" "none")))
+ (eq_attr "type" "call"))
"ca15_issue3,\
ca15_sx1+ca15_sx2+ca15_bx+ca15_mx+ca15_cx_ij+ca15_cx_ik+ca15_ls1+ca15_ls2+\
ca15_cx_imac1+ca15_cx_ialu1+ca15_cx_ialu2+ca15_cx_ishf+\
(define_insn_reservation "cortex_a5_r2f" 4
(and (eq_attr "tune" "cortexa5")
- (eq_attr "type" "r_2_f"))
+ (eq_attr "type" "f_mcr,f_mcrr"))
"cortex_a5_ex1")
(define_insn_reservation "cortex_a5_f2r" 2
(and (eq_attr "tune" "cortexa5")
- (eq_attr "type" "f_2_r"))
+ (eq_attr "type" "f_mrc,f_mrrc"))
"cortex_a5_ex1")
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
(define_insn_reservation "cortex_a53_r2f" 4
(and (eq_attr "tune" "cortexa53")
- (eq_attr "type" "r_2_f"))
+ (eq_attr "type" "f_mcr,f_mcrr"))
"cortex_a53_slot0")
(define_insn_reservation "cortex_a53_f2r" 2
(and (eq_attr "tune" "cortexa53")
- (eq_attr "type" "f_2_r"))
+ (eq_attr "type" "f_mrc,f_mrrc"))
"cortex_a53_slot0")
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
(define_insn_reservation "cortex_a7_branch" 0
(and (eq_attr "tune" "cortexa7")
- (and (eq_attr "type" "branch")
- (eq_attr "neon_type" "none")))
+ (eq_attr "type" "branch"))
"(cortex_a7_ex2|cortex_a7_ex1)+cortex_a7_branch")
;; Call cannot dual-issue as an older instruction. It can dual-issue
;; cycle.
(define_insn_reservation "cortex_a7_call" 1
(and (eq_attr "tune" "cortexa7")
- (and (eq_attr "type" "call")
- (eq_attr "neon_type" "none")))
+ (eq_attr "type" "call"))
"(cortex_a7_ex2|cortex_a7_both)+cortex_a7_branch")
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;; ALU instruction with an immediate operand can dual-issue.
(define_insn_reservation "cortex_a7_alu_imm" 2
(and (eq_attr "tune" "cortexa7")
- (and (ior (eq_attr "type" "arlo_imm,mov_imm,mvn_imm")
- (ior (eq_attr "type" "extend")
- (and (eq_attr "type" "mov_reg,mov_shift,mov_shift_reg")
- (not (eq_attr "length" "8")))))
- (eq_attr "neon_type" "none")))
+ (ior (eq_attr "type" "arlo_imm,mov_imm,mvn_imm,extend")
+ (and (eq_attr "type" "mov_reg,mov_shift,mov_shift_reg")
+ (not (eq_attr "length" "8")))))
"cortex_a7_ex2|cortex_a7_ex1")
;; ALU instruction with register operands can dual-issue
;; with a younger immediate-based instruction.
(define_insn_reservation "cortex_a7_alu_reg" 2
(and (eq_attr "tune" "cortexa7")
- (and (eq_attr "type" "arlo_reg,shift,shift_reg,mov_reg,mvn_reg")
- (eq_attr "neon_type" "none")))
+ (eq_attr "type" "arlo_reg,shift,shift_reg,mov_reg,mvn_reg"))
"cortex_a7_ex1")
(define_insn_reservation "cortex_a7_alu_shift" 2
(and (eq_attr "tune" "cortexa7")
- (and (eq_attr "type" "arlo_shift,arlo_shift_reg,\
- mov_shift,mov_shift_reg,\
- mvn_shift,mvn_shift_reg")
- (eq_attr "neon_type" "none")))
+ (eq_attr "type" "arlo_shift,arlo_shift_reg,\
+ mov_shift,mov_shift_reg,\
+ mvn_shift,mvn_shift_reg"))
"cortex_a7_ex1")
;; Forwarding path for unshifted operands.
(define_insn_reservation "cortex_a7_mul" 2
(and (eq_attr "tune" "cortexa7")
- (and (eq_attr "neon_type" "none")
- (ior (eq_attr "mul32" "yes")
- (eq_attr "mul64" "yes"))))
+ (ior (eq_attr "mul32" "yes")
+ (eq_attr "mul64" "yes")))
"cortex_a7_both")
;; Forward the result of a multiply operation to the accumulator
(define_insn_reservation "cortex_a7_load1" 2
(and (eq_attr "tune" "cortexa7")
- (and (eq_attr "type" "load_byte,load1")
- (eq_attr "neon_type" "none")))
+ (eq_attr "type" "load_byte,load1"))
"cortex_a7_ex1")
(define_insn_reservation "cortex_a7_store1" 0
(and (eq_attr "tune" "cortexa7")
- (and (eq_attr "type" "store1")
- (eq_attr "neon_type" "none")))
+ (eq_attr "type" "store1"))
"cortex_a7_ex1")
(define_insn_reservation "cortex_a7_load2" 2
(and (eq_attr "tune" "cortexa7")
- (and (eq_attr "type" "load2")
- (eq_attr "neon_type" "none")))
+ (eq_attr "type" "load2"))
"cortex_a7_both")
(define_insn_reservation "cortex_a7_store2" 0
(and (eq_attr "tune" "cortexa7")
- (and (eq_attr "type" "store2")
- (eq_attr "neon_type" "none")))
+ (eq_attr "type" "store2"))
"cortex_a7_both")
(define_insn_reservation "cortex_a7_load3" 3
(and (eq_attr "tune" "cortexa7")
- (and (eq_attr "type" "load3")
- (eq_attr "neon_type" "none")))
+ (eq_attr "type" "load3"))
"cortex_a7_both, cortex_a7_ex1")
(define_insn_reservation "cortex_a7_store3" 0
(and (eq_attr "tune" "cortexa7")
- (and (eq_attr "type" "store4")
- (eq_attr "neon_type" "none")))
+ (eq_attr "type" "store4"))
"cortex_a7_both, cortex_a7_ex1")
(define_insn_reservation "cortex_a7_load4" 3
(and (eq_attr "tune" "cortexa7")
- (and (eq_attr "type" "load4")
- (eq_attr "neon_type" "none")))
+ (eq_attr "type" "load4"))
"cortex_a7_both, cortex_a7_both")
(define_insn_reservation "cortex_a7_store4" 0
(and (eq_attr "tune" "cortexa7")
- (and (eq_attr "type" "store3")
- (eq_attr "neon_type" "none")))
+ (eq_attr "type" "store3"))
"cortex_a7_both, cortex_a7_both")
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
(define_insn_reservation "cortex_a7_fpalu" 4
(and (eq_attr "tune" "cortexa7")
- (and (eq_attr "type" "ffariths, fadds, ffarithd, faddd, fcpys,\
- f_cvt, fcmps, fcmpd")
- (eq_attr "neon_type" "none")))
+ (eq_attr "type" "ffariths, fadds, ffarithd, faddd, fcpys,\
+ f_cvt, fcmps, fcmpd"))
"cortex_a7_ex1+cortex_a7_fpadd_pipe")
;; For fconsts and fconstd, 8-bit immediate data is passed directly from
(define_insn_reservation "cortex_a7_fconst" 3
(and (eq_attr "tune" "cortexa7")
- (and (eq_attr "type" "fconsts,fconstd")
- (eq_attr "neon_type" "none")))
+ (eq_attr "type" "fconsts,fconstd"))
"cortex_a7_ex1+cortex_a7_fpadd_pipe")
;; We should try not to attempt to issue a single-precision multiplication in
(define_insn_reservation "cortex_a7_fpmuls" 4
(and (eq_attr "tune" "cortexa7")
- (and (eq_attr "type" "fmuls")
- (eq_attr "neon_type" "none")))
+ (eq_attr "type" "fmuls"))
"cortex_a7_ex1+cortex_a7_fpmul_pipe")
(define_insn_reservation "cortex_a7_neon_mul" 4
(and (eq_attr "tune" "cortexa7")
- (eq_attr "neon_type"
+ (eq_attr "type"
"neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\
neon_mul_qqq_8_16_32_ddd_32,\
neon_mul_qdd_64_32_long_qqd_16_ddd_32_scalar_64_32_long_scalar,\
(define_insn_reservation "cortex_a7_fpmacs" 8
(and (eq_attr "tune" "cortexa7")
- (and (eq_attr "type" "fmacs,ffmas")
- (eq_attr "neon_type" "none")))
+ (eq_attr "type" "fmacs,ffmas"))
"cortex_a7_ex1+cortex_a7_fpmul_pipe")
(define_insn_reservation "cortex_a7_neon_mla" 8
(and (eq_attr "tune" "cortexa7")
- (eq_attr "neon_type"
+ (eq_attr "type"
"neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\
neon_mla_qqq_8_16,\
neon_mla_ddd_32_qqd_16_ddd_32_scalar_qdd_64_32_long_scalar_qdd_64_32_long,\
(define_insn_reservation "cortex_a7_fpmuld" 7
(and (eq_attr "tune" "cortexa7")
- (and (eq_attr "type" "fmuld")
- (eq_attr "neon_type" "none")))
+ (eq_attr "type" "fmuld"))
"cortex_a7_ex1+cortex_a7_fpmul_pipe, cortex_a7_fpmul_pipe*3")
(define_insn_reservation "cortex_a7_fpmacd" 11
(and (eq_attr "tune" "cortexa7")
- (and (eq_attr "type" "fmacd")
- (eq_attr "neon_type" "none")))
+ (eq_attr "type" "fmacd"))
"cortex_a7_ex1+cortex_a7_fpmul_pipe, cortex_a7_fpmul_pipe*3")
(define_insn_reservation "cortex_a7_fpfmad" 8
(and (eq_attr "tune" "cortexa7")
- (and (eq_attr "type" "ffmad")
- (eq_attr "neon_type" "none")))
+ (eq_attr "type" "ffmad"))
"cortex_a7_ex1+cortex_a7_fpmul_pipe, cortex_a7_fpmul_pipe*4")
(define_bypass 7 "cortex_a7_fpmacd"
(define_insn_reservation "cortex_a7_fdivs" 16
(and (eq_attr "tune" "cortexa7")
- (and (eq_attr "type" "fdivs")
- (eq_attr "neon_type" "none")))
+ (eq_attr "type" "fdivs"))
"cortex_a7_ex1+cortex_a7_fp_div_sqrt, cortex_a7_fp_div_sqrt * 13")
(define_insn_reservation "cortex_a7_fdivd" 31
(and (eq_attr "tune" "cortexa7")
- (and (eq_attr "type" "fdivd")
- (eq_attr "neon_type" "none")))
+ (eq_attr "type" "fdivd"))
"cortex_a7_ex1+cortex_a7_fp_div_sqrt, cortex_a7_fp_div_sqrt * 28")
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
(define_insn_reservation "cortex_a7_r2f" 4
(and (eq_attr "tune" "cortexa7")
- (and (eq_attr "type" "r_2_f")
- (eq_attr "neon_type" "none")))
+ (eq_attr "type" "f_mcr,f_mcrr"))
"cortex_a7_both")
(define_insn_reservation "cortex_a7_f2r" 2
(and (eq_attr "tune" "cortexa7")
- (and (eq_attr "type" "f_2_r")
- (eq_attr "neon_type" "none")))
+ (eq_attr "type" "f_mrc,f_mrrc"))
"cortex_a7_ex1")
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
(define_insn_reservation "cortex_a7_f_flags" 4
(and (eq_attr "tune" "cortexa7")
- (and (eq_attr "type" "f_flag")
- (eq_attr "neon_type" "none")))
+ (eq_attr "type" "f_flag"))
"cortex_a7_ex1")
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
(define_insn_reservation "cortex_a7_f_loads" 4
(and (eq_attr "tune" "cortexa7")
- (and (eq_attr "type" "f_loads")
- (eq_attr "neon_type" "none")))
+ (eq_attr "type" "f_loads"))
"cortex_a7_ex1")
(define_insn_reservation "cortex_a7_f_loadd" 4
(and (eq_attr "tune" "cortexa7")
- (and (eq_attr "type" "f_loadd")
- (eq_attr "neon_type" "none")))
+ (eq_attr "type" "f_loadd"))
"cortex_a7_both")
(define_insn_reservation "cortex_a7_f_stores" 0
(and (eq_attr "tune" "cortexa7")
- (and (eq_attr "type" "f_stores")
- (eq_attr "neon_type" "none")))
+ (eq_attr "type" "f_stores"))
"cortex_a7_ex1")
(define_insn_reservation "cortex_a7_f_stored" 0
(and (eq_attr "tune" "cortexa7")
- (and (eq_attr "type" "f_stored")
- (eq_attr "neon_type" "none")))
+ (eq_attr "type" "f_stored"))
"cortex_a7_both")
;; Load-to-use for floating-point values has a penalty of one cycle,
(define_insn_reservation "cortex_a7_neon" 4
(and (eq_attr "tune" "cortexa7")
- (eq_attr "neon_type"
- "!none,\
- neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\
- neon_mul_qqq_8_16_32_ddd_32,\
- neon_mul_qdd_64_32_long_qqd_16_ddd_32_scalar_64_32_long_scalar,\
- neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\
- neon_mla_qqq_8_16,\
- neon_mla_ddd_32_qqd_16_ddd_32_scalar_qdd_64_32_long_scalar_qdd_64_32_long,\
- neon_mla_qqq_32_qqd_32_scalar,\
- neon_mul_ddd_16_scalar_32_16_long_scalar,\
- neon_mul_qqd_32_scalar,\
- neon_mla_ddd_16_scalar_qdd_32_16_long_scalar,\
- neon_fp_vmul_ddd,\
- neon_fp_vmul_qqd,\
- neon_fp_vmla_ddd,\
- neon_fp_vmla_qqq,\
- neon_fp_vmla_ddd_scalar,\
- neon_fp_vmla_qqq_scalar"))
+ (eq_attr "type"
+ "neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\
+ neon_mul_qqq_8_16_32_ddd_32,\
+ neon_mul_qdd_64_32_long_qqd_16_ddd_32_scalar_64_32_long_scalar,\
+ neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\
+ neon_mla_qqq_8_16,\
+ neon_mla_ddd_32_qqd_16_ddd_32_scalar_qdd_64_32_long_scalar_qdd_64_32_long,\
+ neon_mla_qqq_32_qqd_32_scalar,\
+ neon_mul_ddd_16_scalar_32_16_long_scalar,\
+ neon_mul_qqd_32_scalar,\
+ neon_mla_ddd_16_scalar_qdd_32_16_long_scalar,\
+ neon_fp_vmul_ddd,\
+ neon_fp_vmul_qqd,\
+ neon_fp_vmla_ddd,\
+ neon_fp_vmla_qqq,\
+ neon_fp_vmla_ddd_scalar,\
+ neon_fp_vmla_qqq_scalar"))
"cortex_a7_both*2")
(define_insn_reservation "cortex_a8_neon_mrc" 20
(and (eq_attr "tune" "cortexa8")
- (eq_attr "neon_type" "neon_mrc"))
+ (eq_attr "type" "neon_mrc"))
"cortex_a8_neon_ls")
(define_insn_reservation "cortex_a8_neon_mrrc" 21
(and (eq_attr "tune" "cortexa8")
- (eq_attr "neon_type" "neon_mrrc"))
+ (eq_attr "type" "neon_mrrc"))
"cortex_a8_neon_ls_2")
;; The remainder of this file is auto-generated by neon-schedgen.
;; produce a result at N3.
(define_insn_reservation "cortex_a8_neon_int_1" 3
(and (eq_attr "tune" "cortexa8")
- (eq_attr "neon_type" "neon_int_1"))
+ (eq_attr "type" "neon_int_1"))
"cortex_a8_neon_dp")
;; Instructions using this reservation read their (D|Q)m operands at N1,
;; their (D|Q)n operands at N2, and produce a result at N3.
(define_insn_reservation "cortex_a8_neon_int_2" 3
(and (eq_attr "tune" "cortexa8")
- (eq_attr "neon_type" "neon_int_2"))
+ (eq_attr "type" "neon_int_2"))
"cortex_a8_neon_dp")
;; Instructions using this reservation read their source operands at N1, and
;; produce a result at N3.
(define_insn_reservation "cortex_a8_neon_int_3" 3
(and (eq_attr "tune" "cortexa8")
- (eq_attr "neon_type" "neon_int_3"))
+ (eq_attr "type" "neon_int_3"))
"cortex_a8_neon_dp")
;; Instructions using this reservation read their source operands at N2, and
;; produce a result at N4.
(define_insn_reservation "cortex_a8_neon_int_4" 4
(and (eq_attr "tune" "cortexa8")
- (eq_attr "neon_type" "neon_int_4"))
+ (eq_attr "type" "neon_int_4"))
"cortex_a8_neon_dp")
;; Instructions using this reservation read their (D|Q)m operands at N1,
;; their (D|Q)n operands at N2, and produce a result at N4.
(define_insn_reservation "cortex_a8_neon_int_5" 4
(and (eq_attr "tune" "cortexa8")
- (eq_attr "neon_type" "neon_int_5"))
+ (eq_attr "type" "neon_int_5"))
"cortex_a8_neon_dp")
;; Instructions using this reservation read their source operands at N1, and
;; produce a result at N4.
(define_insn_reservation "cortex_a8_neon_vqneg_vqabs" 4
(and (eq_attr "tune" "cortexa8")
- (eq_attr "neon_type" "neon_vqneg_vqabs"))
+ (eq_attr "type" "neon_vqneg_vqabs"))
"cortex_a8_neon_dp")
;; Instructions using this reservation produce a result at N3.
(define_insn_reservation "cortex_a8_neon_vmov" 3
(and (eq_attr "tune" "cortexa8")
- (eq_attr "neon_type" "neon_vmov"))
+ (eq_attr "type" "neon_vmov"))
"cortex_a8_neon_dp")
;; Instructions using this reservation read their (D|Q)n operands at N2,
;; produce a result at N6.
(define_insn_reservation "cortex_a8_neon_vaba" 6
(and (eq_attr "tune" "cortexa8")
- (eq_attr "neon_type" "neon_vaba"))
+ (eq_attr "type" "neon_vaba"))
"cortex_a8_neon_dp")
;; Instructions using this reservation read their (D|Q)n operands at N2,
;; produce a result at N6 on cycle 2.
(define_insn_reservation "cortex_a8_neon_vaba_qqq" 7
(and (eq_attr "tune" "cortexa8")
- (eq_attr "neon_type" "neon_vaba_qqq"))
+ (eq_attr "type" "neon_vaba_qqq"))
"cortex_a8_neon_dp_2")
;; Instructions using this reservation read their (D|Q)m operands at N1,
;; their (D|Q)d operands at N3, and produce a result at N6.
(define_insn_reservation "cortex_a8_neon_vsma" 6
(and (eq_attr "tune" "cortexa8")
- (eq_attr "neon_type" "neon_vsma"))
+ (eq_attr "type" "neon_vsma"))
"cortex_a8_neon_dp")
;; Instructions using this reservation read their source operands at N2, and
;; produce a result at N6.
(define_insn_reservation "cortex_a8_neon_mul_ddd_8_16_qdd_16_8_long_32_16_long" 6
(and (eq_attr "tune" "cortexa8")
- (eq_attr "neon_type" "neon_mul_ddd_8_16_qdd_16_8_long_32_16_long"))
+ (eq_attr "type" "neon_mul_ddd_8_16_qdd_16_8_long_32_16_long"))
"cortex_a8_neon_dp")
;; Instructions using this reservation read their source operands at N2, and
;; produce a result at N6 on cycle 2.
(define_insn_reservation "cortex_a8_neon_mul_qqq_8_16_32_ddd_32" 7
(and (eq_attr "tune" "cortexa8")
- (eq_attr "neon_type" "neon_mul_qqq_8_16_32_ddd_32"))
+ (eq_attr "type" "neon_mul_qqq_8_16_32_ddd_32"))
"cortex_a8_neon_dp_2")
;; Instructions using this reservation read their (D|Q)n operands at N2,
;; their (D|Q)m operands at N1, and produce a result at N6 on cycle 2.
(define_insn_reservation "cortex_a8_neon_mul_qdd_64_32_long_qqd_16_ddd_32_scalar_64_32_long_scalar" 7
(and (eq_attr "tune" "cortexa8")
- (eq_attr "neon_type" "neon_mul_qdd_64_32_long_qqd_16_ddd_32_scalar_64_32_long_scalar"))
+ (eq_attr "type" "neon_mul_qdd_64_32_long_qqd_16_ddd_32_scalar_64_32_long_scalar"))
"cortex_a8_neon_dp_2")
;; Instructions using this reservation read their (D|Q)n operands at N2,
;; produce a result at N6.
(define_insn_reservation "cortex_a8_neon_mla_ddd_8_16_qdd_16_8_long_32_16_long" 6
(and (eq_attr "tune" "cortexa8")
- (eq_attr "neon_type" "neon_mla_ddd_8_16_qdd_16_8_long_32_16_long"))
+ (eq_attr "type" "neon_mla_ddd_8_16_qdd_16_8_long_32_16_long"))
"cortex_a8_neon_dp")
;; Instructions using this reservation read their (D|Q)n operands at N2,
;; produce a result at N6 on cycle 2.
(define_insn_reservation "cortex_a8_neon_mla_qqq_8_16" 7
(and (eq_attr "tune" "cortexa8")
- (eq_attr "neon_type" "neon_mla_qqq_8_16"))
+ (eq_attr "type" "neon_mla_qqq_8_16"))
"cortex_a8_neon_dp_2")
;; Instructions using this reservation read their (D|Q)n operands at N2,
;; produce a result at N6 on cycle 2.
(define_insn_reservation "cortex_a8_neon_mla_ddd_32_qqd_16_ddd_32_scalar_qdd_64_32_long_scalar_qdd_64_32_long" 7
(and (eq_attr "tune" "cortexa8")
- (eq_attr "neon_type" "neon_mla_ddd_32_qqd_16_ddd_32_scalar_qdd_64_32_long_scalar_qdd_64_32_long"))
+ (eq_attr "type" "neon_mla_ddd_32_qqd_16_ddd_32_scalar_qdd_64_32_long_scalar_qdd_64_32_long"))
"cortex_a8_neon_dp_2")
;; Instructions using this reservation read their (D|Q)n operands at N2,
;; produce a result at N6 on cycle 4.
(define_insn_reservation "cortex_a8_neon_mla_qqq_32_qqd_32_scalar" 9
(and (eq_attr "tune" "cortexa8")
- (eq_attr "neon_type" "neon_mla_qqq_32_qqd_32_scalar"))
+ (eq_attr "type" "neon_mla_qqq_32_qqd_32_scalar"))
"cortex_a8_neon_dp_4")
;; Instructions using this reservation read their (D|Q)n operands at N2,
;; their (D|Q)m operands at N1, and produce a result at N6.
(define_insn_reservation "cortex_a8_neon_mul_ddd_16_scalar_32_16_long_scalar" 6
(and (eq_attr "tune" "cortexa8")
- (eq_attr "neon_type" "neon_mul_ddd_16_scalar_32_16_long_scalar"))
+ (eq_attr "type" "neon_mul_ddd_16_scalar_32_16_long_scalar"))
"cortex_a8_neon_dp")
;; Instructions using this reservation read their (D|Q)n operands at N2,
;; their (D|Q)m operands at N1, and produce a result at N6 on cycle 4.
(define_insn_reservation "cortex_a8_neon_mul_qqd_32_scalar" 9
(and (eq_attr "tune" "cortexa8")
- (eq_attr "neon_type" "neon_mul_qqd_32_scalar"))
+ (eq_attr "type" "neon_mul_qqd_32_scalar"))
"cortex_a8_neon_dp_4")
;; Instructions using this reservation read their (D|Q)n operands at N2,
;; produce a result at N6.
(define_insn_reservation "cortex_a8_neon_mla_ddd_16_scalar_qdd_32_16_long_scalar" 6
(and (eq_attr "tune" "cortexa8")
- (eq_attr "neon_type" "neon_mla_ddd_16_scalar_qdd_32_16_long_scalar"))
+ (eq_attr "type" "neon_mla_ddd_16_scalar_qdd_32_16_long_scalar"))
"cortex_a8_neon_dp")
;; Instructions using this reservation read their source operands at N1, and
;; produce a result at N3.
(define_insn_reservation "cortex_a8_neon_shift_1" 3
(and (eq_attr "tune" "cortexa8")
- (eq_attr "neon_type" "neon_shift_1"))
+ (eq_attr "type" "neon_shift_1"))
"cortex_a8_neon_dp")
;; Instructions using this reservation read their source operands at N1, and
;; produce a result at N4.
(define_insn_reservation "cortex_a8_neon_shift_2" 4
(and (eq_attr "tune" "cortexa8")
- (eq_attr "neon_type" "neon_shift_2"))
+ (eq_attr "type" "neon_shift_2"))
"cortex_a8_neon_dp")
;; Instructions using this reservation read their source operands at N1, and
;; produce a result at N3 on cycle 2.
(define_insn_reservation "cortex_a8_neon_shift_3" 4
(and (eq_attr "tune" "cortexa8")
- (eq_attr "neon_type" "neon_shift_3"))
+ (eq_attr "type" "neon_shift_3"))
"cortex_a8_neon_dp_2")
;; Instructions using this reservation read their source operands at N1, and
;; produce a result at N1.
(define_insn_reservation "cortex_a8_neon_vshl_ddd" 1
(and (eq_attr "tune" "cortexa8")
- (eq_attr "neon_type" "neon_vshl_ddd"))
+ (eq_attr "type" "neon_vshl_ddd"))
"cortex_a8_neon_dp")
;; Instructions using this reservation read their source operands at N1, and
;; produce a result at N4 on cycle 2.
(define_insn_reservation "cortex_a8_neon_vqshl_vrshl_vqrshl_qqq" 5
(and (eq_attr "tune" "cortexa8")
- (eq_attr "neon_type" "neon_vqshl_vrshl_vqrshl_qqq"))
+ (eq_attr "type" "neon_vqshl_vrshl_vqrshl_qqq"))
"cortex_a8_neon_dp_2")
;; Instructions using this reservation read their (D|Q)m operands at N1,
;; their (D|Q)d operands at N3, and produce a result at N6.
(define_insn_reservation "cortex_a8_neon_vsra_vrsra" 6
(and (eq_attr "tune" "cortexa8")
- (eq_attr "neon_type" "neon_vsra_vrsra"))
+ (eq_attr "type" "neon_vsra_vrsra"))
"cortex_a8_neon_dp")
;; Instructions using this reservation read their source operands at N2, and
;; produce a result at N5.
(define_insn_reservation "cortex_a8_neon_fp_vadd_ddd_vabs_dd" 5
(and (eq_attr "tune" "cortexa8")
- (eq_attr "neon_type" "neon_fp_vadd_ddd_vabs_dd"))
+ (eq_attr "type" "neon_fp_vadd_ddd_vabs_dd"))
"cortex_a8_neon_fadd")
;; Instructions using this reservation read their source operands at N2, and
;; produce a result at N5 on cycle 2.
(define_insn_reservation "cortex_a8_neon_fp_vadd_qqq_vabs_qq" 6
(and (eq_attr "tune" "cortexa8")
- (eq_attr "neon_type" "neon_fp_vadd_qqq_vabs_qq"))
+ (eq_attr "type" "neon_fp_vadd_qqq_vabs_qq"))
"cortex_a8_neon_fadd_2")
;; Instructions using this reservation read their source operands at N1, and
;; produce a result at N5.
(define_insn_reservation "cortex_a8_neon_fp_vsum" 5
(and (eq_attr "tune" "cortexa8")
- (eq_attr "neon_type" "neon_fp_vsum"))
+ (eq_attr "type" "neon_fp_vsum"))
"cortex_a8_neon_fadd")
;; Instructions using this reservation read their (D|Q)n operands at N2,
;; their (D|Q)m operands at N1, and produce a result at N5.
(define_insn_reservation "cortex_a8_neon_fp_vmul_ddd" 5
(and (eq_attr "tune" "cortexa8")
- (eq_attr "neon_type" "neon_fp_vmul_ddd"))
+ (eq_attr "type" "neon_fp_vmul_ddd"))
"cortex_a8_neon_dp")
;; Instructions using this reservation read their (D|Q)n operands at N2,
;; their (D|Q)m operands at N1, and produce a result at N5 on cycle 2.
(define_insn_reservation "cortex_a8_neon_fp_vmul_qqd" 6
(and (eq_attr "tune" "cortexa8")
- (eq_attr "neon_type" "neon_fp_vmul_qqd"))
+ (eq_attr "type" "neon_fp_vmul_qqd"))
"cortex_a8_neon_dp_2")
;; Instructions using this reservation read their (D|Q)n operands at N2,
;; produce a result at N9.
(define_insn_reservation "cortex_a8_neon_fp_vmla_ddd" 9
(and (eq_attr "tune" "cortexa8")
- (eq_attr "neon_type" "neon_fp_vmla_ddd"))
+ (eq_attr "type" "neon_fp_vmla_ddd"))
"cortex_a8_neon_fmul_then_fadd")
;; Instructions using this reservation read their (D|Q)n operands at N2,
;; produce a result at N9 on cycle 2.
(define_insn_reservation "cortex_a8_neon_fp_vmla_qqq" 10
(and (eq_attr "tune" "cortexa8")
- (eq_attr "neon_type" "neon_fp_vmla_qqq"))
+ (eq_attr "type" "neon_fp_vmla_qqq"))
"cortex_a8_neon_fmul_then_fadd_2")
;; Instructions using this reservation read their (D|Q)n operands at N2,
;; produce a result at N9.
(define_insn_reservation "cortex_a8_neon_fp_vmla_ddd_scalar" 9
(and (eq_attr "tune" "cortexa8")
- (eq_attr "neon_type" "neon_fp_vmla_ddd_scalar"))
+ (eq_attr "type" "neon_fp_vmla_ddd_scalar"))
"cortex_a8_neon_fmul_then_fadd")
;; Instructions using this reservation read their (D|Q)n operands at N2,
;; produce a result at N9 on cycle 2.
(define_insn_reservation "cortex_a8_neon_fp_vmla_qqq_scalar" 10
(and (eq_attr "tune" "cortexa8")
- (eq_attr "neon_type" "neon_fp_vmla_qqq_scalar"))
+ (eq_attr "type" "neon_fp_vmla_qqq_scalar"))
"cortex_a8_neon_fmul_then_fadd_2")
;; Instructions using this reservation read their source operands at N2, and
;; produce a result at N9.
(define_insn_reservation "cortex_a8_neon_fp_vrecps_vrsqrts_ddd" 9
(and (eq_attr "tune" "cortexa8")
- (eq_attr "neon_type" "neon_fp_vrecps_vrsqrts_ddd"))
+ (eq_attr "type" "neon_fp_vrecps_vrsqrts_ddd"))
"cortex_a8_neon_fmul_then_fadd")
;; Instructions using this reservation read their source operands at N2, and
;; produce a result at N9 on cycle 2.
(define_insn_reservation "cortex_a8_neon_fp_vrecps_vrsqrts_qqq" 10
(and (eq_attr "tune" "cortexa8")
- (eq_attr "neon_type" "neon_fp_vrecps_vrsqrts_qqq"))
+ (eq_attr "type" "neon_fp_vrecps_vrsqrts_qqq"))
"cortex_a8_neon_fmul_then_fadd_2")
;; Instructions using this reservation read their source operands at N1, and
;; produce a result at N2.
(define_insn_reservation "cortex_a8_neon_bp_simple" 2
(and (eq_attr "tune" "cortexa8")
- (eq_attr "neon_type" "neon_bp_simple"))
+ (eq_attr "type" "neon_bp_simple"))
"cortex_a8_neon_perm")
;; Instructions using this reservation read their source operands at N1, and
;; produce a result at N2 on cycle 2.
(define_insn_reservation "cortex_a8_neon_bp_2cycle" 3
(and (eq_attr "tune" "cortexa8")
- (eq_attr "neon_type" "neon_bp_2cycle"))
+ (eq_attr "type" "neon_bp_2cycle"))
"cortex_a8_neon_perm_2")
;; Instructions using this reservation read their source operands at N1, and
;; produce a result at N2 on cycle 3.
(define_insn_reservation "cortex_a8_neon_bp_3cycle" 4
(and (eq_attr "tune" "cortexa8")
- (eq_attr "neon_type" "neon_bp_3cycle"))
+ (eq_attr "type" "neon_bp_3cycle"))
"cortex_a8_neon_perm_3")
;; Instructions using this reservation produce a result at N1.
(define_insn_reservation "cortex_a8_neon_ldr" 1
(and (eq_attr "tune" "cortexa8")
- (eq_attr "neon_type" "neon_ldr"))
+ (eq_attr "type" "neon_ldr"))
"cortex_a8_neon_ls")
;; Instructions using this reservation read their source operands at N1.
(define_insn_reservation "cortex_a8_neon_str" 0
(and (eq_attr "tune" "cortexa8")
- (eq_attr "neon_type" "neon_str"))
+ (eq_attr "type" "neon_str"))
"cortex_a8_neon_ls")
;; Instructions using this reservation produce a result at N1 on cycle 2.
(define_insn_reservation "cortex_a8_neon_vld1_1_2_regs" 2
(and (eq_attr "tune" "cortexa8")
- (eq_attr "neon_type" "neon_vld1_1_2_regs"))
+ (eq_attr "type" "neon_vld1_1_2_regs"))
"cortex_a8_neon_ls_2")
;; Instructions using this reservation produce a result at N1 on cycle 3.
(define_insn_reservation "cortex_a8_neon_vld1_3_4_regs" 3
(and (eq_attr "tune" "cortexa8")
- (eq_attr "neon_type" "neon_vld1_3_4_regs"))
+ (eq_attr "type" "neon_vld1_3_4_regs"))
"cortex_a8_neon_ls_3")
;; Instructions using this reservation produce a result at N2 on cycle 2.
(define_insn_reservation "cortex_a8_neon_vld2_2_regs_vld1_vld2_all_lanes" 3
(and (eq_attr "tune" "cortexa8")
- (eq_attr "neon_type" "neon_vld2_2_regs_vld1_vld2_all_lanes"))
+ (eq_attr "type" "neon_vld2_2_regs_vld1_vld2_all_lanes"))
"cortex_a8_neon_ls_2")
;; Instructions using this reservation produce a result at N2 on cycle 3.
(define_insn_reservation "cortex_a8_neon_vld2_4_regs" 4
(and (eq_attr "tune" "cortexa8")
- (eq_attr "neon_type" "neon_vld2_4_regs"))
+ (eq_attr "type" "neon_vld2_4_regs"))
"cortex_a8_neon_ls_3")
;; Instructions using this reservation produce a result at N2 on cycle 4.
(define_insn_reservation "cortex_a8_neon_vld3_vld4" 5
(and (eq_attr "tune" "cortexa8")
- (eq_attr "neon_type" "neon_vld3_vld4"))
+ (eq_attr "type" "neon_vld3_vld4"))
"cortex_a8_neon_ls_4")
;; Instructions using this reservation read their source operands at N1.
(define_insn_reservation "cortex_a8_neon_vst1_1_2_regs_vst2_2_regs" 0
(and (eq_attr "tune" "cortexa8")
- (eq_attr "neon_type" "neon_vst1_1_2_regs_vst2_2_regs"))
+ (eq_attr "type" "neon_vst1_1_2_regs_vst2_2_regs"))
"cortex_a8_neon_ls_2")
;; Instructions using this reservation read their source operands at N1.
(define_insn_reservation "cortex_a8_neon_vst1_3_4_regs" 0
(and (eq_attr "tune" "cortexa8")
- (eq_attr "neon_type" "neon_vst1_3_4_regs"))
+ (eq_attr "type" "neon_vst1_3_4_regs"))
"cortex_a8_neon_ls_3")
;; Instructions using this reservation read their source operands at N1.
(define_insn_reservation "cortex_a8_neon_vst2_4_regs_vst3_vst4" 0
(and (eq_attr "tune" "cortexa8")
- (eq_attr "neon_type" "neon_vst2_4_regs_vst3_vst4"))
+ (eq_attr "type" "neon_vst2_4_regs_vst3_vst4"))
"cortex_a8_neon_ls_4")
;; Instructions using this reservation read their source operands at N1.
(define_insn_reservation "cortex_a8_neon_vst3_vst4" 0
(and (eq_attr "tune" "cortexa8")
- (eq_attr "neon_type" "neon_vst3_vst4"))
+ (eq_attr "type" "neon_vst3_vst4"))
"cortex_a8_neon_ls_4")
;; Instructions using this reservation read their source operands at N1, and
;; produce a result at N2 on cycle 3.
(define_insn_reservation "cortex_a8_neon_vld1_vld2_lane" 4
(and (eq_attr "tune" "cortexa8")
- (eq_attr "neon_type" "neon_vld1_vld2_lane"))
+ (eq_attr "type" "neon_vld1_vld2_lane"))
"cortex_a8_neon_ls_3")
;; Instructions using this reservation read their source operands at N1, and
;; produce a result at N2 on cycle 5.
(define_insn_reservation "cortex_a8_neon_vld3_vld4_lane" 6
(and (eq_attr "tune" "cortexa8")
- (eq_attr "neon_type" "neon_vld3_vld4_lane"))
+ (eq_attr "type" "neon_vld3_vld4_lane"))
"cortex_a8_neon_ls_5")
;; Instructions using this reservation read their source operands at N1.
(define_insn_reservation "cortex_a8_neon_vst1_vst2_lane" 0
(and (eq_attr "tune" "cortexa8")
- (eq_attr "neon_type" "neon_vst1_vst2_lane"))
+ (eq_attr "type" "neon_vst1_vst2_lane"))
"cortex_a8_neon_ls_2")
;; Instructions using this reservation read their source operands at N1.
(define_insn_reservation "cortex_a8_neon_vst3_vst4_lane" 0
(and (eq_attr "tune" "cortexa8")
- (eq_attr "neon_type" "neon_vst3_vst4_lane"))
+ (eq_attr "type" "neon_vst3_vst4_lane"))
"cortex_a8_neon_ls_3")
;; Instructions using this reservation produce a result at N2 on cycle 2.
(define_insn_reservation "cortex_a8_neon_vld3_vld4_all_lanes" 3
(and (eq_attr "tune" "cortexa8")
- (eq_attr "neon_type" "neon_vld3_vld4_all_lanes"))
+ (eq_attr "type" "neon_vld3_vld4_all_lanes"))
"cortex_a8_neon_ls_3")
;; Instructions using this reservation produce a result at N2.
(define_insn_reservation "cortex_a8_neon_mcr" 2
(and (eq_attr "tune" "cortexa8")
- (eq_attr "neon_type" "neon_mcr"))
+ (eq_attr "type" "neon_mcr"))
"cortex_a8_neon_perm")
;; Instructions using this reservation produce a result at N2.
(define_insn_reservation "cortex_a8_neon_mcr_2_mcrr" 2
(and (eq_attr "tune" "cortexa8")
- (eq_attr "neon_type" "neon_mcr_2_mcrr"))
+ (eq_attr "type" "neon_mcr_2_mcrr"))
"cortex_a8_neon_perm_2")
;; Exceptions to the default latencies.
;; (source read in E2 and destination available at the end of that cycle).
(define_insn_reservation "cortex_a8_alu" 2
(and (eq_attr "tune" "cortexa8")
- (ior (and (eq_attr "type" "arlo_imm,arlo_reg,shift,shift_reg")
- (eq_attr "neon_type" "none"))
- (eq_attr "type" "clz")))
+ (eq_attr "type" "arlo_imm,arlo_reg,shift,shift_reg,clz"))
"cortex_a8_default")
(define_insn_reservation "cortex_a8_alu_shift" 2
;; NEON -> core transfers.
(define_insn_reservation "ca9_neon_mrc" 1
(and (eq_attr "tune" "cortexa9")
- (eq_attr "neon_type" "neon_mrc"))
+ (eq_attr "type" "neon_mrc"))
"ca9_issue_vfp_neon + cortex_a9_neon_mcr")
(define_insn_reservation "ca9_neon_mrrc" 1
(and (eq_attr "tune" "cortexa9")
- (eq_attr "neon_type" "neon_mrrc"))
+ (eq_attr "type" "neon_mrrc"))
"ca9_issue_vfp_neon + cortex_a9_neon_mcr")
;; The remainder of this file is auto-generated by neon-schedgen.
;; produce a result at N3.
(define_insn_reservation "cortex_a9_neon_int_1" 3
(and (eq_attr "tune" "cortexa9")
- (eq_attr "neon_type" "neon_int_1"))
+ (eq_attr "type" "neon_int_1"))
"cortex_a9_neon_dp")
;; Instructions using this reservation read their (D|Q)m operands at N1,
;; their (D|Q)n operands at N2, and produce a result at N3.
(define_insn_reservation "cortex_a9_neon_int_2" 3
(and (eq_attr "tune" "cortexa9")
- (eq_attr "neon_type" "neon_int_2"))
+ (eq_attr "type" "neon_int_2"))
"cortex_a9_neon_dp")
;; Instructions using this reservation read their source operands at N1, and
;; produce a result at N3.
(define_insn_reservation "cortex_a9_neon_int_3" 3
(and (eq_attr "tune" "cortexa9")
- (eq_attr "neon_type" "neon_int_3"))
+ (eq_attr "type" "neon_int_3"))
"cortex_a9_neon_dp")
;; Instructions using this reservation read their source operands at N2, and
;; produce a result at N4.
(define_insn_reservation "cortex_a9_neon_int_4" 4
(and (eq_attr "tune" "cortexa9")
- (eq_attr "neon_type" "neon_int_4"))
+ (eq_attr "type" "neon_int_4"))
"cortex_a9_neon_dp")
;; Instructions using this reservation read their (D|Q)m operands at N1,
;; their (D|Q)n operands at N2, and produce a result at N4.
(define_insn_reservation "cortex_a9_neon_int_5" 4
(and (eq_attr "tune" "cortexa9")
- (eq_attr "neon_type" "neon_int_5"))
+ (eq_attr "type" "neon_int_5"))
"cortex_a9_neon_dp")
;; Instructions using this reservation read their source operands at N1, and
;; produce a result at N4.
(define_insn_reservation "cortex_a9_neon_vqneg_vqabs" 4
(and (eq_attr "tune" "cortexa9")
- (eq_attr "neon_type" "neon_vqneg_vqabs"))
+ (eq_attr "type" "neon_vqneg_vqabs"))
"cortex_a9_neon_dp")
;; Instructions using this reservation produce a result at N3.
(define_insn_reservation "cortex_a9_neon_vmov" 3
(and (eq_attr "tune" "cortexa9")
- (eq_attr "neon_type" "neon_vmov"))
+ (eq_attr "type" "neon_vmov"))
"cortex_a9_neon_dp")
;; Instructions using this reservation read their (D|Q)n operands at N2,
;; produce a result at N6.
(define_insn_reservation "cortex_a9_neon_vaba" 6
(and (eq_attr "tune" "cortexa9")
- (eq_attr "neon_type" "neon_vaba"))
+ (eq_attr "type" "neon_vaba"))
"cortex_a9_neon_dp")
;; Instructions using this reservation read their (D|Q)n operands at N2,
;; produce a result at N6 on cycle 2.
(define_insn_reservation "cortex_a9_neon_vaba_qqq" 7
(and (eq_attr "tune" "cortexa9")
- (eq_attr "neon_type" "neon_vaba_qqq"))
+ (eq_attr "type" "neon_vaba_qqq"))
"cortex_a9_neon_dp_2")
;; Instructions using this reservation read their (D|Q)m operands at N1,
;; their (D|Q)d operands at N3, and produce a result at N6.
(define_insn_reservation "cortex_a9_neon_vsma" 6
(and (eq_attr "tune" "cortexa9")
- (eq_attr "neon_type" "neon_vsma"))
+ (eq_attr "type" "neon_vsma"))
"cortex_a9_neon_dp")
;; Instructions using this reservation read their source operands at N2, and
;; produce a result at N6.
(define_insn_reservation "cortex_a9_neon_mul_ddd_8_16_qdd_16_8_long_32_16_long" 6
(and (eq_attr "tune" "cortexa9")
- (eq_attr "neon_type" "neon_mul_ddd_8_16_qdd_16_8_long_32_16_long"))
+ (eq_attr "type" "neon_mul_ddd_8_16_qdd_16_8_long_32_16_long"))
"cortex_a9_neon_dp")
;; Instructions using this reservation read their source operands at N2, and
;; produce a result at N6 on cycle 2.
(define_insn_reservation "cortex_a9_neon_mul_qqq_8_16_32_ddd_32" 7
(and (eq_attr "tune" "cortexa9")
- (eq_attr "neon_type" "neon_mul_qqq_8_16_32_ddd_32"))
+ (eq_attr "type" "neon_mul_qqq_8_16_32_ddd_32"))
"cortex_a9_neon_dp_2")
;; Instructions using this reservation read their (D|Q)n operands at N2,
;; their (D|Q)m operands at N1, and produce a result at N6 on cycle 2.
(define_insn_reservation "cortex_a9_neon_mul_qdd_64_32_long_qqd_16_ddd_32_scalar_64_32_long_scalar" 7
(and (eq_attr "tune" "cortexa9")
- (eq_attr "neon_type" "neon_mul_qdd_64_32_long_qqd_16_ddd_32_scalar_64_32_long_scalar"))
+ (eq_attr "type" "neon_mul_qdd_64_32_long_qqd_16_ddd_32_scalar_64_32_long_scalar"))
"cortex_a9_neon_dp_2")
;; Instructions using this reservation read their (D|Q)n operands at N2,
;; produce a result at N6.
(define_insn_reservation "cortex_a9_neon_mla_ddd_8_16_qdd_16_8_long_32_16_long" 6
(and (eq_attr "tune" "cortexa9")
- (eq_attr "neon_type" "neon_mla_ddd_8_16_qdd_16_8_long_32_16_long"))
+ (eq_attr "type" "neon_mla_ddd_8_16_qdd_16_8_long_32_16_long"))
"cortex_a9_neon_dp")
;; Instructions using this reservation read their (D|Q)n operands at N2,
;; produce a result at N6 on cycle 2.
(define_insn_reservation "cortex_a9_neon_mla_qqq_8_16" 7
(and (eq_attr "tune" "cortexa9")
- (eq_attr "neon_type" "neon_mla_qqq_8_16"))
+ (eq_attr "type" "neon_mla_qqq_8_16"))
"cortex_a9_neon_dp_2")
;; Instructions using this reservation read their (D|Q)n operands at N2,
;; produce a result at N6 on cycle 2.
(define_insn_reservation "cortex_a9_neon_mla_ddd_32_qqd_16_ddd_32_scalar_qdd_64_32_long_scalar_qdd_64_32_long" 7
(and (eq_attr "tune" "cortexa9")
- (eq_attr "neon_type" "neon_mla_ddd_32_qqd_16_ddd_32_scalar_qdd_64_32_long_scalar_qdd_64_32_long"))
+ (eq_attr "type" "neon_mla_ddd_32_qqd_16_ddd_32_scalar_qdd_64_32_long_scalar_qdd_64_32_long"))
"cortex_a9_neon_dp_2")
;; Instructions using this reservation read their (D|Q)n operands at N2,
;; produce a result at N6 on cycle 4.
(define_insn_reservation "cortex_a9_neon_mla_qqq_32_qqd_32_scalar" 9
(and (eq_attr "tune" "cortexa9")
- (eq_attr "neon_type" "neon_mla_qqq_32_qqd_32_scalar"))
+ (eq_attr "type" "neon_mla_qqq_32_qqd_32_scalar"))
"cortex_a9_neon_dp_4")
;; Instructions using this reservation read their (D|Q)n operands at N2,
;; their (D|Q)m operands at N1, and produce a result at N6.
(define_insn_reservation "cortex_a9_neon_mul_ddd_16_scalar_32_16_long_scalar" 6
(and (eq_attr "tune" "cortexa9")
- (eq_attr "neon_type" "neon_mul_ddd_16_scalar_32_16_long_scalar"))
+ (eq_attr "type" "neon_mul_ddd_16_scalar_32_16_long_scalar"))
"cortex_a9_neon_dp")
;; Instructions using this reservation read their (D|Q)n operands at N2,
;; their (D|Q)m operands at N1, and produce a result at N6 on cycle 4.
(define_insn_reservation "cortex_a9_neon_mul_qqd_32_scalar" 9
(and (eq_attr "tune" "cortexa9")
- (eq_attr "neon_type" "neon_mul_qqd_32_scalar"))
+ (eq_attr "type" "neon_mul_qqd_32_scalar"))
"cortex_a9_neon_dp_4")
;; Instructions using this reservation read their (D|Q)n operands at N2,
;; produce a result at N6.
(define_insn_reservation "cortex_a9_neon_mla_ddd_16_scalar_qdd_32_16_long_scalar" 6
(and (eq_attr "tune" "cortexa9")
- (eq_attr "neon_type" "neon_mla_ddd_16_scalar_qdd_32_16_long_scalar"))
+ (eq_attr "type" "neon_mla_ddd_16_scalar_qdd_32_16_long_scalar"))
"cortex_a9_neon_dp")
;; Instructions using this reservation read their source operands at N1, and
;; produce a result at N3.
(define_insn_reservation "cortex_a9_neon_shift_1" 3
(and (eq_attr "tune" "cortexa9")
- (eq_attr "neon_type" "neon_shift_1"))
+ (eq_attr "type" "neon_shift_1"))
"cortex_a9_neon_dp")
;; Instructions using this reservation read their source operands at N1, and
;; produce a result at N4.
(define_insn_reservation "cortex_a9_neon_shift_2" 4
(and (eq_attr "tune" "cortexa9")
- (eq_attr "neon_type" "neon_shift_2"))
+ (eq_attr "type" "neon_shift_2"))
"cortex_a9_neon_dp")
;; Instructions using this reservation read their source operands at N1, and
;; produce a result at N3 on cycle 2.
(define_insn_reservation "cortex_a9_neon_shift_3" 4
(and (eq_attr "tune" "cortexa9")
- (eq_attr "neon_type" "neon_shift_3"))
+ (eq_attr "type" "neon_shift_3"))
"cortex_a9_neon_dp_2")
;; Instructions using this reservation read their source operands at N1, and
;; produce a result at N1.
(define_insn_reservation "cortex_a9_neon_vshl_ddd" 1
(and (eq_attr "tune" "cortexa9")
- (eq_attr "neon_type" "neon_vshl_ddd"))
+ (eq_attr "type" "neon_vshl_ddd"))
"cortex_a9_neon_dp")
;; Instructions using this reservation read their source operands at N1, and
;; produce a result at N4 on cycle 2.
(define_insn_reservation "cortex_a9_neon_vqshl_vrshl_vqrshl_qqq" 5
(and (eq_attr "tune" "cortexa9")
- (eq_attr "neon_type" "neon_vqshl_vrshl_vqrshl_qqq"))
+ (eq_attr "type" "neon_vqshl_vrshl_vqrshl_qqq"))
"cortex_a9_neon_dp_2")
;; Instructions using this reservation read their (D|Q)m operands at N1,
;; their (D|Q)d operands at N3, and produce a result at N6.
(define_insn_reservation "cortex_a9_neon_vsra_vrsra" 6
(and (eq_attr "tune" "cortexa9")
- (eq_attr "neon_type" "neon_vsra_vrsra"))
+ (eq_attr "type" "neon_vsra_vrsra"))
"cortex_a9_neon_dp")
;; Instructions using this reservation read their source operands at N2, and
;; produce a result at N5.
(define_insn_reservation "cortex_a9_neon_fp_vadd_ddd_vabs_dd" 5
(and (eq_attr "tune" "cortexa9")
- (eq_attr "neon_type" "neon_fp_vadd_ddd_vabs_dd"))
+ (eq_attr "type" "neon_fp_vadd_ddd_vabs_dd"))
"cortex_a9_neon_fadd")
;; Instructions using this reservation read their source operands at N2, and
;; produce a result at N5 on cycle 2.
(define_insn_reservation "cortex_a9_neon_fp_vadd_qqq_vabs_qq" 6
(and (eq_attr "tune" "cortexa9")
- (eq_attr "neon_type" "neon_fp_vadd_qqq_vabs_qq"))
+ (eq_attr "type" "neon_fp_vadd_qqq_vabs_qq"))
"cortex_a9_neon_fadd_2")
;; Instructions using this reservation read their source operands at N1, and
;; produce a result at N5.
(define_insn_reservation "cortex_a9_neon_fp_vsum" 5
(and (eq_attr "tune" "cortexa9")
- (eq_attr "neon_type" "neon_fp_vsum"))
+ (eq_attr "type" "neon_fp_vsum"))
"cortex_a9_neon_fadd")
;; Instructions using this reservation read their (D|Q)n operands at N2,
;; their (D|Q)m operands at N1, and produce a result at N5.
(define_insn_reservation "cortex_a9_neon_fp_vmul_ddd" 5
(and (eq_attr "tune" "cortexa9")
- (eq_attr "neon_type" "neon_fp_vmul_ddd"))
+ (eq_attr "type" "neon_fp_vmul_ddd"))
"cortex_a9_neon_dp")
;; Instructions using this reservation read their (D|Q)n operands at N2,
;; their (D|Q)m operands at N1, and produce a result at N5 on cycle 2.
(define_insn_reservation "cortex_a9_neon_fp_vmul_qqd" 6
(and (eq_attr "tune" "cortexa9")
- (eq_attr "neon_type" "neon_fp_vmul_qqd"))
+ (eq_attr "type" "neon_fp_vmul_qqd"))
"cortex_a9_neon_dp_2")
;; Instructions using this reservation read their (D|Q)n operands at N2,
;; produce a result at N9.
(define_insn_reservation "cortex_a9_neon_fp_vmla_ddd" 9
(and (eq_attr "tune" "cortexa9")
- (eq_attr "neon_type" "neon_fp_vmla_ddd"))
+ (eq_attr "type" "neon_fp_vmla_ddd"))
"cortex_a9_neon_fmul_then_fadd")
;; Instructions using this reservation read their (D|Q)n operands at N2,
;; produce a result at N9 on cycle 2.
(define_insn_reservation "cortex_a9_neon_fp_vmla_qqq" 10
(and (eq_attr "tune" "cortexa9")
- (eq_attr "neon_type" "neon_fp_vmla_qqq"))
+ (eq_attr "type" "neon_fp_vmla_qqq"))
"cortex_a9_neon_fmul_then_fadd_2")
;; Instructions using this reservation read their (D|Q)n operands at N2,
;; produce a result at N9.
(define_insn_reservation "cortex_a9_neon_fp_vmla_ddd_scalar" 9
(and (eq_attr "tune" "cortexa9")
- (eq_attr "neon_type" "neon_fp_vmla_ddd_scalar"))
+ (eq_attr "type" "neon_fp_vmla_ddd_scalar"))
"cortex_a9_neon_fmul_then_fadd")
;; Instructions using this reservation read their (D|Q)n operands at N2,
;; produce a result at N9 on cycle 2.
(define_insn_reservation "cortex_a9_neon_fp_vmla_qqq_scalar" 10
(and (eq_attr "tune" "cortexa9")
- (eq_attr "neon_type" "neon_fp_vmla_qqq_scalar"))
+ (eq_attr "type" "neon_fp_vmla_qqq_scalar"))
"cortex_a9_neon_fmul_then_fadd_2")
;; Instructions using this reservation read their source operands at N2, and
;; produce a result at N9.
(define_insn_reservation "cortex_a9_neon_fp_vrecps_vrsqrts_ddd" 9
(and (eq_attr "tune" "cortexa9")
- (eq_attr "neon_type" "neon_fp_vrecps_vrsqrts_ddd"))
+ (eq_attr "type" "neon_fp_vrecps_vrsqrts_ddd"))
"cortex_a9_neon_fmul_then_fadd")
;; Instructions using this reservation read their source operands at N2, and
;; produce a result at N9 on cycle 2.
(define_insn_reservation "cortex_a9_neon_fp_vrecps_vrsqrts_qqq" 10
(and (eq_attr "tune" "cortexa9")
- (eq_attr "neon_type" "neon_fp_vrecps_vrsqrts_qqq"))
+ (eq_attr "type" "neon_fp_vrecps_vrsqrts_qqq"))
"cortex_a9_neon_fmul_then_fadd_2")
;; Instructions using this reservation read their source operands at N1, and
;; produce a result at N2.
(define_insn_reservation "cortex_a9_neon_bp_simple" 2
(and (eq_attr "tune" "cortexa9")
- (eq_attr "neon_type" "neon_bp_simple"))
+ (eq_attr "type" "neon_bp_simple"))
"cortex_a9_neon_perm")
;; Instructions using this reservation read their source operands at N1, and
;; produce a result at N2 on cycle 2.
(define_insn_reservation "cortex_a9_neon_bp_2cycle" 3
(and (eq_attr "tune" "cortexa9")
- (eq_attr "neon_type" "neon_bp_2cycle"))
+ (eq_attr "type" "neon_bp_2cycle"))
"cortex_a9_neon_perm_2")
;; Instructions using this reservation read their source operands at N1, and
;; produce a result at N2 on cycle 3.
(define_insn_reservation "cortex_a9_neon_bp_3cycle" 4
(and (eq_attr "tune" "cortexa9")
- (eq_attr "neon_type" "neon_bp_3cycle"))
+ (eq_attr "type" "neon_bp_3cycle"))
"cortex_a9_neon_perm_3")
;; Instructions using this reservation produce a result at N1.
(define_insn_reservation "cortex_a9_neon_ldr" 1
(and (eq_attr "tune" "cortexa9")
- (eq_attr "neon_type" "neon_ldr"))
+ (eq_attr "type" "neon_ldr"))
"cortex_a9_neon_ls")
;; Instructions using this reservation read their source operands at N1.
(define_insn_reservation "cortex_a9_neon_str" 0
(and (eq_attr "tune" "cortexa9")
- (eq_attr "neon_type" "neon_str"))
+ (eq_attr "type" "neon_str"))
"cortex_a9_neon_ls")
;; Instructions using this reservation produce a result at N1 on cycle 2.
(define_insn_reservation "cortex_a9_neon_vld1_1_2_regs" 2
(and (eq_attr "tune" "cortexa9")
- (eq_attr "neon_type" "neon_vld1_1_2_regs"))
+ (eq_attr "type" "neon_vld1_1_2_regs"))
"cortex_a9_neon_ls_2")
;; Instructions using this reservation produce a result at N1 on cycle 3.
(define_insn_reservation "cortex_a9_neon_vld1_3_4_regs" 3
(and (eq_attr "tune" "cortexa9")
- (eq_attr "neon_type" "neon_vld1_3_4_regs"))
+ (eq_attr "type" "neon_vld1_3_4_regs"))
"cortex_a9_neon_ls_3")
;; Instructions using this reservation produce a result at N2 on cycle 2.
(define_insn_reservation "cortex_a9_neon_vld2_2_regs_vld1_vld2_all_lanes" 3
(and (eq_attr "tune" "cortexa9")
- (eq_attr "neon_type" "neon_vld2_2_regs_vld1_vld2_all_lanes"))
+ (eq_attr "type" "neon_vld2_2_regs_vld1_vld2_all_lanes"))
"cortex_a9_neon_ls_2")
;; Instructions using this reservation produce a result at N2 on cycle 3.
(define_insn_reservation "cortex_a9_neon_vld2_4_regs" 4
(and (eq_attr "tune" "cortexa9")
- (eq_attr "neon_type" "neon_vld2_4_regs"))
+ (eq_attr "type" "neon_vld2_4_regs"))
"cortex_a9_neon_ls_3")
;; Instructions using this reservation produce a result at N2 on cycle 4.
(define_insn_reservation "cortex_a9_neon_vld3_vld4" 5
(and (eq_attr "tune" "cortexa9")
- (eq_attr "neon_type" "neon_vld3_vld4"))
+ (eq_attr "type" "neon_vld3_vld4"))
"cortex_a9_neon_ls_4")
;; Instructions using this reservation read their source operands at N1.
(define_insn_reservation "cortex_a9_neon_vst1_1_2_regs_vst2_2_regs" 0
(and (eq_attr "tune" "cortexa9")
- (eq_attr "neon_type" "neon_vst1_1_2_regs_vst2_2_regs"))
+ (eq_attr "type" "neon_vst1_1_2_regs_vst2_2_regs"))
"cortex_a9_neon_ls_2")
;; Instructions using this reservation read their source operands at N1.
(define_insn_reservation "cortex_a9_neon_vst1_3_4_regs" 0
(and (eq_attr "tune" "cortexa9")
- (eq_attr "neon_type" "neon_vst1_3_4_regs"))
+ (eq_attr "type" "neon_vst1_3_4_regs"))
"cortex_a9_neon_ls_3")
;; Instructions using this reservation read their source operands at N1.
(define_insn_reservation "cortex_a9_neon_vst2_4_regs_vst3_vst4" 0
(and (eq_attr "tune" "cortexa9")
- (eq_attr "neon_type" "neon_vst2_4_regs_vst3_vst4"))
+ (eq_attr "type" "neon_vst2_4_regs_vst3_vst4"))
"cortex_a9_neon_ls_4")
;; Instructions using this reservation read their source operands at N1.
(define_insn_reservation "cortex_a9_neon_vst3_vst4" 0
(and (eq_attr "tune" "cortexa9")
- (eq_attr "neon_type" "neon_vst3_vst4"))
+ (eq_attr "type" "neon_vst3_vst4"))
"cortex_a9_neon_ls_4")
;; Instructions using this reservation read their source operands at N1, and
;; produce a result at N2 on cycle 3.
(define_insn_reservation "cortex_a9_neon_vld1_vld2_lane" 4
(and (eq_attr "tune" "cortexa9")
- (eq_attr "neon_type" "neon_vld1_vld2_lane"))
+ (eq_attr "type" "neon_vld1_vld2_lane"))
"cortex_a9_neon_ls_3")
;; Instructions using this reservation read their source operands at N1, and
;; produce a result at N2 on cycle 5.
(define_insn_reservation "cortex_a9_neon_vld3_vld4_lane" 6
(and (eq_attr "tune" "cortexa9")
- (eq_attr "neon_type" "neon_vld3_vld4_lane"))
+ (eq_attr "type" "neon_vld3_vld4_lane"))
"cortex_a9_neon_ls_5")
;; Instructions using this reservation read their source operands at N1.
(define_insn_reservation "cortex_a9_neon_vst1_vst2_lane" 0
(and (eq_attr "tune" "cortexa9")
- (eq_attr "neon_type" "neon_vst1_vst2_lane"))
+ (eq_attr "type" "neon_vst1_vst2_lane"))
"cortex_a9_neon_ls_2")
;; Instructions using this reservation read their source operands at N1.
(define_insn_reservation "cortex_a9_neon_vst3_vst4_lane" 0
(and (eq_attr "tune" "cortexa9")
- (eq_attr "neon_type" "neon_vst3_vst4_lane"))
+ (eq_attr "type" "neon_vst3_vst4_lane"))
"cortex_a9_neon_ls_3")
;; Instructions using this reservation produce a result at N2 on cycle 2.
(define_insn_reservation "cortex_a9_neon_vld3_vld4_all_lanes" 3
(and (eq_attr "tune" "cortexa9")
- (eq_attr "neon_type" "neon_vld3_vld4_all_lanes"))
+ (eq_attr "type" "neon_vld3_vld4_all_lanes"))
"cortex_a9_neon_ls_3")
;; Instructions using this reservation produce a result at N2.
(define_insn_reservation "cortex_a9_neon_mcr" 2
(and (eq_attr "tune" "cortexa9")
- (eq_attr "neon_type" "neon_mcr"))
+ (eq_attr "type" "neon_mcr"))
"cortex_a9_neon_perm")
;; Instructions using this reservation produce a result at N2.
(define_insn_reservation "cortex_a9_neon_mcr_2_mcrr" 2
(and (eq_attr "tune" "cortexa9")
- (eq_attr "neon_type" "neon_mcr_2_mcrr"))
+ (eq_attr "type" "neon_mcr_2_mcrr"))
"cortex_a9_neon_perm_2")
;; Exceptions to the default latencies.
;; which can go down E2 without any problem.
(define_insn_reservation "cortex_a9_dp" 2
(and (eq_attr "tune" "cortexa9")
- (and (eq_attr "type" "arlo_imm,arlo_reg,shift,shift_reg,\
- mov_imm,mov_reg,mvn_imm,mvn_reg,\
- mov_shift_reg,mov_shift")
- (eq_attr "neon_type" "none")))
+ (eq_attr "type" "arlo_imm,arlo_reg,shift,shift_reg,\
+ mov_imm,mov_reg,mvn_imm,mvn_reg,\
+ mov_shift_reg,mov_shift"))
"cortex_a9_p0_default|cortex_a9_p1_default")
;; An instruction using the shifter will go down E1.
;; Pipelining for VFP instructions.
;; Issue happens either along load store unit or the VFP / Neon unit.
;; Pipeline Instruction Classification.
-;; FPS - fcpys, ffariths, ffarithd,r_2_f,f_2_r
+;; FPS - fcpys, ffariths, ffarithd,f_mcr,f_mcrr,f_mrc,f_mrrc
;; FP_ADD - fadds, faddd, fcmps (1)
;; FPMUL - fmul{s,d}, fmac{s,d}, ffma{s,d}
;; FPDIV - fdiv{s,d}
;; fmrs, fmrrd, fmstat and fmrx - The data is available after 1 cycle.
(define_insn_reservation "cortex_a9_fps" 2
(and (eq_attr "tune" "cortexa9")
- (eq_attr "type" "fcpys, fconsts, fconstd, ffariths, ffarithd, r_2_f, f_2_r, f_flag"))
+ (eq_attr "type" "fcpys, fconsts, fconstd, ffariths, ffarithd,\
+ f_mcr, f_mcrr, f_mrc, f_mrrc, f_flag"))
"ca9_issue_vfp_neon + ca9fps")
(define_bypass 1
(define_insn_reservation "cortex_m4_vmov_2" 2
(and (eq_attr "tune" "cortexm4")
- (eq_attr "type" "f_2_r,r_2_f"))
+ (eq_attr "type" "f_mrc,f_mrrc,f_mcr,f_mcrr"))
"cortex_m4_ex_v*2")
(define_insn_reservation "cortex_m4_fmuls" 2
(define_insn_reservation "cortex_r4_mcr" 2
(and (eq_attr "tune_cortexr4" "yes")
- (eq_attr "type" "r_2_f"))
+ (eq_attr "type" "f_mcr,f_mcrr"))
"cortex_r4_issue_ab")
(define_insn_reservation "cortex_r4_mrc" 3
(and (eq_attr "tune_cortexr4" "yes")
- (eq_attr "type" "f_2_r"))
+ (eq_attr "type" "f_mrc,f_mrrc"))
"cortex_r4_issue_ab")
;; Bypasses for normal (not early) regs.
(define_mode_attr scalar_mul_constraint [(V4HI "x") (V2SI "t") (V2SF "t")
(V8HI "x") (V4SI "t") (V4SF "t")])
-;; Predicates used for setting neon_type
+;; Predicates used for setting type for neon instructions
(define_mode_attr Is_float_mode [(V8QI "false") (V16QI "false")
(V4HI "false") (V8HI "false")
(const_int 8)
(const_int 4))]
(const_int 4)))
- (set_attr "type" "*,*,*,load2,store2,wmmx_wmov,wmmx_tmcrr,wmmx_tmrrc,wmmx_wldr,wmmx_wstr,r_2_f,f_2_r,ffarithd,f_loadd,f_stored")
+ (set_attr "type" "*,*,*,load2,store2,*,*,*,*,*,f_mcrr,f_mrrc,\
+ ffarithd,f_loadd,f_stored")
(set_attr "arm_pool_range" "*,*,*,1020,*,*,*,*,*,*,*,*,*,1020,*")
(set_attr "arm_neg_pool_range" "*,*,*,1008,*,*,*,*,*,*,*,*,*,1008,*")]
)
default:
gcc_unreachable ();
}"
- [(set_attr "type" "*,*,*,*,load1,store1,wmmx_tmcr,wmmx_tmrc,wmmx_wldr,wmmx_wstr,r_2_f,f_2_r,fcpys,f_loads,f_stores")
+ [(set_attr "type" "*,*,*,*,load1,store1,*,*,*,*,f_mcr,f_mrc,\
+ fcpys,f_loads,f_stores")
(set_attr "length" "*,*,*,*,*, *,*,*, 16, *,*,*,*,*,*")
(set_attr "pool_range" "*,*,*,*,4096, *,*,*,1024, *,*,*,*,1020,*")
(set_attr "neg_pool_range" "*,*,*,*,4084, *,*,*, *, 1012,*,*,*,1008,*")
(define_insn_reservation "pj4_vfp_to_core" 7
(and (eq_attr "tune" "marvell_pj4")
- (eq_attr "type" "f_2_r,f_flag")) "pj4_isb,nothing,nothing,vissue,vfast,nothing*2")
+ (eq_attr "type" "f_mrc,f_mrrc,f_flag")) "pj4_isb,nothing,nothing,vissue,vfast,nothing*2")
(define_insn_reservation "pj4_core_to_vfp" 2
(and (eq_attr "tune" "marvell_pj4")
- (eq_attr "type" "r_2_f")) "pj4_isb,pj4_alu1,pj4_w1,vissue,pj4_cp")
+ (eq_attr "type" "f_mcr,f_mcrr")) "pj4_isb,pj4_alu1,pj4_w1,vissue,pj4_cp")
Printf.printf "(define_insn_reservation \"%s_%s\" %d\n"
corestring producer latency;
Printf.printf " (and (eq_attr \"tune\" \"%s\")\n" tunestring;
- Printf.printf " (eq_attr \"neon_type\" \"%s\"))\n" producer;
+ Printf.printf " (eq_attr \"type\" \"%s\"))\n" producer;
let str =
match reservation with
Mul -> "dp" | Mul_2cycle -> "dp_2" | Mul_4cycle -> "dp_4"
;; Attribute used to permit string comparisons against <VQH_mnem> in
-;; neon_type attribute definitions.
+;; type attribute definitions.
(define_attr "vqh_mnem" "vadd,vmin,vmax" (const_string "vadd"))
(define_insn "*neon_mov<mode>"
default: return output_move_double (operands, true, NULL);
}
}
- [(set_attr "neon_type" "neon_int_1,*,neon_vmov,*,neon_mrrc,neon_mcr_2_mcrr,*,*,*")
- (set_attr "type" "*,f_stored,*,f_loadd,*,*,mov_reg,load2,store2")
+ [(set_attr "type" "neon_int_1,f_stored,neon_vmov,f_loadd,neon_mrrc,\
+ neon_mcr_2_mcrr,mov_reg,load2,store2")
(set_attr "length" "4,4,4,4,4,4,8,8,8")
(set_attr "arm_pool_range" "*,*,*,1020,*,*,*,1020,*")
(set_attr "thumb2_pool_range" "*,*,*,1018,*,*,*,1018,*")
default: return output_move_quad (operands);
}
}
- [(set_attr "neon_type" "neon_int_1,neon_stm_2,neon_vmov,neon_ldm_2,\
- neon_mrrc,neon_mcr_2_mcrr,*,*,*")
- (set_attr "type" "*,*,*,*,*,*,mov_reg,load4,store4")
+ [(set_attr "type" "neon_int_1,neon_stm_2,neon_vmov,neon_ldm_2,\
+ neon_mrrc,neon_mcr_2_mcrr,mov_reg,load4,store4")
(set_attr "length" "4,8,4,8,8,8,16,8,16")
(set_attr "arm_pool_range" "*,*,*,1020,*,*,*,1020,*")
(set_attr "thumb2_pool_range" "*,*,*,1018,*,*,*,1018,*")
default: gcc_unreachable ();
}
}
- [(set_attr "neon_type" "neon_int_1,neon_stm_2,neon_ldm_2")
+ [(set_attr "type" "neon_int_1,neon_stm_2,neon_ldm_2")
(set (attr "length") (symbol_ref "arm_attr_length_move_neon (insn)"))])
(define_split
UNSPEC_MISALIGNED_ACCESS))]
"TARGET_NEON && !BYTES_BIG_ENDIAN && unaligned_access"
"vst1.<V_sz_elem>\t{%P1}, %A0"
- [(set_attr "neon_type" "neon_vst1_1_2_regs_vst2_2_regs")])
+ [(set_attr "type" "neon_vst1_1_2_regs_vst2_2_regs")])
(define_insn "*movmisalign<mode>_neon_load"
[(set (match_operand:VDX 0 "s_register_operand" "=w")
UNSPEC_MISALIGNED_ACCESS))]
"TARGET_NEON && !BYTES_BIG_ENDIAN && unaligned_access"
"vld1.<V_sz_elem>\t{%P0}, %A1"
- [(set_attr "neon_type" "neon_vld1_1_2_regs")])
+ [(set_attr "type" "neon_vld1_1_2_regs")])
(define_insn "*movmisalign<mode>_neon_store"
[(set (match_operand:VQX 0 "neon_permissive_struct_operand" "=Um")
UNSPEC_MISALIGNED_ACCESS))]
"TARGET_NEON && !BYTES_BIG_ENDIAN && unaligned_access"
"vst1.<V_sz_elem>\t{%q1}, %A0"
- [(set_attr "neon_type" "neon_vst1_1_2_regs_vst2_2_regs")])
+ [(set_attr "type" "neon_vst1_1_2_regs_vst2_2_regs")])
(define_insn "*movmisalign<mode>_neon_load"
[(set (match_operand:VQX 0 "s_register_operand" "=w")
UNSPEC_MISALIGNED_ACCESS))]
"TARGET_NEON && !BYTES_BIG_ENDIAN && unaligned_access"
"vld1.<V_sz_elem>\t{%q0}, %A1"
- [(set_attr "neon_type" "neon_vld1_1_2_regs")])
+ [(set_attr "type" "neon_vld1_1_2_regs")])
(define_insn "vec_set<mode>_internal"
[(set (match_operand:VD 0 "s_register_operand" "=w,w")
else
return "vmov.<V_sz_elem>\t%P0[%c2], %1";
}
- [(set_attr "neon_type" "neon_vld1_vld2_lane,neon_mcr")])
+ [(set_attr "type" "neon_vld1_vld2_lane,neon_mcr")])
(define_insn "vec_set<mode>_internal"
[(set (match_operand:VQ 0 "s_register_operand" "=w,w")
else
return "vmov.<V_sz_elem>\t%P0[%c2], %1";
}
- [(set_attr "neon_type" "neon_vld1_vld2_lane,neon_mcr")]
+ [(set_attr "type" "neon_vld1_vld2_lane,neon_mcr")]
)
(define_insn "vec_setv2di_internal"
else
return "vmov\t%P0, %Q1, %R1";
}
- [(set_attr "neon_type" "neon_vld1_1_2_regs,neon_mcr_2_mcrr")]
+ [(set_attr "type" "neon_vld1_1_2_regs,neon_mcr_2_mcrr")]
)
(define_expand "vec_set<mode>"
else
return "vmov.<V_uf_sclr>\t%0, %P1[%c2]";
}
- [(set_attr "neon_type" "neon_vst1_vst2_lane,neon_bp_simple")]
+ [(set_attr "type" "neon_vst1_vst2_lane,neon_bp_simple")]
)
(define_insn "vec_extract<mode>"
else
return "vmov.<V_uf_sclr>\t%0, %P1[%c2]";
}
- [(set_attr "neon_type" "neon_vst1_vst2_lane,neon_bp_simple")]
+ [(set_attr "type" "neon_vst1_vst2_lane,neon_bp_simple")]
)
(define_insn "vec_extractv2di"
else
return "vmov\t%Q0, %R0, %P1 @ v2di";
}
- [(set_attr "neon_type" "neon_vst1_vst2_lane,neon_int_1")]
+ [(set_attr "type" "neon_vst1_vst2_lane,neon_int_1")]
)
(define_expand "vec_init<mode>"
(match_operand:VDQ 2 "s_register_operand" "w")))]
"TARGET_NEON && (!<Is_float_mode> || flag_unsafe_math_optimizations)"
"vadd.<V_if_elem>\t%<V_reg>0, %<V_reg>1, %<V_reg>2"
- [(set (attr "neon_type")
+ [(set (attr "type")
(if_then_else (match_test "<Is_float_mode>")
(if_then_else (match_test "<Is_d_reg>")
(const_string "neon_fp_vadd_ddd_vabs_dd")
default: gcc_unreachable ();
}
}
- [(set_attr "neon_type" "neon_int_1,*,*,neon_int_1,*,*,*")
+ [(set_attr "type" "neon_int_1,*,*,neon_int_1,*,*,*")
(set_attr "conds" "*,clob,clob,*,clob,clob,clob")
(set_attr "length" "*,8,8,*,8,8,8")
(set_attr "arch" "neon_for_64bits,*,*,avoid_neon_for_64bits,*,*,*")]
(match_operand:VDQ 2 "s_register_operand" "w")))]
"TARGET_NEON && (!<Is_float_mode> || flag_unsafe_math_optimizations)"
"vsub.<V_if_elem>\t%<V_reg>0, %<V_reg>1, %<V_reg>2"
- [(set (attr "neon_type")
+ [(set (attr "type")
(if_then_else (match_test "<Is_float_mode>")
(if_then_else (match_test "<Is_d_reg>")
(const_string "neon_fp_vadd_ddd_vabs_dd")
default: gcc_unreachable ();
}
}
- [(set_attr "neon_type" "neon_int_2,*,*,*,neon_int_2")
+ [(set_attr "type" "neon_int_2,*,*,*,neon_int_2")
(set_attr "conds" "*,clob,clob,clob,*")
(set_attr "length" "*,8,8,8,*")
(set_attr "arch" "neon_for_64bits,*,*,*,avoid_neon_for_64bits")]
(match_operand:VDQ 2 "s_register_operand" "w")))]
"TARGET_NEON && (!<Is_float_mode> || flag_unsafe_math_optimizations)"
"vmul.<V_if_elem>\t%<V_reg>0, %<V_reg>1, %<V_reg>2"
- [(set (attr "neon_type")
+ [(set (attr "type")
(if_then_else (match_test "<Is_float_mode>")
(if_then_else (match_test "<Is_d_reg>")
(const_string "neon_fp_vadd_ddd_vabs_dd")
(match_operand:VDQ 1 "s_register_operand" "0")))]
"TARGET_NEON && (!<Is_float_mode> || flag_unsafe_math_optimizations)"
"vmla.<V_if_elem>\t%<V_reg>0, %<V_reg>2, %<V_reg>3"
- [(set (attr "neon_type")
+ [(set (attr "type")
(if_then_else (match_test "<Is_float_mode>")
(if_then_else (match_test "<Is_d_reg>")
(const_string "neon_fp_vmla_ddd")
(match_operand:VDQ 3 "s_register_operand" "w"))))]
"TARGET_NEON && (!<Is_float_mode> || flag_unsafe_math_optimizations)"
"vmls.<V_if_elem>\t%<V_reg>0, %<V_reg>2, %<V_reg>3"
- [(set (attr "neon_type")
+ [(set (attr "type")
(if_then_else (match_test "<Is_float_mode>")
(if_then_else (match_test "<Is_d_reg>")
(const_string "neon_fp_vmla_ddd")
(match_operand:VCVTF 3 "register_operand" "0")))]
"TARGET_NEON && TARGET_FMA && flag_unsafe_math_optimizations"
"vfma%?.<V_if_elem>\\t%<V_reg>0, %<V_reg>1, %<V_reg>2"
- [(set (attr "neon_type")
+ [(set (attr "type")
(if_then_else (match_test "<Is_d_reg>")
(const_string "neon_fp_vmla_ddd")
(const_string "neon_fp_vmla_qqq")))]
(match_operand:VCVTF 3 "register_operand" "0")))]
"TARGET_NEON && TARGET_FMA"
"vfma%?.<V_if_elem>\\t%<V_reg>0, %<V_reg>1, %<V_reg>2"
- [(set (attr "neon_type")
+ [(set (attr "type")
(if_then_else (match_test "<Is_d_reg>")
(const_string "neon_fp_vmla_ddd")
(const_string "neon_fp_vmla_qqq")))]
(match_operand:VCVTF 3 "register_operand" "0")))]
"TARGET_NEON && TARGET_FMA && flag_unsafe_math_optimizations"
"vfms%?.<V_if_elem>\\t%<V_reg>0, %<V_reg>1, %<V_reg>2"
- [(set (attr "neon_type")
+ [(set (attr "type")
(if_then_else (match_test "<Is_d_reg>")
(const_string "neon_fp_vmla_ddd")
(const_string "neon_fp_vmla_qqq")))]
(match_operand:VCVTF 3 "register_operand" "0")))]
"TARGET_NEON && TARGET_FMA"
"vfms%?.<V_if_elem>\\t%<V_reg>0, %<V_reg>1, %<V_reg>2"
- [(set (attr "neon_type")
+ [(set (attr "type")
(if_then_else (match_test "<Is_d_reg>")
(const_string "neon_fp_vmla_ddd")
(const_string "neon_fp_vmla_qqq")))]
NEON_VRINT))]
"TARGET_NEON && TARGET_FPU_ARMV8"
"vrint<nvrint_variant>%?.f32\\t%<V_reg>0, %<V_reg>1"
- [(set (attr "neon_type")
+ [(set (attr "type")
(if_then_else (match_test "<Is_d_reg>")
(const_string "neon_fp_vadd_ddd_vabs_dd")
(const_string "neon_fp_vadd_qqq_vabs_qq")))]
default: gcc_unreachable ();
}
}
- [(set_attr "neon_type" "neon_int_1")]
+ [(set_attr "type" "neon_int_1")]
)
;; The concrete forms of the Neon immediate-logic instructions are vbic and
default: gcc_unreachable ();
}
}
- [(set_attr "neon_type" "neon_int_1")]
+ [(set_attr "type" "neon_int_1")]
)
(define_insn "orn<mode>3_neon"
(match_operand:VDQ 1 "s_register_operand" "w")))]
"TARGET_NEON"
"vorn\t%<V_reg>0, %<V_reg>1, %<V_reg>2"
- [(set_attr "neon_type" "neon_int_1")]
+ [(set_attr "type" "neon_int_1")]
)
;; TODO: investigate whether we should disable
DONE;
}
}"
- [(set_attr "neon_type" "neon_int_1,*,*,*")
+ [(set_attr "type" "neon_int_1,*,*,*")
(set_attr "length" "*,16,8,8")
(set_attr "arch" "any,a,t2,t2")]
)
(match_operand:VDQ 1 "s_register_operand" "w")))]
"TARGET_NEON"
"vbic\t%<V_reg>0, %<V_reg>1, %<V_reg>2"
- [(set_attr "neon_type" "neon_int_1")]
+ [(set_attr "type" "neon_int_1")]
)
;; Compare to *anddi_notdi_di.
vbic\t%P0, %P1, %P2
#
#"
- [(set_attr "neon_type" "neon_int_1,*,*")
+ [(set_attr "type" "neon_int_1,*,*")
(set_attr "length" "*,8,8")]
)
(match_operand:VDQ 2 "s_register_operand" "w")))]
"TARGET_NEON"
"veor\t%<V_reg>0, %<V_reg>1, %<V_reg>2"
- [(set_attr "neon_type" "neon_int_1")]
+ [(set_attr "type" "neon_int_1")]
)
(define_insn "one_cmpl<mode>2"
(not:VDQ (match_operand:VDQ 1 "s_register_operand" "w")))]
"TARGET_NEON"
"vmvn\t%<V_reg>0, %<V_reg>1"
- [(set_attr "neon_type" "neon_int_1")]
+ [(set_attr "type" "neon_int_1")]
)
(define_insn "abs<mode>2"
(abs:VDQW (match_operand:VDQW 1 "s_register_operand" "w")))]
"TARGET_NEON"
"vabs.<V_s_elem>\t%<V_reg>0, %<V_reg>1"
- [(set (attr "neon_type")
+ [(set (attr "type")
(if_then_else (match_test "<Is_float_mode>")
(if_then_else (match_test "<Is_d_reg>")
(const_string "neon_fp_vadd_ddd_vabs_dd")
(neg:VDQW (match_operand:VDQW 1 "s_register_operand" "w")))]
"TARGET_NEON"
"vneg.<V_s_elem>\t%<V_reg>0, %<V_reg>1"
- [(set (attr "neon_type")
+ [(set (attr "type")
(if_then_else (match_test "<Is_float_mode>")
(if_then_else (match_test "<Is_d_reg>")
(const_string "neon_fp_vadd_ddd_vabs_dd")
(match_operand:VDQIW 2 "s_register_operand" "w")))]
"TARGET_NEON"
"vmin.<V_u_elem>\t%<V_reg>0, %<V_reg>1, %<V_reg>2"
- [(set_attr "neon_type" "neon_int_5")]
+ [(set_attr "type" "neon_int_5")]
)
(define_insn "*umax<mode>3_neon"
(match_operand:VDQIW 2 "s_register_operand" "w")))]
"TARGET_NEON"
"vmax.<V_u_elem>\t%<V_reg>0, %<V_reg>1, %<V_reg>2"
- [(set_attr "neon_type" "neon_int_5")]
+ [(set_attr "type" "neon_int_5")]
)
(define_insn "*smin<mode>3_neon"
(match_operand:VDQW 2 "s_register_operand" "w")))]
"TARGET_NEON"
"vmin.<V_s_elem>\t%<V_reg>0, %<V_reg>1, %<V_reg>2"
- [(set (attr "neon_type")
+ [(set (attr "type")
(if_then_else (match_test "<Is_float_mode>")
(const_string "neon_fp_vadd_ddd_vabs_dd")
(const_string "neon_int_5")))]
(match_operand:VDQW 2 "s_register_operand" "w")))]
"TARGET_NEON"
"vmax.<V_s_elem>\t%<V_reg>0, %<V_reg>1, %<V_reg>2"
- [(set (attr "neon_type")
+ [(set (attr "type")
(if_then_else (match_test "<Is_float_mode>")
(const_string "neon_fp_vadd_ddd_vabs_dd")
(const_string "neon_int_5")))]
default: gcc_unreachable ();
}
}
- [(set (attr "neon_type")
+ [(set (attr "type")
(if_then_else (match_test "<Is_d_reg>")
(const_string "neon_vshl_ddd")
(const_string "neon_shift_3")))]
<MODE>mode, VALID_NEON_QREG_MODE (<MODE>mode),
false);
}
- [(set (attr "neon_type")
+ [(set (attr "type")
(if_then_else (match_test "<Is_d_reg>")
(const_string "neon_vshl_ddd")
(const_string "neon_shift_3")))]
<MODE>mode, VALID_NEON_QREG_MODE (<MODE>mode),
false);
}
- [(set (attr "neon_type")
+ [(set (attr "type")
(if_then_else (match_test "<Is_d_reg>")
(const_string "neon_vshl_ddd")
(const_string "neon_shift_3")))]
UNSPEC_ASHIFT_SIGNED))]
"TARGET_NEON"
"vshl.<V_s_elem>\t%<V_reg>0, %<V_reg>1, %<V_reg>2"
- [(set (attr "neon_type")
+ [(set (attr "type")
(if_then_else (match_test "<Is_d_reg>")
(const_string "neon_vshl_ddd")
(const_string "neon_shift_3")))]
UNSPEC_ASHIFT_UNSIGNED))]
"TARGET_NEON"
"vshl.<V_u_elem>\t%<V_reg>0, %<V_reg>1, %<V_reg>2"
- [(set (attr "neon_type")
+ [(set (attr "type")
(if_then_else (match_test "<Is_d_reg>")
(const_string "neon_vshl_ddd")
(const_string "neon_shift_3")))]
"@
vld1.32\t{%P0[0]}, %A1
vmov.32\t%P0[0], %1"
- [(set_attr "neon_type" "neon_vld1_vld2_lane,neon_mcr")]
+ [(set_attr "type" "neon_vld1_vld2_lane,neon_mcr")]
)
(define_insn "ashldi3_neon_noclobber"
"@
vshl.u64\t%P0, %P1, %2
vshl.u64\t%P0, %P1, %P2"
- [(set_attr "neon_type" "neon_vshl_ddd,neon_vshl_ddd")]
+ [(set_attr "type" "neon_vshl_ddd,neon_vshl_ddd")]
)
(define_insn_and_split "ashldi3_neon"
UNSPEC_ASHIFT_SIGNED))]
"TARGET_NEON && reload_completed"
"vshl.s64\t%P0, %P1, %P2"
- [(set_attr "neon_type" "neon_vshl_ddd")]
+ [(set_attr "type" "neon_vshl_ddd")]
)
; The shift amount needs to be negated for right-shifts
UNSPEC_ASHIFT_UNSIGNED))]
"TARGET_NEON && reload_completed"
"vshl.u64\t%P0, %P1, %P2"
- [(set_attr "neon_type" "neon_vshl_ddd")]
+ [(set_attr "type" "neon_vshl_ddd")]
)
(define_insn "ashrdi3_neon_imm_noclobber"
"TARGET_NEON && reload_completed
&& INTVAL (operands[2]) > 0 && INTVAL (operands[2]) <= 64"
"vshr.s64\t%P0, %P1, %2"
- [(set_attr "neon_type" "neon_vshl_ddd")]
+ [(set_attr "type" "neon_vshl_ddd")]
)
(define_insn "lshrdi3_neon_imm_noclobber"
"TARGET_NEON && reload_completed
&& INTVAL (operands[2]) > 0 && INTVAL (operands[2]) <= 64"
"vshr.u64\t%P0, %P1, %2"
- [(set_attr "neon_type" "neon_vshl_ddd")]
+ [(set_attr "type" "neon_vshl_ddd")]
)
;; ashrdi3_neon
(match_operand:<V_widen> 2 "s_register_operand" "w")))]
"TARGET_NEON"
"vaddw.<V_s_elem>\t%q0, %q2, %P1"
- [(set_attr "neon_type" "neon_int_3")]
+ [(set_attr "type" "neon_int_3")]
)
(define_insn "widen_usum<mode>3"
(match_operand:<V_widen> 2 "s_register_operand" "w")))]
"TARGET_NEON"
"vaddw.<V_u_elem>\t%q0, %q2, %P1"
- [(set_attr "neon_type" "neon_int_3")]
+ [(set_attr "type" "neon_int_3")]
)
;; VEXT can be used to synthesize coarse whole-vector shifts with 8-bit
"TARGET_NEON"
"<VQH_mnem>.<VQH_sign>32\t%P0, %e1, %f1"
[(set_attr "vqh_mnem" "<VQH_mnem>")
- (set (attr "neon_type")
+ (set (attr "type")
(if_then_else (eq_attr "vqh_mnem" "vadd")
(const_string "neon_int_1") (const_string "neon_int_5")))]
)
"TARGET_NEON && flag_unsafe_math_optimizations"
"<VQH_mnem>.f32\t%P0, %e1, %f1"
[(set_attr "vqh_mnem" "<VQH_mnem>")
- (set (attr "neon_type")
+ (set (attr "type")
(if_then_else (eq_attr "vqh_mnem" "vadd")
(const_string "neon_int_1") (const_string "neon_int_5")))]
)
"TARGET_NEON"
"<VQH_mnem>.<VQH_sign>16\t%P0, %e1, %f1"
[(set_attr "vqh_mnem" "<VQH_mnem>")
- (set (attr "neon_type")
+ (set (attr "type")
(if_then_else (eq_attr "vqh_mnem" "vadd")
(const_string "neon_int_1") (const_string "neon_int_5")))]
)
"TARGET_NEON"
"<VQH_mnem>.<VQH_sign>8\t%P0, %e1, %f1"
[(set_attr "vqh_mnem" "<VQH_mnem>")
- (set (attr "neon_type")
+ (set (attr "type")
(if_then_else (eq_attr "vqh_mnem" "vadd")
(const_string "neon_int_1") (const_string "neon_int_5")))]
)
UNSPEC_VPADD))]
"TARGET_NEON && !BYTES_BIG_ENDIAN"
"vadd.i64\t%e0, %e1, %f1"
- [(set_attr "neon_type" "neon_int_1")]
+ [(set_attr "type" "neon_int_1")]
)
;; NEON does not distinguish between signed and unsigned addition except on
"TARGET_NEON"
"vpadd.<V_if_elem>\t%P0, %P1, %P2"
;; Assume this schedules like vadd.
- [(set (attr "neon_type")
+ [(set (attr "type")
(if_then_else (match_test "<Is_float_mode>")
(if_then_else (match_test "<Is_d_reg>")
(const_string "neon_fp_vadd_ddd_vabs_dd")
"TARGET_NEON"
"vpmin.<V_s_elem>\t%P0, %P1, %P2"
;; Assume this schedules like vmin.
- [(set (attr "neon_type")
+ [(set (attr "type")
(if_then_else (match_test "<Is_float_mode>")
(const_string "neon_fp_vadd_ddd_vabs_dd")
(const_string "neon_int_5")))]
"TARGET_NEON"
"vpmax.<V_s_elem>\t%P0, %P1, %P2"
;; Assume this schedules like vmax.
- [(set (attr "neon_type")
+ [(set (attr "type")
(if_then_else (match_test "<Is_float_mode>")
(const_string "neon_fp_vadd_ddd_vabs_dd")
(const_string "neon_int_5")))]
"TARGET_NEON"
"vpmin.<V_u_elem>\t%P0, %P1, %P2"
;; Assume this schedules like umin.
- [(set_attr "neon_type" "neon_int_5")]
+ [(set_attr "type" "neon_int_5")]
)
(define_insn "neon_vpumax<mode>"
"TARGET_NEON"
"vpmax.<V_u_elem>\t%P0, %P1, %P2"
;; Assume this schedules like umax.
- [(set_attr "neon_type" "neon_int_5")]
+ [(set_attr "type" "neon_int_5")]
)
;; Saturating arithmetic
(match_operand:VD 2 "s_register_operand" "w")))]
"TARGET_NEON"
"vqadd.<V_s_elem>\t%P0, %P1, %P2"
- [(set_attr "neon_type" "neon_int_4")]
+ [(set_attr "type" "neon_int_4")]
)
(define_insn "*us_add<mode>_neon"
(match_operand:VD 2 "s_register_operand" "w")))]
"TARGET_NEON"
"vqadd.<V_u_elem>\t%P0, %P1, %P2"
- [(set_attr "neon_type" "neon_int_4")]
+ [(set_attr "type" "neon_int_4")]
)
(define_insn "*ss_sub<mode>_neon"
(match_operand:VD 2 "s_register_operand" "w")))]
"TARGET_NEON"
"vqsub.<V_s_elem>\t%P0, %P1, %P2"
- [(set_attr "neon_type" "neon_int_5")]
+ [(set_attr "type" "neon_int_5")]
)
(define_insn "*us_sub<mode>_neon"
(match_operand:VD 2 "s_register_operand" "w")))]
"TARGET_NEON"
"vqsub.<V_u_elem>\t%P0, %P1, %P2"
- [(set_attr "neon_type" "neon_int_5")]
+ [(set_attr "type" "neon_int_5")]
)
;; Conditional instructions. These are comparisons with conditional moves for
UNSPEC_VADD))]
"TARGET_NEON"
"vadd.<V_if_elem>\t%<V_reg>0, %<V_reg>1, %<V_reg>2"
- [(set (attr "neon_type")
+ [(set (attr "type")
(if_then_else (match_test "<Is_float_mode>")
(if_then_else (match_test "<Is_d_reg>")
(const_string "neon_fp_vadd_ddd_vabs_dd")
UNSPEC_VADDL))]
"TARGET_NEON"
"vaddl.%T3%#<V_sz_elem>\t%q0, %P1, %P2"
- [(set_attr "neon_type" "neon_int_3")]
+ [(set_attr "type" "neon_int_3")]
)
(define_insn "neon_vaddw<mode>"
UNSPEC_VADDW))]
"TARGET_NEON"
"vaddw.%T3%#<V_sz_elem>\t%q0, %q1, %P2"
- [(set_attr "neon_type" "neon_int_2")]
+ [(set_attr "type" "neon_int_2")]
)
; vhadd and vrhadd.
UNSPEC_VHADD))]
"TARGET_NEON"
"v%O3hadd.%T3%#<V_sz_elem>\t%<V_reg>0, %<V_reg>1, %<V_reg>2"
- [(set_attr "neon_type" "neon_int_4")]
+ [(set_attr "type" "neon_int_4")]
)
(define_insn "neon_vqadd<mode>"
UNSPEC_VQADD))]
"TARGET_NEON"
"vqadd.%T3%#<V_sz_elem>\t%<V_reg>0, %<V_reg>1, %<V_reg>2"
- [(set_attr "neon_type" "neon_int_4")]
+ [(set_attr "type" "neon_int_4")]
)
(define_insn "neon_vaddhn<mode>"
UNSPEC_VADDHN))]
"TARGET_NEON"
"v%O3addhn.<V_if_elem>\t%P0, %q1, %q2"
- [(set_attr "neon_type" "neon_int_4")]
+ [(set_attr "type" "neon_int_4")]
)
;; We cannot replace this unspec with mul<mode>3 because of the odd
UNSPEC_VMUL))]
"TARGET_NEON"
"vmul.%F3%#<V_sz_elem>\t%<V_reg>0, %<V_reg>1, %<V_reg>2"
- [(set (attr "neon_type")
+ [(set (attr "type")
(if_then_else (match_test "<Is_float_mode>")
(if_then_else (match_test "<Is_d_reg>")
(const_string "neon_fp_vadd_ddd_vabs_dd")
UNSPEC_VMLA))]
"TARGET_NEON"
"vmla.<V_if_elem>\t%<V_reg>0, %<V_reg>2, %<V_reg>3"
- [(set (attr "neon_type")
+ [(set (attr "type")
(if_then_else (match_test "<Is_float_mode>")
(if_then_else (match_test "<Is_d_reg>")
(const_string "neon_fp_vmla_ddd")
UNSPEC_VMLAL))]
"TARGET_NEON"
"vmlal.%T4%#<V_sz_elem>\t%q0, %P2, %P3"
- [(set (attr "neon_type")
+ [(set (attr "type")
(if_then_else (match_test "<Scalar_mul_8_16>")
(const_string "neon_mla_ddd_8_16_qdd_16_8_long_32_16_long")
(const_string "neon_mla_ddd_32_qqd_16_ddd_32_scalar_qdd_64_32_long_scalar_qdd_64_32_long")))]
UNSPEC_VMLS))]
"TARGET_NEON"
"vmls.<V_if_elem>\t%<V_reg>0, %<V_reg>2, %<V_reg>3"
- [(set (attr "neon_type")
+ [(set (attr "type")
(if_then_else (match_test "<Is_float_mode>")
(if_then_else (match_test "<Is_d_reg>")
(const_string "neon_fp_vmla_ddd")
UNSPEC_VMLSL))]
"TARGET_NEON"
"vmlsl.%T4%#<V_sz_elem>\t%q0, %P2, %P3"
- [(set (attr "neon_type")
+ [(set (attr "type")
(if_then_else (match_test "<Scalar_mul_8_16>")
(const_string "neon_mla_ddd_8_16_qdd_16_8_long_32_16_long")
(const_string "neon_mla_ddd_32_qqd_16_ddd_32_scalar_qdd_64_32_long_scalar_qdd_64_32_long")))]
UNSPEC_VQDMULH))]
"TARGET_NEON"
"vq%O3dmulh.<V_s_elem>\t%<V_reg>0, %<V_reg>1, %<V_reg>2"
- [(set (attr "neon_type")
+ [(set (attr "type")
(if_then_else (match_test "<Is_d_reg>")
(if_then_else (match_test "<Scalar_mul_8_16>")
(const_string "neon_mul_ddd_8_16_qdd_16_8_long_32_16_long")
UNSPEC_VQDMLAL))]
"TARGET_NEON"
"vqdmlal.<V_s_elem>\t%q0, %P2, %P3"
- [(set (attr "neon_type")
+ [(set (attr "type")
(if_then_else (match_test "<Scalar_mul_8_16>")
(const_string "neon_mla_ddd_8_16_qdd_16_8_long_32_16_long")
(const_string "neon_mla_ddd_32_qqd_16_ddd_32_scalar_qdd_64_32_long_scalar_qdd_64_32_long")))]
UNSPEC_VQDMLSL))]
"TARGET_NEON"
"vqdmlsl.<V_s_elem>\t%q0, %P2, %P3"
- [(set (attr "neon_type")
+ [(set (attr "type")
(if_then_else (match_test "<Scalar_mul_8_16>")
(const_string "neon_mla_ddd_8_16_qdd_16_8_long_32_16_long")
(const_string "neon_mla_ddd_32_qqd_16_ddd_32_scalar_qdd_64_32_long_scalar_qdd_64_32_long")))]
UNSPEC_VMULL))]
"TARGET_NEON"
"vmull.%T3%#<V_sz_elem>\t%q0, %P1, %P2"
- [(set (attr "neon_type")
+ [(set (attr "type")
(if_then_else (match_test "<Scalar_mul_8_16>")
(const_string "neon_mul_ddd_8_16_qdd_16_8_long_32_16_long")
(const_string "neon_mul_qdd_64_32_long_qqd_16_ddd_32_scalar_64_32_long_scalar")))]
UNSPEC_VQDMULL))]
"TARGET_NEON"
"vqdmull.<V_s_elem>\t%q0, %P1, %P2"
- [(set (attr "neon_type")
+ [(set (attr "type")
(if_then_else (match_test "<Scalar_mul_8_16>")
(const_string "neon_mul_ddd_8_16_qdd_16_8_long_32_16_long")
(const_string "neon_mul_qdd_64_32_long_qqd_16_ddd_32_scalar_64_32_long_scalar")))]
UNSPEC_VSUB))]
"TARGET_NEON"
"vsub.<V_if_elem>\t%<V_reg>0, %<V_reg>1, %<V_reg>2"
- [(set (attr "neon_type")
+ [(set (attr "type")
(if_then_else (match_test "<Is_float_mode>")
(if_then_else (match_test "<Is_d_reg>")
(const_string "neon_fp_vadd_ddd_vabs_dd")
UNSPEC_VSUBL))]
"TARGET_NEON"
"vsubl.%T3%#<V_sz_elem>\t%q0, %P1, %P2"
- [(set_attr "neon_type" "neon_int_2")]
+ [(set_attr "type" "neon_int_2")]
)
(define_insn "neon_vsubw<mode>"
UNSPEC_VSUBW))]
"TARGET_NEON"
"vsubw.%T3%#<V_sz_elem>\t%q0, %q1, %P2"
- [(set_attr "neon_type" "neon_int_2")]
+ [(set_attr "type" "neon_int_2")]
)
(define_insn "neon_vqsub<mode>"
UNSPEC_VQSUB))]
"TARGET_NEON"
"vqsub.%T3%#<V_sz_elem>\t%<V_reg>0, %<V_reg>1, %<V_reg>2"
- [(set_attr "neon_type" "neon_int_5")]
+ [(set_attr "type" "neon_int_5")]
)
(define_insn "neon_vhsub<mode>"
UNSPEC_VHSUB))]
"TARGET_NEON"
"vhsub.%T3%#<V_sz_elem>\t%<V_reg>0, %<V_reg>1, %<V_reg>2"
- [(set_attr "neon_type" "neon_int_5")]
+ [(set_attr "type" "neon_int_5")]
)
(define_insn "neon_vsubhn<mode>"
UNSPEC_VSUBHN))]
"TARGET_NEON"
"v%O3subhn.<V_if_elem>\t%P0, %q1, %q2"
- [(set_attr "neon_type" "neon_int_4")]
+ [(set_attr "type" "neon_int_4")]
)
(define_insn "neon_vceq<mode>"
"@
vceq.<V_if_elem>\t%<V_reg>0, %<V_reg>1, %<V_reg>2
vceq.<V_if_elem>\t%<V_reg>0, %<V_reg>1, #0"
- [(set (attr "neon_type")
+ [(set (attr "type")
(if_then_else (match_test "<Is_float_mode>")
(if_then_else (match_test "<Is_d_reg>")
(const_string "neon_fp_vadd_ddd_vabs_dd")
"@
vcge.%T3%#<V_sz_elem>\t%<V_reg>0, %<V_reg>1, %<V_reg>2
vcge.%T3%#<V_sz_elem>\t%<V_reg>0, %<V_reg>1, #0"
- [(set (attr "neon_type")
+ [(set (attr "type")
(if_then_else (match_test "<Is_float_mode>")
(if_then_else (match_test "<Is_d_reg>")
(const_string "neon_fp_vadd_ddd_vabs_dd")
UNSPEC_VCGEU))]
"TARGET_NEON"
"vcge.%T3%#<V_sz_elem>\t%<V_reg>0, %<V_reg>1, %<V_reg>2"
- [(set_attr "neon_type" "neon_int_5")]
+ [(set_attr "type" "neon_int_5")]
)
(define_insn "neon_vcgt<mode>"
"@
vcgt.%T3%#<V_sz_elem>\t%<V_reg>0, %<V_reg>1, %<V_reg>2
vcgt.%T3%#<V_sz_elem>\t%<V_reg>0, %<V_reg>1, #0"
- [(set (attr "neon_type")
+ [(set (attr "type")
(if_then_else (match_test "<Is_float_mode>")
(if_then_else (match_test "<Is_d_reg>")
(const_string "neon_fp_vadd_ddd_vabs_dd")
UNSPEC_VCGTU))]
"TARGET_NEON"
"vcgt.%T3%#<V_sz_elem>\t%<V_reg>0, %<V_reg>1, %<V_reg>2"
- [(set_attr "neon_type" "neon_int_5")]
+ [(set_attr "type" "neon_int_5")]
)
;; VCLE and VCLT only support comparisons with immediate zero (register
UNSPEC_VCLE))]
"TARGET_NEON"
"vcle.%T3%#<V_sz_elem>\t%<V_reg>0, %<V_reg>1, #0"
- [(set (attr "neon_type")
+ [(set (attr "type")
(if_then_else (match_test "<Is_float_mode>")
(if_then_else (match_test "<Is_d_reg>")
(const_string "neon_fp_vadd_ddd_vabs_dd")
UNSPEC_VCLT))]
"TARGET_NEON"
"vclt.%T3%#<V_sz_elem>\t%<V_reg>0, %<V_reg>1, #0"
- [(set (attr "neon_type")
+ [(set (attr "type")
(if_then_else (match_test "<Is_float_mode>")
(if_then_else (match_test "<Is_d_reg>")
(const_string "neon_fp_vadd_ddd_vabs_dd")
UNSPEC_VCAGE))]
"TARGET_NEON"
"vacge.<V_if_elem>\t%<V_reg>0, %<V_reg>1, %<V_reg>2"
- [(set (attr "neon_type")
+ [(set (attr "type")
(if_then_else (match_test "<Is_d_reg>")
(const_string "neon_fp_vadd_ddd_vabs_dd")
(const_string "neon_fp_vadd_qqq_vabs_qq")))]
UNSPEC_VCAGT))]
"TARGET_NEON"
"vacgt.<V_if_elem>\t%<V_reg>0, %<V_reg>1, %<V_reg>2"
- [(set (attr "neon_type")
+ [(set (attr "type")
(if_then_else (match_test "<Is_d_reg>")
(const_string "neon_fp_vadd_ddd_vabs_dd")
(const_string "neon_fp_vadd_qqq_vabs_qq")))]
UNSPEC_VTST))]
"TARGET_NEON"
"vtst.<V_sz_elem>\t%<V_reg>0, %<V_reg>1, %<V_reg>2"
- [(set_attr "neon_type" "neon_int_4")]
+ [(set_attr "type" "neon_int_4")]
)
(define_insn "neon_vabd<mode>"
UNSPEC_VABD))]
"TARGET_NEON"
"vabd.%T3%#<V_sz_elem>\t%<V_reg>0, %<V_reg>1, %<V_reg>2"
- [(set (attr "neon_type")
+ [(set (attr "type")
(if_then_else (match_test "<Is_float_mode>")
(if_then_else (match_test "<Is_d_reg>")
(const_string "neon_fp_vadd_ddd_vabs_dd")
UNSPEC_VABDL))]
"TARGET_NEON"
"vabdl.%T3%#<V_sz_elem>\t%q0, %P1, %P2"
- [(set_attr "neon_type" "neon_int_5")]
+ [(set_attr "type" "neon_int_5")]
)
(define_insn "neon_vaba<mode>"
(match_operand:VDQIW 1 "s_register_operand" "0")))]
"TARGET_NEON"
"vaba.%T4%#<V_sz_elem>\t%<V_reg>0, %<V_reg>2, %<V_reg>3"
- [(set (attr "neon_type")
+ [(set (attr "type")
(if_then_else (match_test "<Is_d_reg>")
(const_string "neon_vaba") (const_string "neon_vaba_qqq")))]
)
(match_operand:<V_widen> 1 "s_register_operand" "0")))]
"TARGET_NEON"
"vabal.%T4%#<V_sz_elem>\t%q0, %P2, %P3"
- [(set_attr "neon_type" "neon_vaba")]
+ [(set_attr "type" "neon_vaba")]
)
(define_insn "neon_vmax<mode>"
UNSPEC_VMAX))]
"TARGET_NEON"
"vmax.%T3%#<V_sz_elem>\t%<V_reg>0, %<V_reg>1, %<V_reg>2"
- [(set (attr "neon_type")
+ [(set (attr "type")
(if_then_else (match_test "<Is_float_mode>")
(if_then_else (match_test "<Is_d_reg>")
(const_string "neon_fp_vadd_ddd_vabs_dd")
UNSPEC_VMIN))]
"TARGET_NEON"
"vmin.%T3%#<V_sz_elem>\t%<V_reg>0, %<V_reg>1, %<V_reg>2"
- [(set (attr "neon_type")
+ [(set (attr "type")
(if_then_else (match_test "<Is_float_mode>")
(if_then_else (match_test "<Is_d_reg>")
(const_string "neon_fp_vadd_ddd_vabs_dd")
"TARGET_NEON"
"vpaddl.%T2%#<V_sz_elem>\t%<V_reg>0, %<V_reg>1"
;; Assume this schedules like vaddl.
- [(set_attr "neon_type" "neon_int_3")]
+ [(set_attr "type" "neon_int_3")]
)
(define_insn "neon_vpadal<mode>"
"TARGET_NEON"
"vpadal.%T3%#<V_sz_elem>\t%<V_reg>0, %<V_reg>2"
;; Assume this schedules like vpadd.
- [(set_attr "neon_type" "neon_int_1")]
+ [(set_attr "type" "neon_int_1")]
)
(define_insn "neon_vpmax<mode>"
"TARGET_NEON"
"vpmax.%T3%#<V_sz_elem>\t%<V_reg>0, %<V_reg>1, %<V_reg>2"
;; Assume this schedules like vmax.
- [(set (attr "neon_type")
+ [(set (attr "type")
(if_then_else (match_test "<Is_float_mode>")
(const_string "neon_fp_vadd_ddd_vabs_dd")
(const_string "neon_int_5")))]
"TARGET_NEON"
"vpmin.%T3%#<V_sz_elem>\t%<V_reg>0, %<V_reg>1, %<V_reg>2"
;; Assume this schedules like vmin.
- [(set (attr "neon_type")
+ [(set (attr "type")
(if_then_else (match_test "<Is_float_mode>")
(const_string "neon_fp_vadd_ddd_vabs_dd")
(const_string "neon_int_5")))]
UNSPEC_VRECPS))]
"TARGET_NEON"
"vrecps.<V_if_elem>\t%<V_reg>0, %<V_reg>1, %<V_reg>2"
- [(set (attr "neon_type")
+ [(set (attr "type")
(if_then_else (match_test "<Is_d_reg>")
(const_string "neon_fp_vrecps_vrsqrts_ddd")
(const_string "neon_fp_vrecps_vrsqrts_qqq")))]
UNSPEC_VRSQRTS))]
"TARGET_NEON"
"vrsqrts.<V_if_elem>\t%<V_reg>0, %<V_reg>1, %<V_reg>2"
- [(set (attr "neon_type")
+ [(set (attr "type")
(if_then_else (match_test "<Is_d_reg>")
(const_string "neon_fp_vrecps_vrsqrts_ddd")
(const_string "neon_fp_vrecps_vrsqrts_qqq")))]
UNSPEC_VQABS))]
"TARGET_NEON"
"vqabs.<V_s_elem>\t%<V_reg>0, %<V_reg>1"
- [(set_attr "neon_type" "neon_vqneg_vqabs")]
+ [(set_attr "type" "neon_vqneg_vqabs")]
)
(define_expand "neon_vneg<mode>"
UNSPEC_VQNEG))]
"TARGET_NEON"
"vqneg.<V_s_elem>\t%<V_reg>0, %<V_reg>1"
- [(set_attr "neon_type" "neon_vqneg_vqabs")]
+ [(set_attr "type" "neon_vqneg_vqabs")]
)
(define_insn "neon_vcls<mode>"
UNSPEC_VCLS))]
"TARGET_NEON"
"vcls.<V_s_elem>\t%<V_reg>0, %<V_reg>1"
- [(set_attr "neon_type" "neon_int_1")]
+ [(set_attr "type" "neon_int_1")]
)
(define_insn "clz<mode>2"
(clz:VDQIW (match_operand:VDQIW 1 "s_register_operand" "w")))]
"TARGET_NEON"
"vclz.<V_if_elem>\t%<V_reg>0, %<V_reg>1"
- [(set_attr "neon_type" "neon_int_1")]
+ [(set_attr "type" "neon_int_1")]
)
(define_expand "neon_vclz<mode>"
(popcount:VE (match_operand:VE 1 "s_register_operand" "w")))]
"TARGET_NEON"
"vcnt.<V_sz_elem>\t%<V_reg>0, %<V_reg>1"
- [(set_attr "neon_type" "neon_int_1")]
+ [(set_attr "type" "neon_int_1")]
)
(define_expand "neon_vcnt<mode>"
UNSPEC_VRECPE))]
"TARGET_NEON"
"vrecpe.<V_u_elem>\t%<V_reg>0, %<V_reg>1"
- [(set (attr "neon_type")
+ [(set (attr "type")
(if_then_else (match_test "<Is_d_reg>")
(const_string "neon_fp_vadd_ddd_vabs_dd")
(const_string "neon_fp_vadd_qqq_vabs_qq")))]
UNSPEC_VRSQRTE))]
"TARGET_NEON"
"vrsqrte.<V_u_elem>\t%<V_reg>0, %<V_reg>1"
- [(set (attr "neon_type")
+ [(set (attr "type")
(if_then_else (match_test "<Is_d_reg>")
(const_string "neon_fp_vadd_ddd_vabs_dd")
(const_string "neon_fp_vadd_qqq_vabs_qq")))]
}
return "vmov.s<V_sz_elem>\t%0, %P1[%c2]";
}
- [(set_attr "neon_type" "neon_bp_simple")]
+ [(set_attr "type" "neon_bp_simple")]
)
(define_insn "neon_vget_lane<mode>_zext_internal"
}
return "vmov.u<V_sz_elem>\t%0, %P1[%c2]";
}
- [(set_attr "neon_type" "neon_bp_simple")]
+ [(set_attr "type" "neon_bp_simple")]
)
(define_insn "neon_vget_lane<mode>_sext_internal"
return "";
}
- [(set_attr "neon_type" "neon_bp_simple")]
+ [(set_attr "type" "neon_bp_simple")]
)
(define_insn "neon_vget_lane<mode>_zext_internal"
return "";
}
- [(set_attr "neon_type" "neon_bp_simple")]
+ [(set_attr "type" "neon_bp_simple")]
)
(define_expand "neon_vget_lane<mode>"
"TARGET_NEON"
"vdup.<V_sz_elem>\t%<V_reg>0, %1"
;; Assume this schedules like vmov.
- [(set_attr "neon_type" "neon_bp_simple")]
+ [(set_attr "type" "neon_bp_simple")]
)
(define_insn "neon_vdup_n<mode>"
vdup.<V_sz_elem>\t%<V_reg>0, %1
vdup.<V_sz_elem>\t%<V_reg>0, %y1"
;; Assume this schedules like vmov.
- [(set_attr "neon_type" "neon_bp_simple")]
+ [(set_attr "type" "neon_bp_simple")]
)
(define_expand "neon_vdup_ndi"
vmov\t%e0, %Q1, %R1\;vmov\t%f0, %Q1, %R1
vmov\t%e0, %P1\;vmov\t%f0, %P1"
[(set_attr "length" "8")
- (set_attr "neon_type" "neon_bp_simple")]
+ (set_attr "type" "neon_bp_simple")]
)
(define_insn "neon_vdup_lane<mode>_internal"
return "vdup.<V_sz_elem>\t%q0, %P1[%c2]";
}
;; Assume this schedules like vmov.
- [(set_attr "neon_type" "neon_bp_simple")]
+ [(set_attr "type" "neon_bp_simple")]
)
(define_expand "neon_vdup_lane<mode>"
(set (match_dup 1) (match_dup 0))]
"TARGET_NEON && reload_completed"
"vswp\t%<V_reg>0, %<V_reg>1"
- [(set (attr "neon_type")
+ [(set (attr "type")
(if_then_else (match_test "<Is_d_reg>")
(const_string "neon_bp_simple")
(const_string "neon_bp_2cycle")))]
(float:<V_CVTTO> (match_operand:VCVTI 1 "s_register_operand" "w")))]
"TARGET_NEON && !flag_rounding_math"
"vcvt.f32.s32\t%<V_reg>0, %<V_reg>1"
- [(set (attr "neon_type")
+ [(set (attr "type")
(if_then_else (match_test "<Is_d_reg>")
(const_string "neon_fp_vadd_ddd_vabs_dd")
(const_string "neon_fp_vadd_qqq_vabs_qq")))]
(unsigned_float:<V_CVTTO> (match_operand:VCVTI 1 "s_register_operand" "w")))]
"TARGET_NEON && !flag_rounding_math"
"vcvt.f32.u32\t%<V_reg>0, %<V_reg>1"
- [(set (attr "neon_type")
+ [(set (attr "type")
(if_then_else (match_test "<Is_d_reg>")
(const_string "neon_fp_vadd_ddd_vabs_dd")
(const_string "neon_fp_vadd_qqq_vabs_qq")))]
(fix:<V_CVTTO> (match_operand:VCVTF 1 "s_register_operand" "w")))]
"TARGET_NEON"
"vcvt.s32.f32\t%<V_reg>0, %<V_reg>1"
- [(set (attr "neon_type")
+ [(set (attr "type")
(if_then_else (match_test "<Is_d_reg>")
(const_string "neon_fp_vadd_ddd_vabs_dd")
(const_string "neon_fp_vadd_qqq_vabs_qq")))]
(unsigned_fix:<V_CVTTO> (match_operand:VCVTF 1 "s_register_operand" "w")))]
"TARGET_NEON"
"vcvt.u32.f32\t%<V_reg>0, %<V_reg>1"
- [(set (attr "neon_type")
+ [(set (attr "type")
(if_then_else (match_test "<Is_d_reg>")
(const_string "neon_fp_vadd_ddd_vabs_dd")
(const_string "neon_fp_vadd_qqq_vabs_qq")))]
UNSPEC_VCVT))]
"TARGET_NEON"
"vcvt.%T2%#32.f32\t%<V_reg>0, %<V_reg>1"
- [(set (attr "neon_type")
+ [(set (attr "type")
(if_then_else (match_test "<Is_d_reg>")
(const_string "neon_fp_vadd_ddd_vabs_dd")
(const_string "neon_fp_vadd_qqq_vabs_qq")))]
UNSPEC_VCVT))]
"TARGET_NEON"
"vcvt.f32.%T2%#32\t%<V_reg>0, %<V_reg>1"
- [(set (attr "neon_type")
+ [(set (attr "type")
(if_then_else (match_test "<Is_d_reg>")
(const_string "neon_fp_vadd_ddd_vabs_dd")
(const_string "neon_fp_vadd_qqq_vabs_qq")))]
UNSPEC_VCVT))]
"TARGET_NEON && TARGET_FP16"
"vcvt.f32.f16\t%q0, %P1"
- [(set_attr "neon_type" "neon_fp_vadd_ddd_vabs_dd")]
+ [(set_attr "type" "neon_fp_vadd_ddd_vabs_dd")]
)
(define_insn "neon_vcvtv4hfv4sf"
UNSPEC_VCVT))]
"TARGET_NEON && TARGET_FP16"
"vcvt.f16.f32\t%P0, %q1"
- [(set_attr "neon_type" "neon_fp_vadd_ddd_vabs_dd")]
+ [(set_attr "type" "neon_fp_vadd_ddd_vabs_dd")]
)
(define_insn "neon_vcvt_n<mode>"
neon_const_bounds (operands[2], 1, 33);
return "vcvt.%T3%#32.f32\t%<V_reg>0, %<V_reg>1, %2";
}
- [(set (attr "neon_type")
+ [(set (attr "type")
(if_then_else (match_test "<Is_d_reg>")
(const_string "neon_fp_vadd_ddd_vabs_dd")
(const_string "neon_fp_vadd_qqq_vabs_qq")))]
neon_const_bounds (operands[2], 1, 33);
return "vcvt.f32.%T3%#32\t%<V_reg>0, %<V_reg>1, %2";
}
- [(set (attr "neon_type")
+ [(set (attr "type")
(if_then_else (match_test "<Is_d_reg>")
(const_string "neon_fp_vadd_ddd_vabs_dd")
(const_string "neon_fp_vadd_qqq_vabs_qq")))]
UNSPEC_VMOVN))]
"TARGET_NEON"
"vmovn.<V_if_elem>\t%P0, %q1"
- [(set_attr "neon_type" "neon_bp_simple")]
+ [(set_attr "type" "neon_bp_simple")]
)
(define_insn "neon_vqmovn<mode>"
UNSPEC_VQMOVN))]
"TARGET_NEON"
"vqmovn.%T2%#<V_sz_elem>\t%P0, %q1"
- [(set_attr "neon_type" "neon_shift_2")]
+ [(set_attr "type" "neon_shift_2")]
)
(define_insn "neon_vqmovun<mode>"
UNSPEC_VQMOVUN))]
"TARGET_NEON"
"vqmovun.<V_s_elem>\t%P0, %q1"
- [(set_attr "neon_type" "neon_shift_2")]
+ [(set_attr "type" "neon_shift_2")]
)
(define_insn "neon_vmovl<mode>"
UNSPEC_VMOVL))]
"TARGET_NEON"
"vmovl.%T2%#<V_sz_elem>\t%q0, %P1"
- [(set_attr "neon_type" "neon_shift_1")]
+ [(set_attr "type" "neon_shift_1")]
)
(define_insn "neon_vmul_lane<mode>"
neon_lane_bounds (operands[3], 0, GET_MODE_NUNITS (<MODE>mode));
return "vmul.<V_if_elem>\t%P0, %P1, %P2[%c3]";
}
- [(set (attr "neon_type")
+ [(set (attr "type")
(if_then_else (match_test "<Is_float_mode>")
(const_string "neon_fp_vmul_ddd")
(if_then_else (match_test "<Scalar_mul_8_16>")
neon_lane_bounds (operands[3], 0, GET_MODE_NUNITS (<V_HALF>mode));
return "vmul.<V_if_elem>\t%q0, %q1, %P2[%c3]";
}
- [(set (attr "neon_type")
+ [(set (attr "type")
(if_then_else (match_test "<Is_float_mode>")
(const_string "neon_fp_vmul_qqd")
(if_then_else (match_test "<Scalar_mul_8_16>")
neon_lane_bounds (operands[3], 0, GET_MODE_NUNITS (<MODE>mode));
return "vmull.%T4%#<V_sz_elem>\t%q0, %P1, %P2[%c3]";
}
- [(set (attr "neon_type")
+ [(set (attr "type")
(if_then_else (match_test "<Scalar_mul_8_16>")
(const_string "neon_mul_ddd_16_scalar_32_16_long_scalar")
(const_string "neon_mul_qdd_64_32_long_qqd_16_ddd_32_scalar_64_32_long_scalar")))]
neon_lane_bounds (operands[3], 0, GET_MODE_NUNITS (<MODE>mode));
return "vqdmull.<V_s_elem>\t%q0, %P1, %P2[%c3]";
}
- [(set (attr "neon_type")
+ [(set (attr "type")
(if_then_else (match_test "<Scalar_mul_8_16>")
(const_string "neon_mul_ddd_16_scalar_32_16_long_scalar")
(const_string "neon_mul_qdd_64_32_long_qqd_16_ddd_32_scalar_64_32_long_scalar")))]
neon_lane_bounds (operands[3], 0, GET_MODE_NUNITS (<MODE>mode));
return "vq%O4dmulh.%T4%#<V_sz_elem>\t%q0, %q1, %P2[%c3]";
}
- [(set (attr "neon_type")
+ [(set (attr "type")
(if_then_else (match_test "<Scalar_mul_8_16>")
(const_string "neon_mul_qdd_64_32_long_qqd_16_ddd_32_scalar_64_32_long_scalar")
(const_string "neon_mul_qqd_32_scalar")))]
neon_lane_bounds (operands[3], 0, GET_MODE_NUNITS (<MODE>mode));
return "vq%O4dmulh.%T4%#<V_sz_elem>\t%P0, %P1, %P2[%c3]";
}
- [(set (attr "neon_type")
+ [(set (attr "type")
(if_then_else (match_test "<Scalar_mul_8_16>")
(const_string "neon_mul_ddd_16_scalar_32_16_long_scalar")
(const_string "neon_mul_qdd_64_32_long_qqd_16_ddd_32_scalar_64_32_long_scalar")))]
neon_lane_bounds (operands[4], 0, GET_MODE_NUNITS (<MODE>mode));
return "vmla.<V_if_elem>\t%P0, %P2, %P3[%c4]";
}
- [(set (attr "neon_type")
+ [(set (attr "type")
(if_then_else (match_test "<Is_float_mode>")
(const_string "neon_fp_vmla_ddd_scalar")
(if_then_else (match_test "<Scalar_mul_8_16>")
neon_lane_bounds (operands[4], 0, GET_MODE_NUNITS (<MODE>mode));
return "vmla.<V_if_elem>\t%q0, %q2, %P3[%c4]";
}
- [(set (attr "neon_type")
+ [(set (attr "type")
(if_then_else (match_test "<Is_float_mode>")
(const_string "neon_fp_vmla_qqq_scalar")
(if_then_else (match_test "<Scalar_mul_8_16>")
neon_lane_bounds (operands[4], 0, GET_MODE_NUNITS (<MODE>mode));
return "vmlal.%T5%#<V_sz_elem>\t%q0, %P2, %P3[%c4]";
}
- [(set (attr "neon_type")
+ [(set (attr "type")
(if_then_else (match_test "<Scalar_mul_8_16>")
(const_string "neon_mla_ddd_16_scalar_qdd_32_16_long_scalar")
(const_string "neon_mla_ddd_32_qqd_16_ddd_32_scalar_qdd_64_32_long_scalar_qdd_64_32_long")))]
neon_lane_bounds (operands[4], 0, GET_MODE_NUNITS (<MODE>mode));
return "vqdmlal.<V_s_elem>\t%q0, %P2, %P3[%c4]";
}
- [(set (attr "neon_type")
+ [(set (attr "type")
(if_then_else (match_test "<Scalar_mul_8_16>")
(const_string "neon_mla_ddd_16_scalar_qdd_32_16_long_scalar")
(const_string "neon_mla_ddd_32_qqd_16_ddd_32_scalar_qdd_64_32_long_scalar_qdd_64_32_long")))]
neon_lane_bounds (operands[4], 0, GET_MODE_NUNITS (<MODE>mode));
return "vmls.<V_if_elem>\t%P0, %P2, %P3[%c4]";
}
- [(set (attr "neon_type")
+ [(set (attr "type")
(if_then_else (match_test "<Is_float_mode>")
(const_string "neon_fp_vmla_ddd_scalar")
(if_then_else (match_test "<Scalar_mul_8_16>")
neon_lane_bounds (operands[4], 0, GET_MODE_NUNITS (<MODE>mode));
return "vmls.<V_if_elem>\t%q0, %q2, %P3[%c4]";
}
- [(set (attr "neon_type")
+ [(set (attr "type")
(if_then_else (match_test "<Is_float_mode>")
(const_string "neon_fp_vmla_qqq_scalar")
(if_then_else (match_test "<Scalar_mul_8_16>")
neon_lane_bounds (operands[4], 0, GET_MODE_NUNITS (<MODE>mode));
return "vmlsl.%T5%#<V_sz_elem>\t%q0, %P2, %P3[%c4]";
}
- [(set (attr "neon_type")
+ [(set (attr "type")
(if_then_else (match_test "<Scalar_mul_8_16>")
(const_string "neon_mla_ddd_16_scalar_qdd_32_16_long_scalar")
(const_string "neon_mla_ddd_32_qqd_16_ddd_32_scalar_qdd_64_32_long_scalar_qdd_64_32_long")))]
neon_lane_bounds (operands[4], 0, GET_MODE_NUNITS (<MODE>mode));
return "vqdmlsl.<V_s_elem>\t%q0, %P2, %P3[%c4]";
}
- [(set (attr "neon_type")
+ [(set (attr "type")
(if_then_else (match_test "<Scalar_mul_8_16>")
(const_string "neon_mla_ddd_16_scalar_qdd_32_16_long_scalar")
(const_string "neon_mla_ddd_32_qqd_16_ddd_32_scalar_qdd_64_32_long_scalar_qdd_64_32_long")))]
neon_const_bounds (operands[3], 0, GET_MODE_NUNITS (<MODE>mode));
return "vext.<V_sz_elem>\t%<V_reg>0, %<V_reg>1, %<V_reg>2, %3";
}
- [(set (attr "neon_type")
+ [(set (attr "type")
(if_then_else (match_test "<Is_d_reg>")
(const_string "neon_bp_simple")
(const_string "neon_bp_2cycle")))]
UNSPEC_VREV64))]
"TARGET_NEON"
"vrev64.<V_sz_elem>\t%<V_reg>0, %<V_reg>1"
- [(set_attr "neon_type" "neon_bp_simple")]
+ [(set_attr "type" "neon_bp_simple")]
)
(define_insn "neon_vrev32<mode>"
UNSPEC_VREV32))]
"TARGET_NEON"
"vrev32.<V_sz_elem>\t%<V_reg>0, %<V_reg>1"
- [(set_attr "neon_type" "neon_bp_simple")]
+ [(set_attr "type" "neon_bp_simple")]
)
(define_insn "neon_vrev16<mode>"
UNSPEC_VREV16))]
"TARGET_NEON"
"vrev16.<V_sz_elem>\t%<V_reg>0, %<V_reg>1"
- [(set_attr "neon_type" "neon_bp_simple")]
+ [(set_attr "type" "neon_bp_simple")]
)
; vbsl_* intrinsics may compile to any of vbsl/vbif/vbit depending on register
vbsl\t%<V_reg>0, %<V_reg>2, %<V_reg>3
vbit\t%<V_reg>0, %<V_reg>2, %<V_reg>1
vbif\t%<V_reg>0, %<V_reg>3, %<V_reg>1"
- [(set_attr "neon_type" "neon_int_1")]
+ [(set_attr "type" "neon_int_1")]
)
(define_expand "neon_vbsl<mode>"
UNSPEC_VSHL))]
"TARGET_NEON"
"v%O3shl.%T3%#<V_sz_elem>\t%<V_reg>0, %<V_reg>1, %<V_reg>2"
- [(set (attr "neon_type")
+ [(set (attr "type")
(if_then_else (match_test "<Is_d_reg>")
(const_string "neon_vshl_ddd")
(const_string "neon_shift_3")))]
UNSPEC_VQSHL))]
"TARGET_NEON"
"vq%O3shl.%T3%#<V_sz_elem>\t%<V_reg>0, %<V_reg>1, %<V_reg>2"
- [(set (attr "neon_type")
+ [(set (attr "type")
(if_then_else (match_test "<Is_d_reg>")
(const_string "neon_shift_2")
(const_string "neon_vqshl_vrshl_vqrshl_qqq")))]
neon_const_bounds (operands[2], 1, neon_element_bits (<MODE>mode) + 1);
return "v%O3shr.%T3%#<V_sz_elem>\t%<V_reg>0, %<V_reg>1, %2";
}
- [(set_attr "neon_type" "neon_shift_1")]
+ [(set_attr "type" "neon_shift_1")]
)
(define_insn "neon_vshrn_n<mode>"
neon_const_bounds (operands[2], 1, neon_element_bits (<MODE>mode) / 2 + 1);
return "v%O3shrn.<V_if_elem>\t%P0, %q1, %2";
}
- [(set_attr "neon_type" "neon_shift_1")]
+ [(set_attr "type" "neon_shift_1")]
)
(define_insn "neon_vqshrn_n<mode>"
neon_const_bounds (operands[2], 1, neon_element_bits (<MODE>mode) / 2 + 1);
return "vq%O3shrn.%T3%#<V_sz_elem>\t%P0, %q1, %2";
}
- [(set_attr "neon_type" "neon_shift_2")]
+ [(set_attr "type" "neon_shift_2")]
)
(define_insn "neon_vqshrun_n<mode>"
neon_const_bounds (operands[2], 1, neon_element_bits (<MODE>mode) / 2 + 1);
return "vq%O3shrun.%T3%#<V_sz_elem>\t%P0, %q1, %2";
}
- [(set_attr "neon_type" "neon_shift_2")]
+ [(set_attr "type" "neon_shift_2")]
)
(define_insn "neon_vshl_n<mode>"
neon_const_bounds (operands[2], 0, neon_element_bits (<MODE>mode));
return "vshl.<V_if_elem>\t%<V_reg>0, %<V_reg>1, %2";
}
- [(set_attr "neon_type" "neon_shift_1")]
+ [(set_attr "type" "neon_shift_1")]
)
(define_insn "neon_vqshl_n<mode>"
neon_const_bounds (operands[2], 0, neon_element_bits (<MODE>mode));
return "vqshl.%T3%#<V_sz_elem>\t%<V_reg>0, %<V_reg>1, %2";
}
- [(set_attr "neon_type" "neon_shift_2")]
+ [(set_attr "type" "neon_shift_2")]
)
(define_insn "neon_vqshlu_n<mode>"
neon_const_bounds (operands[2], 0, neon_element_bits (<MODE>mode));
return "vqshlu.%T3%#<V_sz_elem>\t%<V_reg>0, %<V_reg>1, %2";
}
- [(set_attr "neon_type" "neon_shift_2")]
+ [(set_attr "type" "neon_shift_2")]
)
(define_insn "neon_vshll_n<mode>"
neon_const_bounds (operands[2], 0, neon_element_bits (<MODE>mode) + 1);
return "vshll.%T3%#<V_sz_elem>\t%q0, %P1, %2";
}
- [(set_attr "neon_type" "neon_shift_1")]
+ [(set_attr "type" "neon_shift_1")]
)
(define_insn "neon_vsra_n<mode>"
neon_const_bounds (operands[3], 1, neon_element_bits (<MODE>mode) + 1);
return "v%O4sra.%T4%#<V_sz_elem>\t%<V_reg>0, %<V_reg>2, %3";
}
- [(set_attr "neon_type" "neon_vsra_vrsra")]
+ [(set_attr "type" "neon_vsra_vrsra")]
)
(define_insn "neon_vsri_n<mode>"
neon_const_bounds (operands[3], 1, neon_element_bits (<MODE>mode) + 1);
return "vsri.<V_sz_elem>\t%<V_reg>0, %<V_reg>2, %3";
}
- [(set (attr "neon_type")
+ [(set (attr "type")
(if_then_else (match_test "<Is_d_reg>")
(const_string "neon_shift_1")
(const_string "neon_shift_3")))]
neon_const_bounds (operands[3], 0, neon_element_bits (<MODE>mode));
return "vsli.<V_sz_elem>\t%<V_reg>0, %<V_reg>2, %3";
}
- [(set (attr "neon_type")
+ [(set (attr "type")
(if_then_else (match_test "<Is_d_reg>")
(const_string "neon_shift_1")
(const_string "neon_shift_3")))]
UNSPEC_VTBL))]
"TARGET_NEON"
"vtbl.8\t%P0, {%P1}, %P2"
- [(set_attr "neon_type" "neon_bp_2cycle")]
+ [(set_attr "type" "neon_bp_2cycle")]
)
(define_insn "neon_vtbl2v8qi"
return "";
}
- [(set_attr "neon_type" "neon_bp_2cycle")]
+ [(set_attr "type" "neon_bp_2cycle")]
)
(define_insn "neon_vtbl3v8qi"
return "";
}
- [(set_attr "neon_type" "neon_bp_3cycle")]
+ [(set_attr "type" "neon_bp_3cycle")]
)
(define_insn "neon_vtbl4v8qi"
return "";
}
- [(set_attr "neon_type" "neon_bp_3cycle")]
+ [(set_attr "type" "neon_bp_3cycle")]
)
;; These three are used by the vec_perm infrastructure for V16QImode.
UNSPEC_VTBX))]
"TARGET_NEON"
"vtbx.8\t%P0, {%P2}, %P3"
- [(set_attr "neon_type" "neon_bp_2cycle")]
+ [(set_attr "type" "neon_bp_2cycle")]
)
(define_insn "neon_vtbx2v8qi"
return "";
}
- [(set_attr "neon_type" "neon_bp_2cycle")]
+ [(set_attr "type" "neon_bp_2cycle")]
)
(define_insn "neon_vtbx3v8qi"
return "";
}
- [(set_attr "neon_type" "neon_bp_3cycle")]
+ [(set_attr "type" "neon_bp_3cycle")]
)
(define_insn "neon_vtbx4v8qi"
return "";
}
- [(set_attr "neon_type" "neon_bp_3cycle")]
+ [(set_attr "type" "neon_bp_3cycle")]
)
(define_expand "neon_vtrn<mode>_internal"
UNSPEC_VTRN2))]
"TARGET_NEON"
"vtrn.<V_sz_elem>\t%<V_reg>0, %<V_reg>2"
- [(set (attr "neon_type")
+ [(set (attr "type")
(if_then_else (match_test "<Is_d_reg>")
(const_string "neon_bp_simple")
(const_string "neon_bp_3cycle")))]
UNSPEC_VZIP2))]
"TARGET_NEON"
"vzip.<V_sz_elem>\t%<V_reg>0, %<V_reg>2"
- [(set (attr "neon_type")
+ [(set (attr "type")
(if_then_else (match_test "<Is_d_reg>")
(const_string "neon_bp_simple")
(const_string "neon_bp_3cycle")))]
UNSPEC_VUZP2))]
"TARGET_NEON"
"vuzp.<V_sz_elem>\t%<V_reg>0, %<V_reg>2"
- [(set (attr "neon_type")
+ [(set (attr "type")
(if_then_else (match_test "<Is_d_reg>")
(const_string "neon_bp_simple")
(const_string "neon_bp_3cycle")))]
UNSPEC_VLD1))]
"TARGET_NEON"
"vld1.<V_sz_elem>\t%h0, %A1"
- [(set_attr "neon_type" "neon_vld1_1_2_regs")]
+ [(set_attr "type" "neon_vld1_1_2_regs")]
)
(define_insn "neon_vld1_lane<mode>"
else
return "vld1.<V_sz_elem>\t{%P0[%c3]}, %A1";
}
- [(set (attr "neon_type")
+ [(set (attr "type")
(if_then_else (eq (const_string "<V_mode_nunits>") (const_int 2))
(const_string "neon_vld1_1_2_regs")
(const_string "neon_vld1_vld2_lane")))]
else
return "vld1.<V_sz_elem>\t{%P0[%c3]}, %A1";
}
- [(set (attr "neon_type")
+ [(set (attr "type")
(if_then_else (eq (const_string "<V_mode_nunits>") (const_int 2))
(const_string "neon_vld1_1_2_regs")
(const_string "neon_vld1_vld2_lane")))]
(vec_duplicate:VD (match_operand:<V_elem> 1 "neon_struct_operand" "Um")))]
"TARGET_NEON"
"vld1.<V_sz_elem>\t{%P0[]}, %A1"
- [(set_attr "neon_type" "neon_vld2_2_regs_vld1_vld2_all_lanes")]
+ [(set_attr "type" "neon_vld2_2_regs_vld1_vld2_all_lanes")]
)
;; Special case for DImode. Treat it exactly like a simple load.
{
return "vld1.<V_sz_elem>\t{%e0[], %f0[]}, %A1";
}
- [(set_attr "neon_type" "neon_vld2_2_regs_vld1_vld2_all_lanes")]
+ [(set_attr "type" "neon_vld2_2_regs_vld1_vld2_all_lanes")]
)
(define_insn_and_split "neon_vld1_dupv2di"
DONE;
}
[(set_attr "length" "8")
- (set_attr "neon_type" "neon_vld2_2_regs_vld1_vld2_all_lanes")]
+ (set_attr "type" "neon_vld2_2_regs_vld1_vld2_all_lanes")]
)
(define_expand "vec_store_lanes<mode><mode>"
UNSPEC_VST1))]
"TARGET_NEON"
"vst1.<V_sz_elem>\t%h1, %A0"
- [(set_attr "neon_type" "neon_vst1_1_2_regs_vst2_2_regs")])
+ [(set_attr "type" "neon_vst1_1_2_regs_vst2_2_regs")])
(define_insn "neon_vst1_lane<mode>"
[(set (match_operand:<V_elem> 0 "neon_struct_operand" "=Um")
else
return "vst1.<V_sz_elem>\t{%P1[%c2]}, %A0";
}
- [(set (attr "neon_type")
+ [(set (attr "type")
(if_then_else (eq (const_string "<V_mode_nunits>") (const_int 1))
(const_string "neon_vst1_1_2_regs_vst2_2_regs")
(const_string "neon_vst1_vst2_lane")))])
else
return "vst1.<V_sz_elem>\t{%P1[%c2]}, %A0";
}
- [(set_attr "neon_type" "neon_vst1_vst2_lane")]
+ [(set_attr "type" "neon_vst1_vst2_lane")]
)
(define_expand "vec_load_lanesti<mode>"
else
return "vld2.<V_sz_elem>\t%h0, %A1";
}
- [(set (attr "neon_type")
+ [(set (attr "type")
(if_then_else (eq (const_string "<V_sz_elem>") (const_string "64"))
(const_string "neon_vld1_1_2_regs")
(const_string "neon_vld2_2_regs_vld1_vld2_all_lanes")))]
UNSPEC_VLD2))]
"TARGET_NEON"
"vld2.<V_sz_elem>\t%h0, %A1"
- [(set_attr "neon_type" "neon_vld2_2_regs_vld1_vld2_all_lanes")])
+ [(set_attr "type" "neon_vld2_2_regs_vld1_vld2_all_lanes")])
(define_insn "neon_vld2_lane<mode>"
[(set (match_operand:TI 0 "s_register_operand" "=w")
output_asm_insn ("vld2.<V_sz_elem>\t{%P0[%c3], %P1[%c3]}, %A2", ops);
return "";
}
- [(set_attr "neon_type" "neon_vld1_vld2_lane")]
+ [(set_attr "type" "neon_vld1_vld2_lane")]
)
(define_insn "neon_vld2_lane<mode>"
output_asm_insn ("vld2.<V_sz_elem>\t{%P0[%c3], %P1[%c3]}, %A2", ops);
return "";
}
- [(set_attr "neon_type" "neon_vld1_vld2_lane")]
+ [(set_attr "type" "neon_vld1_vld2_lane")]
)
(define_insn "neon_vld2_dup<mode>"
else
return "vld1.<V_sz_elem>\t%h0, %A1";
}
- [(set (attr "neon_type")
+ [(set (attr "type")
(if_then_else (gt (const_string "<V_mode_nunits>") (const_string "1"))
(const_string "neon_vld2_2_regs_vld1_vld2_all_lanes")
(const_string "neon_vld1_1_2_regs")))]
else
return "vst2.<V_sz_elem>\t%h1, %A0";
}
- [(set (attr "neon_type")
+ [(set (attr "type")
(if_then_else (eq (const_string "<V_sz_elem>") (const_string "64"))
(const_string "neon_vst1_1_2_regs_vst2_2_regs")
(const_string "neon_vst1_1_2_regs_vst2_2_regs")))]
UNSPEC_VST2))]
"TARGET_NEON"
"vst2.<V_sz_elem>\t%h1, %A0"
- [(set_attr "neon_type" "neon_vst1_1_2_regs_vst2_2_regs")]
+ [(set_attr "type" "neon_vst1_1_2_regs_vst2_2_regs")]
)
(define_insn "neon_vst2_lane<mode>"
output_asm_insn ("vst2.<V_sz_elem>\t{%P1[%c3], %P2[%c3]}, %A0", ops);
return "";
}
- [(set_attr "neon_type" "neon_vst1_vst2_lane")]
+ [(set_attr "type" "neon_vst1_vst2_lane")]
)
(define_insn "neon_vst2_lane<mode>"
output_asm_insn ("vst2.<V_sz_elem>\t{%P1[%c3], %P2[%c3]}, %A0", ops);
return "";
}
- [(set_attr "neon_type" "neon_vst1_vst2_lane")]
+ [(set_attr "type" "neon_vst1_vst2_lane")]
)
(define_expand "vec_load_lanesei<mode>"
else
return "vld3.<V_sz_elem>\t%h0, %A1";
}
- [(set (attr "neon_type")
+ [(set (attr "type")
(if_then_else (eq (const_string "<V_sz_elem>") (const_string "64"))
(const_string "neon_vld1_1_2_regs")
(const_string "neon_vld3_vld4")))]
output_asm_insn ("vld3.<V_sz_elem>\t{%P0, %P1, %P2}, %A3", ops);
return "";
}
- [(set_attr "neon_type" "neon_vld3_vld4")]
+ [(set_attr "type" "neon_vld3_vld4")]
)
(define_insn "neon_vld3qb<mode>"
output_asm_insn ("vld3.<V_sz_elem>\t{%P0, %P1, %P2}, %A3", ops);
return "";
}
- [(set_attr "neon_type" "neon_vld3_vld4")]
+ [(set_attr "type" "neon_vld3_vld4")]
)
(define_insn "neon_vld3_lane<mode>"
ops);
return "";
}
- [(set_attr "neon_type" "neon_vld3_vld4_lane")]
+ [(set_attr "type" "neon_vld3_vld4_lane")]
)
(define_insn "neon_vld3_lane<mode>"
ops);
return "";
}
- [(set_attr "neon_type" "neon_vld3_vld4_lane")]
+ [(set_attr "type" "neon_vld3_vld4_lane")]
)
(define_insn "neon_vld3_dup<mode>"
else
return "vld1.<V_sz_elem>\t%h0, %A1";
}
- [(set (attr "neon_type")
+ [(set (attr "type")
(if_then_else (gt (const_string "<V_mode_nunits>") (const_string "1"))
(const_string "neon_vld3_vld4_all_lanes")
(const_string "neon_vld1_1_2_regs")))])
else
return "vst3.<V_sz_elem>\t%h1, %A0";
}
- [(set (attr "neon_type")
+ [(set (attr "type")
(if_then_else (eq (const_string "<V_sz_elem>") (const_string "64"))
(const_string "neon_vst1_1_2_regs_vst2_2_regs")
(const_string "neon_vst2_4_regs_vst3_vst4")))])
output_asm_insn ("vst3.<V_sz_elem>\t{%P1, %P2, %P3}, %A0", ops);
return "";
}
- [(set_attr "neon_type" "neon_vst2_4_regs_vst3_vst4")]
+ [(set_attr "type" "neon_vst2_4_regs_vst3_vst4")]
)
(define_insn "neon_vst3qb<mode>"
output_asm_insn ("vst3.<V_sz_elem>\t{%P1, %P2, %P3}, %A0", ops);
return "";
}
- [(set_attr "neon_type" "neon_vst2_4_regs_vst3_vst4")]
+ [(set_attr "type" "neon_vst2_4_regs_vst3_vst4")]
)
(define_insn "neon_vst3_lane<mode>"
ops);
return "";
}
- [(set_attr "neon_type" "neon_vst3_vst4_lane")]
+ [(set_attr "type" "neon_vst3_vst4_lane")]
)
(define_insn "neon_vst3_lane<mode>"
ops);
return "";
}
-[(set_attr "neon_type" "neon_vst3_vst4_lane")])
+[(set_attr "type" "neon_vst3_vst4_lane")])
(define_expand "vec_load_lanesoi<mode>"
[(set (match_operand:OI 0 "s_register_operand")
else
return "vld4.<V_sz_elem>\t%h0, %A1";
}
- [(set (attr "neon_type")
+ [(set (attr "type")
(if_then_else (eq (const_string "<V_sz_elem>") (const_string "64"))
(const_string "neon_vld1_1_2_regs")
(const_string "neon_vld3_vld4")))]
output_asm_insn ("vld4.<V_sz_elem>\t{%P0, %P1, %P2, %P3}, %A4", ops);
return "";
}
- [(set_attr "neon_type" "neon_vld3_vld4")]
+ [(set_attr "type" "neon_vld3_vld4")]
)
(define_insn "neon_vld4qb<mode>"
output_asm_insn ("vld4.<V_sz_elem>\t{%P0, %P1, %P2, %P3}, %A4", ops);
return "";
}
- [(set_attr "neon_type" "neon_vld3_vld4")]
+ [(set_attr "type" "neon_vld3_vld4")]
)
(define_insn "neon_vld4_lane<mode>"
ops);
return "";
}
- [(set_attr "neon_type" "neon_vld3_vld4_lane")]
+ [(set_attr "type" "neon_vld3_vld4_lane")]
)
(define_insn "neon_vld4_lane<mode>"
ops);
return "";
}
- [(set_attr "neon_type" "neon_vld3_vld4_lane")]
+ [(set_attr "type" "neon_vld3_vld4_lane")]
)
(define_insn "neon_vld4_dup<mode>"
else
return "vld1.<V_sz_elem>\t%h0, %A1";
}
- [(set (attr "neon_type")
+ [(set (attr "type")
(if_then_else (gt (const_string "<V_mode_nunits>") (const_string "1"))
(const_string "neon_vld3_vld4_all_lanes")
(const_string "neon_vld1_1_2_regs")))]
else
return "vst4.<V_sz_elem>\t%h1, %A0";
}
- [(set (attr "neon_type")
+ [(set (attr "type")
(if_then_else (eq (const_string "<V_sz_elem>") (const_string "64"))
(const_string "neon_vst1_1_2_regs_vst2_2_regs")
(const_string "neon_vst2_4_regs_vst3_vst4")))]
output_asm_insn ("vst4.<V_sz_elem>\t{%P1, %P2, %P3, %P4}, %A0", ops);
return "";
}
- [(set_attr "neon_type" "neon_vst2_4_regs_vst3_vst4")]
+ [(set_attr "type" "neon_vst2_4_regs_vst3_vst4")]
)
(define_insn "neon_vst4qb<mode>"
output_asm_insn ("vst4.<V_sz_elem>\t{%P1, %P2, %P3, %P4}, %A0", ops);
return "";
}
- [(set_attr "neon_type" "neon_vst2_4_regs_vst3_vst4")]
+ [(set_attr "type" "neon_vst2_4_regs_vst3_vst4")]
)
(define_insn "neon_vst4_lane<mode>"
ops);
return "";
}
- [(set_attr "neon_type" "neon_vst3_vst4_lane")]
+ [(set_attr "type" "neon_vst3_vst4_lane")]
)
(define_insn "neon_vst4_lane<mode>"
ops);
return "";
}
- [(set_attr "neon_type" "neon_vst3_vst4_lane")]
+ [(set_attr "type" "neon_vst3_vst4_lane")]
)
(define_expand "neon_vand<mode>"
(match_operand:VU 2 "vect_par_constant_low" ""))))]
"TARGET_NEON && !BYTES_BIG_ENDIAN"
"vmovl.<US><V_sz_elem> %q0, %e1"
- [(set_attr "neon_type" "neon_shift_1")]
+ [(set_attr "type" "neon_shift_1")]
)
(define_insn "neon_vec_unpack<US>_hi_<mode>"
(match_operand:VU 2 "vect_par_constant_high" ""))))]
"TARGET_NEON && !BYTES_BIG_ENDIAN"
"vmovl.<US><V_sz_elem> %q0, %f1"
- [(set_attr "neon_type" "neon_shift_1")]
+ [(set_attr "type" "neon_shift_1")]
)
(define_expand "vec_unpack<US>_hi_<mode>"
(match_dup 2)))))]
"TARGET_NEON && !BYTES_BIG_ENDIAN"
"vmull.<US><V_sz_elem> %q0, %e1, %e3"
- [(set_attr "neon_type" "neon_shift_1")]
+ [(set_attr "type" "neon_shift_1")]
)
(define_expand "vec_widen_<US>mult_lo_<mode>"
(match_dup 2)))))]
"TARGET_NEON && !BYTES_BIG_ENDIAN"
"vmull.<US><V_sz_elem> %q0, %f1, %f3"
- [(set_attr "neon_type" "neon_shift_1")]
+ [(set_attr "type" "neon_shift_1")]
)
(define_expand "vec_widen_<US>mult_hi_<mode>"
{
return "vshll.<US><V_sz_elem> %q0, %P1, %2";
}
- [(set_attr "neon_type" "neon_shift_1")]
+ [(set_attr "type" "neon_shift_1")]
)
(define_expand "vec_widen_<US>shiftl_lo_<mode>"
(SE:<V_widen> (match_operand:VDI 1 "register_operand" "w")))]
"TARGET_NEON"
"vmovl.<US><V_sz_elem> %q0, %P1"
- [(set_attr "neon_type" "neon_shift_1")]
+ [(set_attr "type" "neon_shift_1")]
)
(define_expand "vec_unpack<US>_lo_<mode>"
(match_operand:VDI 2 "register_operand" "w"))))]
"TARGET_NEON"
"vmull.<US><V_sz_elem> %q0, %P1, %P2"
- [(set_attr "neon_type" "neon_shift_1")]
+ [(set_attr "type" "neon_shift_1")]
)
(define_expand "vec_widen_<US>mult_hi_<mode>"
(match_operand:VN 2 "register_operand" "w"))))]
"TARGET_NEON && !BYTES_BIG_ENDIAN"
"vmovn.i<V_sz_elem>\t%e0, %q1\;vmovn.i<V_sz_elem>\t%f0, %q2"
- [(set_attr "neon_type" "neon_shift_1")
+ [(set_attr "type" "neon_shift_1")
(set_attr "length" "8")]
)
(truncate:<V_narrow> (match_operand:VN 1 "register_operand" "w")))]
"TARGET_NEON && !BYTES_BIG_ENDIAN"
"vmovn.i<V_sz_elem>\t%P0, %q1"
- [(set_attr "neon_type" "neon_shift_1")]
+ [(set_attr "type" "neon_shift_1")]
)
(define_expand "vec_pack_trunc_<mode>"
(match_operand:VDQ 2 "s_register_operand" "w"))))]
"TARGET_NEON && (!<Is_float_mode> || flag_unsafe_math_optimizations)"
"vabd.<V_s_elem> %<V_reg>0, %<V_reg>1, %<V_reg>2"
- [(set (attr "neon_type")
+ [(set (attr "type")
(if_then_else (ne (symbol_ref "<Is_float_mode>") (const_int 0))
(if_then_else (ne (symbol_ref "<Is_d_reg>") (const_int 0))
(const_string "neon_fp_vadd_ddd_vabs_dd")
UNSPEC_VSUB)))]
"TARGET_NEON && (!<Is_float_mode> || flag_unsafe_math_optimizations)"
"vabd.<V_if_elem> %<V_reg>0, %<V_reg>1, %<V_reg>2"
- [(set (attr "neon_type")
+ [(set (attr "type")
(if_then_else (ne (symbol_ref "<Is_float_mode>") (const_int 0))
(if_then_else (ne (symbol_ref "<Is_d_reg>") (const_int 0))
(const_string "neon_fp_vadd_ddd_vabs_dd")
; call subroutine call.
; clz count leading zeros (CLZ).
; extend extend instruction (SXTB, SXTH, UXTB, UXTH).
-; f_2_r transfer from float to core (no memory needed).
; f_cvt conversion between float and integral.
; f_flag transfer of co-processor flags to the CPSR.
; f_load[d,s] double/single load from memory. Used for VFP unit.
+; f_mcr transfer arm to vfp reg.
+; f_mcrr transfer two arm regs to vfp reg.
; f_minmax[d,s] double/single floating point minimum/maximum.
+; f_mrc transfer vfp to arm reg.
+; f_mrrc transfer vfp to two arm regs.
; f_rint[d,s] double/single floating point rount to integral.
; f_sel[d,s] double/single floating byte select.
; f_store[d,s] double/single store to memory. Used for VFP unit.
; mvn_reg inverting move instruction, register.
; mvn_shift inverting move instruction, shifted operand by a constant.
; mvn_shift_reg inverting move instruction, shifted operand by a register.
-; r_2_f transfer from core to float.
; sdiv signed division.
; shift simple shift operation (LSL, LSR, ASR, ROR) with an
; immediate.
; wmmx_wunpckih
; wmmx_wunpckil
; wmmx_wxor
+;
+; The classification below is for NEON instructions.
+;
+; neon_bp_2cycle
+; neon_bp_3cycle
+; neon_bp_simple
+; neon_fp_vadd_ddd_vabs_dd
+; neon_fp_vadd_qqq_vabs_qq
+; neon_fp_vmla_ddd_scalar
+; neon_fp_vmla_ddd
+; neon_fp_vmla_qqq_scalar
+; neon_fp_vmla_qqq
+; neon_fp_vmul_ddd
+; neon_fp_vmul_qqd
+; neon_fp_vrecps_vrsqrts_ddd
+; neon_fp_vrecps_vrsqrts_qqq
+; neon_fp_vsum
+; neon_int_1
+; neon_int_2
+; neon_int_3
+; neon_int_4
+; neon_int_5
+; neon_ldm_2
+; neon_ldr
+; neon_mcr_2_mcrr
+; neon_mcr
+; neon_mla_ddd_16_scalar_qdd_32_16_long_scalar
+; neon_mla_ddd_32_qqd_16_ddd_32_scalar_qdd_64_32_long_scalar_qdd_64_32_long
+; neon_mla_ddd_8_16_qdd_16_8_long_32_16_long
+; neon_mla_qqq_32_qqd_32_scalar
+; neon_mla_qqq_8_16
+; neon_mrc
+; neon_mrrc
+; neon_mul_ddd_16_scalar_32_16_long_scalar
+; neon_mul_ddd_8_16_qdd_16_8_long_32_16_long
+; neon_mul_qdd_64_32_long_qqd_16_ddd_32_scalar_64_32_long_scalar
+; neon_mul_qqd_32_scalar
+; neon_mul_qqq_8_16_32_ddd_32
+; neon_shift_1
+; neon_shift_2
+; neon_shift_3
+; neon_stm_2
+; neon_str
+; neon_vaba_qqq
+; neon_vaba
+; neon_vld1_1_2_regs
+; neon_vld1_3_4_regs
+; neon_vld1_vld2_lane
+; neon_vld2_2_regs_vld1_vld2_all_lanes
+; neon_vld2_4_regs
+; neon_vld3_vld4_all_lanes
+; neon_vld3_vld4_lane
+; neon_vld3_vld4
+; neon_vmov
+; neon_vqneg_vqabs
+; neon_vqshl_vrshl_vqrshl_qqq
+; neon_vshl_ddd
+; neon_vsma
+; neon_vsra_vrsra
+; neon_vst1_1_2_regs_vst2_2_regs
+; neon_vst1_3_4_regs
+; neon_vst1_vst2_lane
+; neon_vst2_4_regs_vst3_vst4
+; neon_vst3_vst4_lane
+; neon_vst3_vst4
(define_attr "type"
"arlo_imm,\
call,\
clz,\
extend,\
- f_2_r,\
f_cvt,\
f_flag,\
f_loadd,\
f_loads,\
+ f_mcr,\
+ f_mcrr,\
f_minmaxd,\
f_minmaxs,\
+ f_mrc,\
+ f_mrrc,\
f_rintd,\
f_rints,\
f_seld,\
mvn_reg,\
mvn_shift,\
mvn_shift_reg,\
- r_2_f,\
sdiv,\
shift,\
shift_reg,\
wmmx_wunpckel,\
wmmx_wunpckih,\
wmmx_wunpckil,\
- wmmx_wxor"
- (const_string "arlo_reg"))
+ wmmx_wxor,\
+ neon_bp_2cycle,\
+ neon_bp_3cycle,\
+ neon_bp_simple,\
+ neon_fp_vadd_ddd_vabs_dd,\
+ neon_fp_vadd_qqq_vabs_qq,\
+ neon_fp_vmla_ddd_scalar,\
+ neon_fp_vmla_ddd,\
+ neon_fp_vmla_qqq_scalar,\
+ neon_fp_vmla_qqq,\
+ neon_fp_vmul_ddd,\
+ neon_fp_vmul_qqd,\
+ neon_fp_vrecps_vrsqrts_ddd,\
+ neon_fp_vrecps_vrsqrts_qqq,\
+ neon_fp_vsum,\
+ neon_int_1,\
+ neon_int_2,\
+ neon_int_3,\
+ neon_int_4,\
+ neon_int_5,\
+ neon_ldm_2,\
+ neon_ldr,\
+ neon_mcr_2_mcrr,\
+ neon_mcr,\
+ neon_mla_ddd_16_scalar_qdd_32_16_long_scalar,\
+ neon_mla_ddd_32_qqd_16_ddd_32_scalar_qdd_64_32_long_scalar_qdd_64_32_long,\
+ neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\
+ neon_mla_qqq_32_qqd_32_scalar,\
+ neon_mla_qqq_8_16,\
+ neon_mrc,\
+ neon_mrrc,\
+ neon_mul_ddd_16_scalar_32_16_long_scalar,\
+ neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\
+ neon_mul_qdd_64_32_long_qqd_16_ddd_32_scalar_64_32_long_scalar,\
+ neon_mul_qqd_32_scalar,\
+ neon_mul_qqq_8_16_32_ddd_32,\
+ neon_shift_1,\
+ neon_shift_2,\
+ neon_shift_3,\
+ neon_stm_2,\
+ neon_str,\
+ neon_vaba_qqq,\
+ neon_vaba,\
+ neon_vld1_1_2_regs,\
+ neon_vld1_3_4_regs,\
+ neon_vld1_vld2_lane,\
+ neon_vld2_2_regs_vld1_vld2_all_lanes,\
+ neon_vld2_4_regs,\
+ neon_vld3_vld4_all_lanes,\
+ neon_vld3_vld4_lane,\
+ neon_vld3_vld4,\
+ neon_vmov,\
+ neon_vqneg_vqabs,\
+ neon_vqshl_vrshl_vqrshl_qqq,\
+ neon_vshl_ddd,\
+ neon_vsma,\
+ neon_vsra_vrsra,\
+ neon_vst1_1_2_regs_vst2_2_regs,\
+ neon_vst1_3_4_regs,\
+ neon_vst1_vst2_lane,\
+ neon_vst2_4_regs_vst3_vst4,\
+ neon_vst3_vst4_lane,\
+ neon_vst3_vst4"
+ (const_string "arlo_reg"))
; Is this an (integer side) multiply with a 32-bit (or smaller) result?
(define_attr "mul32" "no,yes"
}
"
[(set_attr "predicable" "yes")
- (set_attr "type" "mov_reg,mov_reg,mvn_imm,mov_imm,load1,store1,r_2_f,f_2_r,fcpys,f_loads,f_stores")
- (set_attr "neon_type" "*,*,*,*,*,*,neon_mcr,neon_mrc,neon_vmov,*,*")
+ (set_attr "type" "mov_reg,mov_reg,mvn_imm,mov_imm,load1,store1,f_mcr,f_mrc,fcpys,f_loads,f_stores")
(set_attr "pool_range" "*,*,*,*,4096,*,*,*,*,1020,*")
(set_attr "neg_pool_range" "*,*,*,*,4084,*,*,*,*,1008,*")]
)
"
[(set_attr "predicable" "yes")
(set_attr "predicable_short_it" "yes,no,yes,no,no,no,no,no,no,no,no,no,no,no")
- (set_attr "type" "mov_reg,mov_reg,mov_reg,mvn_reg,mov_reg,load1,load1,store1,store1,r_2_f,f_2_r,fcpys,f_loads,f_stores")
+ (set_attr "type" "mov_reg,mov_reg,mov_reg,mvn_reg,mov_reg,load1,load1,store1,store1,f_mcr,f_mrc,fcpys,f_loads,f_stores")
(set_attr "length" "2,4,2,4,4,4,4,4,4,4,4,4,4,4")
- (set_attr "neon_type" "*,*,*,*,*,*,*,*,*,neon_mcr,neon_mrc,neon_vmov,*,*")
(set_attr "pool_range" "*,*,*,*,*,1018,4094,*,*,*,*,*,1018,*")
(set_attr "neg_pool_range" "*,*,*,*,*, 0, 0,*,*,*,*,*,1008,*")]
)
gcc_unreachable ();
}
"
- [(set_attr "type" "*,*,*,*,load2,load2,store2,r_2_f,f_2_r,ffarithd,f_loadd,f_stored")
- (set_attr "neon_type" "*,*,*,*,*,*,*,neon_mcr_2_mcrr,neon_mrrc,neon_vmov,*,*")
+ [(set_attr "type" "*,*,*,*,load2,load2,store2,f_mcrr,f_mrrc,ffarithd,f_loadd,f_stored")
(set (attr "length") (cond [(eq_attr "alternative" "1,4,5,6") (const_int 8)
(eq_attr "alternative" "2") (const_int 12)
(eq_attr "alternative" "3") (const_int 16)
gcc_unreachable ();
}
"
- [(set_attr "type" "*,*,*,*,load2,load2,store2,r_2_f,f_2_r,ffarithd,f_loadd,f_stored")
- (set_attr "neon_type" "*,*,*,*,*,*,*,neon_mcr_2_mcrr,neon_mrrc,neon_vmov,*,*")
+ [(set_attr "type" "*,*,*,*,load2,load2,store2,f_mcrr,f_mrrc,ffarithd,f_loadd,f_stored")
(set (attr "length") (cond [(eq_attr "alternative" "1") (const_int 8)
(eq_attr "alternative" "2") (const_int 12)
(eq_attr "alternative" "3") (const_int 16)
}
"
[(set_attr "conds" "unconditional")
- (set_attr "type" "*,*,load1,store1,fcpys,*,r_2_f,f_2_r,*")
- (set_attr "neon_type" "neon_vld1_1_2_regs,neon_vst1_1_2_regs_vst2_2_regs,*,*,*,*,*,*,*")
+ (set_attr "type" "neon_vld1_1_2_regs,neon_vst1_1_2_regs_vst2_2_regs,\
+ load1,store1,fcpys,*,f_mcr,f_mrc,*")
(set_attr "length" "4,4,4,4,4,4,4,4,8")]
)
}
"
[(set_attr "conds" "unconditional")
- (set_attr "type" "load1,store1,fcpys,*,r_2_f,f_2_r,*")
+ (set_attr "type" "load1,store1,fcpys,*,f_mcr,f_mrc,*")
(set_attr "length" "4,4,4,4,4,4,8")]
)
"
[(set_attr "predicable" "yes")
(set_attr "type"
- "r_2_f,f_2_r,fconsts,f_loads,f_stores,load1,store1,fcpys,mov_reg")
- (set_attr "neon_type" "neon_mcr,neon_mrc,*,*,*,*,*,neon_vmov,*")
+ "f_mcr,f_mrc,fconsts,f_loads,f_stores,load1,store1,fcpys,mov_reg")
(set_attr "pool_range" "*,*,*,1020,*,4096,*,*,*")
(set_attr "neg_pool_range" "*,*,*,1008,*,4080,*,*,*")]
)
[(set_attr "predicable" "yes")
(set_attr "predicable_short_it" "no")
(set_attr "type"
- "r_2_f,f_2_r,fconsts,f_loads,f_stores,load1,store1,fcpys,mov_reg")
- (set_attr "neon_type" "neon_mcr,neon_mrc,*,*,*,*,*,neon_vmov,*")
+ "f_mcr,f_mrc,fconsts,f_loads,f_stores,load1,store1,fcpys,mov_reg")
(set_attr "pool_range" "*,*,*,1018,*,4090,*,*,*")
(set_attr "neg_pool_range" "*,*,*,1008,*,0,*,*,*")]
)
}
}
"
- [(set_attr "type"
- "r_2_f,f_2_r,fconstd,f_loadd,f_stored,load2,store2,ffarithd,*")
- (set_attr "neon_type" "neon_mcr_2_mcrr,neon_mrrc,*,*,*,*,*,neon_vmov,*")
+ [(set_attr "type" "f_mcrr,f_mrrc,fconstd,f_loadd,f_stored,\
+ load2,store2,ffarithd,*")
(set (attr "length") (cond [(eq_attr "alternative" "5,6,8") (const_int 8)
(eq_attr "alternative" "7")
(if_then_else
}
}
"
- [(set_attr "type"
- "r_2_f,f_2_r,fconstd,f_loadd,f_stored,load2,store2,ffarithd,*")
- (set_attr "neon_type" "neon_mcr_2_mcrr,neon_mrrc,*,*,*,*,*,neon_vmov,*")
+ [(set_attr "type" "f_mcrr,f_mrrc,fconstd,f_loadd,\
+ f_stored,load2,store2,ffarithd,*")
(set (attr "length") (cond [(eq_attr "alternative" "5,6,8") (const_int 8)
(eq_attr "alternative" "7")
(if_then_else
fmrs%D3\\t%0, %2\;fmrs%d3\\t%0, %1"
[(set_attr "conds" "use")
(set_attr "length" "4,4,8,4,4,8,4,4,8")
- (set_attr "type" "fcpys,fcpys,fcpys,r_2_f,r_2_f,r_2_f,f_2_r,f_2_r,f_2_r")
- (set_attr "neon_type" "neon_vmov,neon_vmov,neon_vmov,neon_mcr,neon_mcr,neon_mcr,neon_mrc,neon_mrc,neon_mrc")]
+ (set_attr "type" "fcpys,fcpys,fcpys,f_mcr,f_mcr,f_mcr,f_mrc,f_mrc,f_mrc")]
)
(define_insn "*thumb2_movsfcc_vfp"
ite\\t%D3\;fmrs%D3\\t%0, %2\;fmrs%d3\\t%0, %1"
[(set_attr "conds" "use")
(set_attr "length" "6,6,10,6,6,10,6,6,10")
- (set_attr "type" "fcpys,fcpys,fcpys,r_2_f,r_2_f,r_2_f,f_2_r,f_2_r,f_2_r")
- (set_attr "neon_type" "neon_vmov,neon_vmov,neon_vmov,neon_mcr,neon_mcr,neon_mcr,neon_mrc,neon_mrc,neon_mrc")]
+ (set_attr "type" "fcpys,fcpys,fcpys,f_mcr,f_mcr,f_mcr,f_mrc,f_mrc,f_mrc")]
)
(define_insn "*movdfcc_vfp"
fmrrd%D3\\t%Q0, %R0, %P2\;fmrrd%d3\\t%Q0, %R0, %P1"
[(set_attr "conds" "use")
(set_attr "length" "4,4,8,4,4,8,4,4,8")
- (set_attr "type" "ffarithd,ffarithd,ffarithd,r_2_f,r_2_f,r_2_f,f_2_r,f_2_r,f_2_r")
- (set_attr "neon_type" "neon_vmov,neon_vmov,neon_vmov,neon_mcr_2_mcrr,neon_mcr_2_mcrr,neon_mcr_2_mcrr,neon_mrrc,neon_mrrc,neon_mrrc")]
+ (set_attr "type" "ffarithd,ffarithd,ffarithd,f_mcr,f_mcr,f_mcr,f_mrrc,f_mrrc,f_mrrc")]
)
(define_insn "*thumb2_movdfcc_vfp"
ite\\t%D3\;fmrrd%D3\\t%Q0, %R0, %P2\;fmrrd%d3\\t%Q0, %R0, %P1"
[(set_attr "conds" "use")
(set_attr "length" "6,6,10,6,6,10,6,6,10")
- (set_attr "type" "ffarithd,ffarithd,ffarithd,r_2_f,r_2_f,r_2_f,f_2_r,f_2_r,f_2_r")
- (set_attr "neon_type" "neon_vmov,neon_vmov,neon_vmov,neon_mcr_2_mcrr,neon_mcr_2_mcrr,neon_mcr_2_mcrr,neon_mrrc,neon_mrrc,neon_mrrc")]
+ (set_attr "type" "ffarithd,ffarithd,ffarithd,f_mcr,f_mcr,f_mcr,f_mrrc,f_mrrc,f_mrrc")]
)
;; Moves to/from arm regs also use the load/store pipeline.
(define_insn_reservation "vfp_fload" 4
(and (eq_attr "generic_vfp" "yes")
- (eq_attr "type" "f_loads,f_loadd,r_2_f"))
+ (eq_attr "type" "f_loads,f_loadd,f_mcr,f_mcrr"))
"vfp_ls")
(define_insn_reservation "vfp_fstore" 4
(and (eq_attr "generic_vfp" "yes")
- (eq_attr "type" "f_stores,f_stored,f_2_r"))
+ (eq_attr "type" "f_stores,f_stored,f_mrc,f_mrrc"))
"vfp_ls")
(define_insn_reservation "vfp_to_cpsr" 4
QABSNEG))]
"TARGET_NEON"
"vq<absneg>.<V_s_elem>\t%<V_reg>0, %<V_reg>1"
- [(set_attr "neon_type" "neon_vqneg_vqabs")]
+ [(set_attr "type" "neon_vqneg_vqabs")]
)
@end smallexample
UNSPEC_VQABS))]
"TARGET_NEON"
"vqabs.<V_s_elem>\t%<V_reg>0, %<V_reg>1"
- [(set_attr "neon_type" "neon_vqneg_vqabs")]
+ [(set_attr "type" "neon_vqneg_vqabs")]
)
(define_insn "neon_vqneg<mode>"
UNSPEC_VQNEG))]
"TARGET_NEON"
"vqneg.<V_s_elem>\t%<V_reg>0, %<V_reg>1"
- [(set_attr "neon_type" "neon_vqneg_vqabs")]
+ [(set_attr "type" "neon_vqneg_vqabs")]
)
@end smallexample
git://gcc.gnu.org / gcc.git / commitdiff