+.I "\s-1IA-64\s0 Options"
+.IX Subsection "IA-64 Options"
+.PP
+These are the \fB\-m\fR options defined for the Intel \s-1IA-64\s0 architecture.
+.Ip "\fB\-mbig-endian\fR" 4
+.IX Item "-mbig-endian"
+Generate code for a big endian target. This is the default for \s-1HPUX\s0.
+.Ip "\fB\-mlittle-endian\fR" 4
+.IX Item "-mlittle-endian"
+Generate code for a little endian target. This is the default for \s-1AIX5\s0
+and Linux.
+.Ip "\fB\-mgnu-as\fR" 4
+.IX Item "-mgnu-as"
+.PD 0
+.Ip "\fB\-mno-gnu-as\fR" 4
+.IX Item "-mno-gnu-as"
+.PD
+Generate (or don't) code for the \s-1GNU\s0 assembler. This is the default.
+.Ip "\fB\-mgnu-ld\fR" 4
+.IX Item "-mgnu-ld"
+.PD 0
+.Ip "\fB\-mno-gnu-ld\fR" 4
+.IX Item "-mno-gnu-ld"
+.PD
+Generate (or don't) code for the \s-1GNU\s0 linker. This is the default.
+.Ip "\fB\-mno-pic\fR" 4
+.IX Item "-mno-pic"
+Generate code that does not use a global pointer register. The result
+is not position independent code, and violates the \s-1IA-64\s0 \s-1ABI\s0.
+.Ip "\fB\-mvolatile-asm-stop\fR" 4
+.IX Item "-mvolatile-asm-stop"
+.PD 0
+.Ip "\fB\-mno-volatile-asm-stop\fR" 4
+.IX Item "-mno-volatile-asm-stop"
+.PD
+Generate (or don't) a stop bit immediately before and after volatile asm
+statements.
+.Ip "\fB\-mb-step\fR" 4
+.IX Item "-mb-step"
+Generate code that works around Itanium B step errata.
+.Ip "\fB\-mregister-names\fR" 4
+.IX Item "-mregister-names"
+.PD 0
+.Ip "\fB\-mno-register-names\fR" 4
+.IX Item "-mno-register-names"
+.PD
+Generate (or don't) \fBin\fR, \fBloc\fR, and \fBout\fR register names for
+the stacked registers. This may make assembler output more readable.
+.Ip "\fB\-mno-sdata\fR" 4
+.IX Item "-mno-sdata"
+.PD 0
+.Ip "\fB\-msdata\fR" 4
+.IX Item "-msdata"
+.PD
+Disable (or enable) optimizations that use the small data section. This may
+be useful for working around optimizer bugs.
+.Ip "\fB\-mconstant-gp\fR" 4
+.IX Item "-mconstant-gp"
+Generate code that uses a single constant global pointer value. This is
+useful when compiling kernel code.
+.Ip "\fB\-mauto-pic\fR" 4
+.IX Item "-mauto-pic"
+Generate code that is self-relocatable. This implies \fB\-mconstant-gp\fR.
+This is useful when compiling firmware code.
+.Ip "\fB\-minline-divide-min-latency\fR" 4
+.IX Item "-minline-divide-min-latency"
+Generate code for inline divides using the minimum latency algorithm.
+.Ip "\fB\-minline-divide-max-throughput\fR" 4
+.IX Item "-minline-divide-max-throughput"
+Generate code for inline divides using the maximum throughput algorithm.
+.Ip "\fB\-mno-dwarf2\-asm\fR" 4
+.IX Item "-mno-dwarf2-asm"
+.PD 0
+.Ip "\fB\-mdwarf2\-asm\fR" 4
+.IX Item "-mdwarf2-asm"
+.PD
+Don't (or do) generate assembler code for the \s-1DWARF2\s0 line number debugging
+info. This may be useful when not using the \s-1GNU\s0 assembler.
+.Ip "\fB\-mfixed-range=\fR\fIregister range\fR" 4
+.IX Item "-mfixed-range=register range"
+Generate code treating the given register range as fixed registers.
+A fixed register is one that the register allocator can not use. This is
+useful when compiling kernel code. A register range is specified as
+two registers separated by a dash. Multiple register ranges can be
+specified separated by a comma.
+.PP