RISC-V: Add VLS widen binary combine patterns

RISC-V: Add VLS widen binary combine patterns

Regression passed.

Committed.

gcc/ChangeLog:

	* config/riscv/vector-iterators.md: Extend VLS modes.

gcc/testsuite/ChangeLog:

	* gcc.target/riscv/rvv/autovec/vls/def.h: Add VLS modes cond tests.
	* gcc.target/riscv/rvv/autovec/vls/wadd-1.c: New test.
	* gcc.target/riscv/rvv/autovec/vls/wadd-2.c: New test.
	* gcc.target/riscv/rvv/autovec/vls/wadd-3.c: New test.
	* gcc.target/riscv/rvv/autovec/vls/wadd-4.c: New test.
	* gcc.target/riscv/rvv/autovec/vls/wmul-1.c: New test.
	* gcc.target/riscv/rvv/autovec/vls/wmul-2.c: New test.
	* gcc.target/riscv/rvv/autovec/vls/wmul-3.c: New test.
	* gcc.target/riscv/rvv/autovec/vls/wsub-1.c: New test.
	* gcc.target/riscv/rvv/autovec/vls/wsub-2.c: New test.
	* gcc.target/riscv/rvv/autovec/vls/wsub-3.c: New test.
	* gcc.target/riscv/rvv/autovec/vls/wsub-4.c: New test.