[APX EGPR] Handle vex insns that only support GPR16 (5/5)

[APX EGPR] Handle vex insns that only support GPR16 (5/5)

These vex insn may have legacy counterpart that could support EGPR,
but they do not have evex counterpart. Split out its vex part from
patterns and set the vex part to non-EGPR supported by adjusting
constraints and attr_gpr32.

insn list:
1. vmovmskpd/vmovmskps
2. vpmovmskb
3. vrsqrtss/vrsqrtps
4. vrcpss/vrcpps
5. vhaddpd/vhaddps, vhsubpd/vhsubps
6. vldmxcsr/vstmxcsr
7. vaddsubpd/vaddsubps
8. vlddqu
9. vtestps/vtestpd
10. vmaskmovps/vmaskmovpd, vpmaskmovd/vpmaskmovq
11. vperm2f128/vperm2i128
12. vinserti128/vinsertf128
13. vbroadcasti128/vbroadcastf128
14. vcmppd/vcmpps, vcmpss/vcmpsd
15. vgatherdps/vgatherqps, vgatherdpd/vgatherqpd

gcc/ChangeLog:

	* config/i386/constraints.md (jb): New constraint for vsib memory
	that does not allow gpr32.
	* config/i386/i386.md: (setcc_<mode>_sse): Replace m to jm for avx
	alternative and set attr_gpr32 to 0.
	(movmsk_df): Split avx/noavx alternatives and  replace "r" to "jr" for
	avx alternative.
	(<sse>_rcp<mode>2): Split avx/noavx alternatives and replace
	"m/Bm" to "jm/ja" for avx alternative, set its gpr32 attr to 0.
	(*rsqrtsf2_sse): Likewise.
	* config/i386/mmx.md (mmx_pmovmskb): Split alternative 1 to
	avx/noavx and assign jr/r constraint to dest.
	* config/i386/sse.md (<sse>_movmsk<ssemodesuffix><avxsizesuffix>):
	Split avx/noavx alternatives and replace "r" to "jr" for avx alternative.
	(*<sse>_movmsk<ssemodesuffix><avxsizesuffix>_<u>ext): Likewise.
	(*<sse>_movmsk<ssemodesuffix><avxsizesuffix>_lt): Likewise.
	(*<sse>_movmsk<ssemodesuffix><avxsizesuffix>_<u>ext_lt): Likewise.
	(*<sse>_movmsk<ssemodesuffix><avxsizesuffix>_shift): Likewise.
	(*<sse>_movmsk<ssemodesuffix><avxsizesuffix>_<u>ext_shift): Likewise.
	(<sse2_avx2>_pmovmskb): Likewise.
	(*<sse2_avx2>_pmovmskb_zext): Likewise.
	(*sse2_pmovmskb_ext): Likewise.
	(*<sse2_avx2>_pmovmskb_lt): Likewise.
	(*<sse2_avx2>_pmovmskb_zext_lt): Likewise.
	(*sse2_pmovmskb_ext_lt): Likewise.
	(<sse>_rcp<mode>2): Split avx/noavx alternatives and replace
	"m/Bm" to "jm/ja" for avx alternative, set its attr_gpr32 to 0.
	(sse_vmrcpv4sf2): Likewise.
	(*sse_vmrcpv4sf2): Likewise.
	(rsqrt<mode>2): Likewise.
	(sse_vmrsqrtv4sf2): Likewise.
	(*sse_vmrsqrtv4sf2): Likewise.
	(avx_h<insn>v4df3): Likewise.
	(sse3_hsubv2df3): Likewise.
	(avx_h<insn>v8sf3): Likewise.
	(sse3_h<insn>v4sf3): Likewise.
	(<sse3>_lddqu<avxsizesuffix>): Likewise.
	(avx_cmp<mode>3): Likewise.
	(avx_vmcmp<mode>3): Likewise.
	(*sse2_gt<mode>3): Likewise.
	(sse_ldmxcsr): Likewise.
	(sse_stmxcsr): Likewise.
	(avx_vtest<ssemodesuffix><avxsizesuffix>): Replace m to jm for
	avx alternative and set attr_gpr32 to 0.
	(avx2_permv2ti): Likewise.
	(*avx_vperm2f128<mode>_full): Likewise.
	(*avx_vperm2f128<mode>_nozero): Likewise.
	(vec_set_lo_v32qi): Likewise.
	(<avx_avx2>_maskload<ssemodesuffix><avxsizesuffix>): Likewise.
	(<avx_avx2>_maskstore<ssemodesuffix><avxsi)zesuffix>: Likewise.
	(avx_cmp<mode>3): Likewise.
	(avx_vmcmp<mode>3): Likewise.
	(*<sse>_maskcmp<mode>3_comm): Likewise.
	(*avx2_gathersi<VEC_GATHER_MODE:mode>): Replace Tv to jb and set
	attr_gpr32 to 0.
	(*avx2_gathersi<VEC_GATHER_MODE:mode>_2): Likewise.
	(*avx2_gatherdi<VEC_GATHER_MODE:mode>): Likewise.
	(*avx2_gatherdi<VEC_GATHER_MODE:mode>_2): Likewise.
	(*avx2_gatherdi<VI4F_256:mode>_3): Likewise.
	(*avx2_gatherdi<VI4F_256:mode>_4): Likewise.
	(avx_vbroadcastf128_<mode>): Restrict non-egpr alternative to
	noavx512vl, set its constraint to jm and set attr_gpr32 to 0.
	(vec_set_lo_<mode><mask_name>): Likewise.
	(vec_set_lo_<mode><mask_name>): Likewise for SF/SI modes.
	(vec_set_hi_<mode><mask_name>): Likewise.
	(vec_set_hi_<mode><mask_name>): Likewise for SF/SI modes.
	(vec_set_hi_<mode>): Likewise.
	(vec_set_lo_<mode>): Likewise.
	(avx2_set_hi_v32qi): Likewise.

Co-authored-by: Hongyu Wang <hongyu.wang@intel.com>
Co-authored-by: Hongtao Liu <hongtao.liu@intel.com>