re PR target/19235 (GCC generates SSE2 instructions for AthlonXP which doesn't suppor...

re PR target/19235 (GCC generates SSE2 instructions for AthlonXP which doesn't support them.)

        PR target/19235
        * config/i386/i386.md (movdi_2): Separate SSE1 and SSE2 alternatives.
        (mov<MMXMODEI>_internal): Likewise.
        (movdf_nointeger): Prefer Y while not preferring, but allowing, x.
        Add V2SF case; use it for SSE1; don't use TI.
        (movdf_integer): Likewise.
        (mov<SSEMODEI>_internal, movti_internal): Force V4SF for SSE1.

From-SVN: r92889