RISC-V: Refine the condition for add additional vars in RVV cost model

RISC-V: Refine the condition for add additional vars in RVV cost model

The adjacent_dr_p is sufficient and unnecessary condition for contiguous access.
So unnecessary live-ranges are added and result in smaller LMUL.

This patch uses MEMORY_ACCESS_TYPE as condition and constrains segment
load/store.

Tested on RV64 and no regression.

	PR target/114506

gcc/ChangeLog:

	* config/riscv/riscv-vector-costs.cc (non_contiguous_memory_access_p): Rename
	(need_additional_vector_vars_p): Rename and refine condition

gcc/testsuite/ChangeLog:

	* gcc.dg/vect/costmodel/riscv/rvv/pr114506.c: New test.

Signed-off-by: demin.han <demin.han@starfivetech.com>