RISC-V: Fix VSETVL VL check condition bug

RISC-V: Fix VSETVL VL check condition bug

When fixing the induction variable vectorization bug, notice there is a ICE bug
in VSETVL PASS:

0x178015b rtl_check_failed_code1(rtx_def const*, rtx_code, char const*, int, char const*)
        ../../../../gcc/gcc/rtl.cc:770
0x1079cdd rhs_regno(rtx_def const*)
        ../../../../gcc/gcc/rtl.h:1934
0x1dab360 vsetvl_info::parse_insn(rtl_ssa::insn_info*)
        ../../../../gcc/gcc/config/riscv/riscv-vsetvl.cc:1070
0x1daa272 vsetvl_info::vsetvl_info(rtl_ssa::insn_info*)
        ../../../../gcc/gcc/config/riscv/riscv-vsetvl.cc:746
0x1da5d98 pre_vsetvl::fuse_local_vsetvl_info()
        ../../../../gcc/gcc/config/riscv/riscv-vsetvl.cc:2708
0x1da94d9 pass_vsetvl::lazy_vsetvl()
        ../../../../gcc/gcc/config/riscv/riscv-vsetvl.cc:3444
0x1da977c pass_vsetvl::execute(function*)
        ../../../../gcc/gcc/config/riscv/riscv-vsetvl.cc:3504

Committed as it is obvious.

gcc/ChangeLog:

	* config/riscv/riscv-vsetvl.cc: Fix ICE.

gcc/testsuite/ChangeLog:

	* gcc.target/riscv/rvv/base/vl-use-ice.c: New test.