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RISC-V: Fix one typo in full-vec-movel test
authorPan Li <pan2.li@intel.com>
Tue, 13 Jun 2023 07:13:48 +0000 (15:13 +0800)
committerPan Li <pan2.li@intel.com>
Tue, 13 Jun 2023 07:26:34 +0000 (15:26 +0800)
commit95e2a51685d5ce977c332735ddc5ef39e777639e
tree435bc6943038b99cc5877bf1e7a650009d2c3020tree
parent22d85c10a004f4f5eaf6b68b62a0792faf048bf8commit | diff
RISC-V: Fix one typo in full-vec-movel test

This patch would like to fix one typo when checking assembly of
full-vec-movel.

Signed-off-by: Pan Li <pan2.li@intel.com>
gcc/testsuite/ChangeLog:

* gcc.target/riscv/rvv/autovec/vls-vlmax/full-vec-move1.c:
Adjust dg-do to comiple for asm checking.
gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/full-vec-move1.c diff | blob | blame | history
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