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(parent: 1bdd665) | patch
Fix ICE generating uniform vector masks
authorAndrew Stubbs <ams@codesourcery.com>
Tue, 14 Nov 2023 16:07:37 +0000 (16:07 +0000)
committerAndrew Stubbs <ams@codesourcery.com>
Tue, 14 Nov 2023 16:46:39 +0000 (16:46 +0000)
commit948b8b6e0e50958ecf56d4d9fb7ac16f245d9cc3
tree793c26179d477114d316de1f196d638740ac790dtree
parent1bdd665a025a74f4f1b641600a8c0bbca3355aa7commit | diff
Fix ICE generating uniform vector masks

Most targets have an "and" instructions for their vector mask size, but RISC-V
only has DImode "and".  Fixed by allowing wider instruction modes.

gcc/ChangeLog:

PR target/112481
* expr.cc (store_constructor): Use OPTAB_WIDEN for mask adjustment.
gcc/expr.cc diff | blob | blame | history
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