]> gcc.gnu.org Git - gcc.git/commit
RISC-V: Support ceil and ceilf auto-vectorization
authorPan Li <pan2.li@intel.com>
Wed, 20 Sep 2023 01:36:22 +0000 (09:36 +0800)
committerPan Li <pan2.li@intel.com>
Fri, 22 Sep 2023 00:49:47 +0000 (08:49 +0800)
commit8bf5636e4fca947527a302813fdf08e1bbc82fa3
tree17b95c795cb733f5b68369e15c96ec3a4bd9c1ae
parentd35e12e1c08992f94d4d43bc8ef16482d200091b
RISC-V: Support ceil and ceilf auto-vectorization

Update in v4:

* Add test for _Float16.
* Remove unnecessary macro in def.h for test.

Original log:

This patch would like to support auto-vectorization for both the
ceil and ceilf of math.h. It depends on the -ffast-math option.

When we would like to call ceil/ceilf like v2 = ceil (v1), we will
convert it into below insn (reference the implementation of llvm).

* vfcvt.x.f v3, v1, RUP
* vfcvt.f.x v2, v3

However, the floating point value may not need the cvt as above if
its mantissa is zero. For example single precision floating point below.

  +-----------+---------------+
  | float     | binary layout |
  +-----------+---------------+
  | 8388607.5 | 0x4affffff    |
  | 8388608.0 | 0x4b000000    |
  | 8388609.0 | 0x4b000001    |
  +-----------+---------------+

All single floating point great than 8388608.0 will have all zero mantisaa.
We leverage vmflt and mask to filter them out in vector and only do the
cvt on mask.

Befor this patch:
math-ceil-1.c:21:1: missed: couldn't vectorize loop
  ...
.L3:
  flw     fa0,0(s0)
  addi    s0,s0,4
  addi    s1,s1,4
  call    ceilf
  fsw     fa0,-4(s1)
  bne     s0,s2,.L3

After this patch:
  ...
  fsrmi   3
.L4:
  vfabs.v     v0,v1
  vmv1r.v     v2,v1
  vmflt.vv    v0,v0,v4
  sub         a3,a3,a4
  vfcvt.x.f.v v3,v1,v0.t
  vfcvt.f.x.v v2,v3,v0.t
  vfsgnj.vv   v2,v2,v1
  bne         .L4
.L14:
  fsrm    a6
  ret

Please note VLS mode is also involved in this patch and covered by the
test cases.

gcc/ChangeLog:

* config/riscv/autovec.md (ceil<mode>2): New pattern.
* config/riscv/riscv-protos.h (enum insn_flags): New enum type.
(enum insn_type): Ditto.
(expand_vec_ceil): New function decl.
* config/riscv/riscv-v.cc (gen_ceil_const_fp): New function impl.
(expand_vec_float_cmp_mask): Ditto.
(expand_vec_copysign): Ditto.
(expand_vec_ceil): Ditto.
* config/riscv/vector.md: Add VLS mode support.

gcc/testsuite/ChangeLog:

* gcc.target/riscv/rvv/autovec/math-ceil-0.c: New test.
* gcc.target/riscv/rvv/autovec/math-ceil-1.c: New test.
* gcc.target/riscv/rvv/autovec/math-ceil-2.c: New test.
* gcc.target/riscv/rvv/autovec/math-ceil-3.c: New test.
* gcc.target/riscv/rvv/autovec/math-ceil-run-0.c: New test.
* gcc.target/riscv/rvv/autovec/math-ceil-run-1.c: New test.
* gcc.target/riscv/rvv/autovec/math-ceil-run-2.c: New test.
* gcc.target/riscv/rvv/autovec/test-math.h: New test.
* gcc.target/riscv/rvv/autovec/vls/math-ceil-1.c: New test.

Signed-off-by: Pan Li <pan2.li@intel.com>
13 files changed:
gcc/config/riscv/autovec.md
gcc/config/riscv/riscv-protos.h
gcc/config/riscv/riscv-v.cc
gcc/config/riscv/vector.md
gcc/testsuite/gcc.target/riscv/rvv/autovec/math-ceil-0.c [new file with mode: 0644]
gcc/testsuite/gcc.target/riscv/rvv/autovec/math-ceil-1.c [new file with mode: 0644]
gcc/testsuite/gcc.target/riscv/rvv/autovec/math-ceil-2.c [new file with mode: 0644]
gcc/testsuite/gcc.target/riscv/rvv/autovec/math-ceil-3.c [new file with mode: 0644]
gcc/testsuite/gcc.target/riscv/rvv/autovec/math-ceil-run-0.c [new file with mode: 0644]
gcc/testsuite/gcc.target/riscv/rvv/autovec/math-ceil-run-1.c [new file with mode: 0644]
gcc/testsuite/gcc.target/riscv/rvv/autovec/math-ceil-run-2.c [new file with mode: 0644]
gcc/testsuite/gcc.target/riscv/rvv/autovec/test-math.h [new file with mode: 0644]
gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/math-ceil-1.c [new file with mode: 0644]
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