RISC-V/testsuite: constraint some of tests to hard_float

RISC-V/testsuite: constraint some of tests to hard_float

Commit 9ddd44b58649d1d ("RISC-V: Provide `fmin'/`fmax' RTL pattern") added
tests which check for hard float instructions which obviously fails on
soft-float ABI builds.

And my recent commit b646d7d279ae ("RISC-V: Inhibit FP <--> int register
moves via tune param") is guilty of same crime.

So constraint with "dg-require-effective-target hard_float"

This reduces bunch of new RV failures.

|               ========= Summary of gcc testsuite =========
|                            | # of unexpected case / # of unique unexpected case
|                            |          gcc |          g++ |     gfortran |
|   rv64imac/   lp64/ medlow |  134 /    22 |    0 /     0 |            - |  BEFORE
|   rv64imac/   lp64/ medlow |   22 /     9 |    0 /     0 |            - |  AFTER
|

gcc/testsuite/Changelog:
	* gcc.target/riscv/fmax.c: Add dg-require-effective-target hard_float.
	* gcc.target/riscv/fmaxf.c: Ditto.
	* gcc.target/riscv/fmin.c: Ditto.
	* gcc.target/riscv/fminf.c: Ditto.
	* gcc.target/riscv/smax-ieee.c: Ditto.
	* gcc.target/riscv/smax.c: Ditto.
	* gcc.target/riscv/smaxf-ieee.c: Ditto.
	* gcc.target/riscv/smaxf.c: Ditto.
	* gcc.target/riscv/smin-ieee.c: Ditto.
	* gcc.target/riscv/smin.c: Ditto.
	* gcc.target/riscv/sminf-ieee.c: Ditto.
	* gcc.target/riscv/sminf.c: Ditto.
	* gcc.target/riscv/pr105666.c: Ditto.

Signed-off-by: Vineet Gupta <vineetg@rivosinc.com>