RISC-V: Make SHA-256, SM3 and SM4 builtins operate on uint32_t

RISC-V: Make SHA-256, SM3 and SM4 builtins operate on uint32_t

This is in parity with the LLVM commit a64b3e92c7cb ("[RISCV] Re-define
sha256, Zksed, and Zksh intrinsics to use i32 types.").

SHA-256, SM3 and SM4 instructions operate on 32-bit integers and upper
32-bits have no effects on RV64 (the output is sign-extended from the
original 32-bit value).  In that sense, making those intrinsics only
operate on uint32_t is much more natural than XLEN-bits wide integers.

This commit reforms instructions and expansions based on 32-bit
instruction handling on RV64 (such as ADDW).

Before:
   riscv_<op>_si: For RV32, fully operate on uint32_t
   riscv_<op>_di: For RV64, fully operate on uint64_t
After:
  *riscv_<op>_si: For RV32, fully operate on uint32_t
   riscv_<op>_di_extended:
                  For RV64.  Input is uint32_t and output is int64_t,
                  sign-extended from the int32_t result
                  (represents a part of <op> behavior).
   riscv_<op>_si: Common (fully operate on uint32_t).
                  On RV32, "expands" to *riscv_<op>_si.
                  On RV64, initially expands to riscv_<op>_di_extended *and*
                  extracts lower 32-bits from the int64_t result.

It also refines definitions of SHA-256, SM3 and SM4 intrinsics.

gcc/ChangeLog:

	* config/riscv/crypto.md (riscv_sha256sig0_<mode>,
	riscv_sha256sig1_<mode>, riscv_sha256sum0_<mode>,
	riscv_sha256sum1_<mode>, riscv_sm3p0_<mode>, riscv_sm3p1_<mode>,
	riscv_sm4ed_<mode>, riscv_sm4ks_<mode>): Remove and replace with
	new insn/expansions.
	(SHA256_OP, SM3_OP, SM4_OP): New iterators.
	(sha256_op, sm3_op, sm4_op): New attributes for iteration.
	(*riscv_<sha256_op>_si): New raw instruction for RV32.
	(*riscv_<sm3_op>_si): Ditto.
	(*riscv_<sm4_op>_si): Ditto.
	(riscv_<sha256_op>_di_extended): New base instruction for RV64.
	(riscv_<sm3_op>_di_extended): Ditto.
	(riscv_<sm4_op>_di_extended): Ditto.
	(riscv_<sha256_op>_si): New common instruction expansion.
	(riscv_<sm3_op>_si): Ditto.
	(riscv_<sm4_op>_si): Ditto.
	* config/riscv/riscv-builtins.cc: Add availability "crypto_zknh",
	"crypto_zksh" and "crypto_zksed".  Remove availability
	"crypto_zksh{32,64}" and "crypto_zksed{32,64}".
	* config/riscv/riscv-ftypes.def: Remove unused function type.
	* config/riscv/riscv-scalar-crypto.def: Make SHA-256, SM3 and SM4
	intrinsics to operate on uint32_t.

gcc/testsuite/ChangeLog:

	* gcc.target/riscv/zknh-sha256.c: Moved to...
	* gcc.target/riscv/zknh-sha256-64.c: ...here.  Test RV64.
	* gcc.target/riscv/zknh-sha256-32.c: New test for RV32.
	* gcc.target/riscv/zksh64.c: Change the type.
	* gcc.target/riscv/zksed64.c: Ditto.

(cherry picked from commit 9882b81410f247604fbfd5883894a96127f461ac)