AArch64: Add pattern xtn+xtn2 to uzp1

AArch64: Add pattern xtn+xtn2 to uzp1

This turns truncate operations with a hi/lo pair into a single permute of half
the bit size of the input and just ignoring the top bits (which are truncated
out).

i.e.

void d2 (short * restrict a, int *b, int n)
{
    for (int i = 0; i < n; i++)
      a[i] = b[i];
}

now generates:

.L4:
        ldp     q0, q1, [x3]
        add     x3, x3, 32
        uzp1    v0.8h, v0.8h, v1.8h
        str     q0, [x5], 16
        cmp     x4, x3
        bne     .L4

instead of

.L4:
        ldp     q0, q1, [x3]
        add     x3, x3, 32
        xtn     v0.4h, v0.4s
        xtn2    v0.8h, v1.4s
        str     q0, [x5], 16
        cmp     x4, x3
        bne     .L4

gcc/ChangeLog:

	* config/aarch64/aarch64-simd.md (*aarch64_narrow_trunc<mode>): New.

gcc/testsuite/ChangeLog:

	* gcc.target/aarch64/narrow_high_combine.c: Update case.
	* gcc.target/aarch64/xtn-combine-1.c: New test.
	* gcc.target/aarch64/xtn-combine-2.c: New test.
	* gcc.target/aarch64/xtn-combine-3.c: New test.
	* gcc.target/aarch64/xtn-combine-4.c: New test.
	* gcc.target/aarch64/xtn-combine-5.c: New test.
	* gcc.target/aarch64/xtn-combine-6.c: New test.