RISC-V: Add more tests for RVV floating-point FRM.

RISC-V: Add more tests for RVV floating-point FRM.

Add more test cases include both the asm check and run for RVV FRM.

Signed-off-by: Pan Li <pan2.li@intel.com>
gcc/testsuite/ChangeLog:

	* gcc.target/riscv/rvv/base/float-point-frm-insert-10.c: New test.
	* gcc.target/riscv/rvv/base/float-point-frm-insert-7.c: New test.
	* gcc.target/riscv/rvv/base/float-point-frm-insert-8.c: New test.
	* gcc.target/riscv/rvv/base/float-point-frm-insert-9.c: New test.
	* gcc.target/riscv/rvv/base/float-point-frm-run-1.c: New test.
	* gcc.target/riscv/rvv/base/float-point-frm-run-2.c: New test.
	* gcc.target/riscv/rvv/base/float-point-frm-run-3.c: New test.