RISC-V: Allow any temp register to be used in amo tests

RISC-V: Allow any temp register to be used in amo tests

We artifically restrict the temp registers to be a[0-9]+ when other
registers like t[0-9]+ are valid too. Update to make the regex
accept any register for the temp value.

gcc/testsuite/ChangeLog:

	* gcc.target/riscv/amo/amo-table-a-6-load-1.c: Update temp register regex.
	* gcc.target/riscv/amo/amo-table-a-6-load-2.c: Ditto.
	* gcc.target/riscv/amo/amo-table-a-6-load-3.c: Ditto.
	* gcc.target/riscv/amo/amo-table-a-6-store-1.c: Ditto.
	* gcc.target/riscv/amo/amo-table-a-6-store-2.c: Ditto.
	* gcc.target/riscv/amo/amo-table-a-6-store-compat-3.c: Ditto.
	* gcc.target/riscv/amo/amo-table-ztso-load-1.c: Ditto.
	* gcc.target/riscv/amo/amo-table-ztso-load-2.c: Ditto.
	* gcc.target/riscv/amo/amo-table-ztso-load-3.c: Ditto.
	* gcc.target/riscv/amo/amo-table-ztso-store-1.c: Ditto.
	* gcc.target/riscv/amo/amo-table-ztso-store-2.c: Ditto.
	* gcc.target/riscv/amo/amo-table-ztso-store-3.c: Ditto.

Signed-off-by: Patrick O'Neill <patrick@rivosinc.com>