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RISC-V: Remove masking third operand of rotate instructions
authorJoern Rennecke <joern.rennecke@embecosm.com>
Fri, 19 May 2023 22:18:42 +0000 (16:18 -0600)
committerJeff Law <jlaw@ventanamicro.com>
Fri, 14 Jul 2023 02:05:24 +0000 (20:05 -0600)
commit3ac3d5adb35760d6fd7e638b7113044fdd8e8009
tree83aa4c6a21e8e6ffc510bb8697050d15ae4a49c4tree
parent17a61c57eb16d94915753061ab3bff31818a15afcommit | diff
RISC-V: Remove masking third operand of rotate instructions

Sorry, I forgot the ChangeLog entry for my patch and missed the [v2]
part of the subject.

2023-05-18  Joern Rennecke  <joern.rennecke@embecosm.com>

gcc/ChangeLog:
* config/riscv/constraints.md (DsS, DsD): Restore agreement
with shiftm1 mode attribute.
gcc/config/riscv/constraints.md diff | blob | blame | history
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