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arm testsuite: Shifts and get_FPSCR ACLE optimisation fixes
authorStam Markianos-Wright <stam.markianos-wright@arm.com>
Thu, 27 Apr 2023 14:55:24 +0000 (15:55 +0100)
committerStam Markianos-Wright <stam.markianos-wright@arm.com>
Thu, 18 May 2023 10:12:17 +0000 (11:12 +0100)
commit340cd371d63434829b7793bf4fe9d91bf58f77ec
treecd65fd2e3c3806f21fa6d85af94a019f3487b2bb
parent7587c2e3844baf26255a7cc6e1d291240a1c28d3
arm testsuite: Shifts and get_FPSCR ACLE optimisation fixes

These newly updated tests were rewritten by Andrea. Some of them
needed further manual fixing as follows:

* The #shift immediate value not in the check-function-bodies as expected
* The ACLE was specifying sub-optimal code: lsr+and instead of ubfx. In
  this case the test rewritten from the ACLE had the lsr+and pattern,
  but the compiler was able to optimise to ubfx. Hence I've changed the
  test to now match on ubfx.
* Added a separate test to check shift on constants being optimised to
  movs.

gcc/testsuite/ChangeLog:

* gcc.target/arm/mve/intrinsics/srshr.c: Update shift value.
* gcc.target/arm/mve/intrinsics/srshrl.c: Update shift value.
* gcc.target/arm/mve/intrinsics/uqshl.c: Update shift value.
* gcc.target/arm/mve/intrinsics/uqshll.c: Update shift value.
* gcc.target/arm/mve/intrinsics/urshr.c: Update shift value.
* gcc.target/arm/mve/intrinsics/urshrl.c: Update shift value.
* gcc.target/arm/mve/intrinsics/vadciq_m_s32.c: Update to ubfx.
* gcc.target/arm/mve/intrinsics/vadciq_m_u32.c: Update to ubfx.
* gcc.target/arm/mve/intrinsics/vadciq_s32.c: Update to ubfx.
* gcc.target/arm/mve/intrinsics/vadciq_u32.c: Update to ubfx.
* gcc.target/arm/mve/intrinsics/vadcq_m_s32.c: Update to ubfx.
* gcc.target/arm/mve/intrinsics/vadcq_m_u32.c: Update to ubfx.
* gcc.target/arm/mve/intrinsics/vadcq_s32.c: Update to ubfx.
* gcc.target/arm/mve/intrinsics/vadcq_u32.c: Update to ubfx.
* gcc.target/arm/mve/intrinsics/vsbciq_m_s32.c: Update to ubfx.
* gcc.target/arm/mve/intrinsics/vsbciq_m_u32.c: Update to ubfx.
* gcc.target/arm/mve/intrinsics/vsbciq_s32.c: Update to ubfx.
* gcc.target/arm/mve/intrinsics/vsbciq_u32.c: Update to ubfx.
* gcc.target/arm/mve/intrinsics/vsbcq_m_s32.c: Update to ubfx.
* gcc.target/arm/mve/intrinsics/vsbcq_m_u32.c: Update to ubfx.
* gcc.target/arm/mve/intrinsics/vsbcq_s32.c: Update to ubfx.
* gcc.target/arm/mve/intrinsics/vsbcq_u32.c: Update to ubfx.
* gcc.target/arm/mve/mve_const_shifts.c: New test.
23 files changed:
gcc/testsuite/gcc.target/arm/mve/intrinsics/srshr.c
gcc/testsuite/gcc.target/arm/mve/intrinsics/srshrl.c
gcc/testsuite/gcc.target/arm/mve/intrinsics/uqshl.c
gcc/testsuite/gcc.target/arm/mve/intrinsics/uqshll.c
gcc/testsuite/gcc.target/arm/mve/intrinsics/urshr.c
gcc/testsuite/gcc.target/arm/mve/intrinsics/urshrl.c
gcc/testsuite/gcc.target/arm/mve/intrinsics/vadciq_m_s32.c
gcc/testsuite/gcc.target/arm/mve/intrinsics/vadciq_m_u32.c
gcc/testsuite/gcc.target/arm/mve/intrinsics/vadciq_s32.c
gcc/testsuite/gcc.target/arm/mve/intrinsics/vadciq_u32.c
gcc/testsuite/gcc.target/arm/mve/intrinsics/vadcq_m_s32.c
gcc/testsuite/gcc.target/arm/mve/intrinsics/vadcq_m_u32.c
gcc/testsuite/gcc.target/arm/mve/intrinsics/vadcq_s32.c
gcc/testsuite/gcc.target/arm/mve/intrinsics/vadcq_u32.c
gcc/testsuite/gcc.target/arm/mve/intrinsics/vsbciq_m_s32.c
gcc/testsuite/gcc.target/arm/mve/intrinsics/vsbciq_m_u32.c
gcc/testsuite/gcc.target/arm/mve/intrinsics/vsbciq_s32.c
gcc/testsuite/gcc.target/arm/mve/intrinsics/vsbciq_u32.c
gcc/testsuite/gcc.target/arm/mve/intrinsics/vsbcq_m_s32.c
gcc/testsuite/gcc.target/arm/mve/intrinsics/vsbcq_m_u32.c
gcc/testsuite/gcc.target/arm/mve/intrinsics/vsbcq_s32.c
gcc/testsuite/gcc.target/arm/mve/intrinsics/vsbcq_u32.c
gcc/testsuite/gcc.target/arm/mve/mve_const_shifts.c [new file with mode: 0644]
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