RISC-V: Handle undef for vector mask patterns

[gcc.git] / gcc / testsuite / gcc.target / riscv / rvv / base / binop_vv_constraint-6.c

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vv_constraint-6.c b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vv_constraint-6.c
index ad5441f3404a017bee131ddddf82b92a2f7cc57c..384e2301a69bb683654a71bce1802f4eb6d87382 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vv_constraint-6.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vv_constraint-6.c
@@ -24,4 +24,4 @@ void f2 (void * in, void *out, int32_t x)
     __riscv_vsm_v_b32 (out, m4, 4);
 }
 
-/* { dg-final { scan-assembler-times {vmv} 2 } } */
+